1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SYSCTRL</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>BSTAPEN</name> 21 <description>Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE.</description> 22 <bitOffset>1</bitOffset> 23 <bitWidth>1</bitWidth> 24 </field> 25 <field> 26 <name>FLASH_PAGE_FLIP</name> 27 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 28 <bitOffset>4</bitOffset> 29 <bitWidth>1</bitWidth> 30 <enumeratedValues> 31 <enumeratedValue> 32 <name>normal</name> 33 <description>Physical layout matches logical layout.</description> 34 <value>0</value> 35 </enumeratedValue> 36 <enumeratedValue> 37 <name>swapped</name> 38 <description>Bottom half mapped to logical top half and vice versa.</description> 39 <value>1</value> 40 </enumeratedValue> 41 </enumeratedValues> 42 </field> 43 <field> 44 <name>ICC0_FLUSH</name> 45 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 46 <bitOffset>6</bitOffset> 47 <bitWidth>1</bitWidth> 48 <enumeratedValues> 49 <enumeratedValue> 50 <name>normal</name> 51 <description>Normal Code Cache Operation</description> 52 <value>0</value> 53 </enumeratedValue> 54 <enumeratedValue> 55 <name>flush</name> 56 <description>Code Caches and CPU instruction buffer are flushed </description> 57 <value>1</value> 58 </enumeratedValue> 59 </enumeratedValues> 60 </field> 61 <field> 62 <name>ROMDONE</name> 63 <description>ROM_DONE status. Used to disable SWD interface during system initialization procedure</description> 64 <bitOffset>12</bitOffset> 65 <bitWidth>1</bitWidth> 66 </field> 67 <field> 68 <name>CCHK</name> 69 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 70 <bitOffset>13</bitOffset> 71 <bitWidth>1</bitWidth> 72 <enumeratedValues> 73 <enumeratedValue> 74 <name>complete</name> 75 <description>No operation/complete.</description> 76 <value>0</value> 77 </enumeratedValue> 78 <enumeratedValue> 79 <name>start</name> 80 <description>Start operation.</description> 81 <value>1</value> 82 </enumeratedValue> 83 </enumeratedValues> 84 </field> 85 <field> 86 <name>SWD_DIS</name> 87 <description> Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set).</description> 88 <bitOffset>14</bitOffset> 89 <bitWidth>1</bitWidth> 90 </field> 91 <field> 92 <name>CHKRES</name> 93 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 94 <bitOffset>15</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>pass</name> 99 <description>ROM Checksum Correct.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>fail</name> 104 <description>ROM Checksum Fail.</description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>OVR</name> 111 <description>Operating Voltage Range.</description> 112 <bitOffset>16</bitOffset> 113 <bitWidth>2</bitWidth> 114 </field> 115 </fields> 116 </register> 117 <register> 118 <name>RST0</name> 119 <description>Reset.</description> 120 <addressOffset>0x04</addressOffset> 121 <fields> 122 <field> 123 <name>DMA</name> 124 <description>DMA Reset.</description> 125 <bitOffset>0</bitOffset> 126 <bitWidth>1</bitWidth> 127 <enumeratedValues> 128 <name>reset</name> 129 <usage>read-write</usage> 130 <enumeratedValue> 131 <name>reset_done</name> 132 <description>Reset complete.</description> 133 <value>0</value> 134 </enumeratedValue> 135 <enumeratedValue> 136 <name>busy</name> 137 <description>Starts Reset or indicates reset in progress.</description> 138 <value>1</value> 139 </enumeratedValue> 140 </enumeratedValues> 141 </field> 142 <field derivedFrom="DMA"> 143 <name>WDT0</name> 144 <description>Watchdog Timer 0 Reset.</description> 145 <bitOffset>1</bitOffset> 146 <bitWidth>1</bitWidth> 147 </field> 148 <field derivedFrom="DMA"> 149 <name>GPIO0</name> 150 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 151 <bitOffset>2</bitOffset> 152 <bitWidth>1</bitWidth> 153 </field> 154 <field derivedFrom="DMA"> 155 <name>GPIO1</name> 156 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 157 <bitOffset>3</bitOffset> 158 <bitWidth>1</bitWidth> 159 </field> 160 <field derivedFrom="DMA"> 161 <name>TMR0</name> 162 <description>Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 163 <bitOffset>5</bitOffset> 164 <bitWidth>1</bitWidth> 165 </field> 166 <field derivedFrom="DMA"> 167 <name>TMR1</name> 168 <description>Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 169 <bitOffset>6</bitOffset> 170 <bitWidth>1</bitWidth> 171 </field> 172 <field derivedFrom="DMA"> 173 <name>TMR2</name> 174 <description>Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 175 <bitOffset>7</bitOffset> 176 <bitWidth>1</bitWidth> 177 </field> 178 <field derivedFrom="DMA"> 179 <name>TMR3</name> 180 <description>Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 181 <bitOffset>8</bitOffset> 182 <bitWidth>1</bitWidth> 183 </field> 184 <field derivedFrom="DMA"> 185 <name>UART0</name> 186 <description>UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 187 <bitOffset>11</bitOffset> 188 <bitWidth>1</bitWidth> 189 </field> 190 <field derivedFrom="DMA"> 191 <name>UART1</name> 192 <description>UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 193 <bitOffset>12</bitOffset> 194 <bitWidth>1</bitWidth> 195 </field> 196 <field derivedFrom="DMA"> 197 <name>SPI1</name> 198 <description>SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 199 <bitOffset>13</bitOffset> 200 <bitWidth>1</bitWidth> 201 </field> 202 <field derivedFrom="DMA"> 203 <name>I2C0</name> 204 <description>I2C 0 Reset.</description> 205 <bitOffset>16</bitOffset> 206 <bitWidth>1</bitWidth> 207 </field> 208 <field derivedFrom="DMA"> 209 <name>RTC</name> 210 <description>Real Time Clock Reset.</description> 211 <bitOffset>17</bitOffset> 212 <bitWidth>1</bitWidth> 213 </field> 214 <field derivedFrom="DMA"> 215 <name>SMPHR</name> 216 <description>Semaphore Reset.</description> 217 <bitOffset>22</bitOffset> 218 <bitWidth>1</bitWidth> 219 </field> 220 <field derivedFrom="DMA"> 221 <name>TRNG</name> 222 <description>TRNG Reset. This reset is only available during the manufacture testing phase.</description> 223 <bitOffset>24</bitOffset> 224 <bitWidth>1</bitWidth> 225 </field> 226 <field derivedFrom="DMA"> 227 <name>CNN</name> 228 <description>CNN Reset.</description> 229 <bitOffset>25</bitOffset> 230 <bitWidth>1</bitWidth> 231 </field> 232 <field derivedFrom="DMA"> 233 <name>ADC</name> 234 <description>ADC Reset.</description> 235 <bitOffset>26</bitOffset> 236 <bitWidth>1</bitWidth> 237 </field> 238 <field derivedFrom="DMA"> 239 <name>UART2</name> 240 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 241 <bitOffset>28</bitOffset> 242 <bitWidth>1</bitWidth> 243 </field> 244 <field derivedFrom="DMA"> 245 <name>SOFT</name> 246 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 247 <bitOffset>29</bitOffset> 248 <bitWidth>1</bitWidth> 249 </field> 250 <field derivedFrom="DMA"> 251 <name>PERIPH</name> 252 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 253 <bitOffset>30</bitOffset> 254 <bitWidth>1</bitWidth> 255 </field> 256 <field derivedFrom="DMA"> 257 <name>SYS</name> 258 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 259 <bitOffset>31</bitOffset> 260 <bitWidth>1</bitWidth> 261 </field> 262 </fields> 263 </register> 264 <register> 265 <name>CLKCTRL</name> 266 <description>Clock Control.</description> 267 <addressOffset>0x08</addressOffset> 268 <resetValue>0x00000008</resetValue> 269 <fields> 270 <field> 271 <name>SYSCLK_DIV</name> 272 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 273 <bitOffset>6</bitOffset> 274 <bitWidth>3</bitWidth> 275 <enumeratedValues> 276 <enumeratedValue> 277 <name>div1</name> 278 <description>Divide by 1.</description> 279 <value>0</value> 280 </enumeratedValue> 281 <enumeratedValue> 282 <name>div2</name> 283 <description>Divide by 2.</description> 284 <value>1</value> 285 </enumeratedValue> 286 <enumeratedValue> 287 <name>div4</name> 288 <description>Divide by 4.</description> 289 <value>2</value> 290 </enumeratedValue> 291 <enumeratedValue> 292 <name>div8</name> 293 <description>Divide by 8.</description> 294 <value>3</value> 295 </enumeratedValue> 296 <enumeratedValue> 297 <name>div16</name> 298 <description>Divide by 16.</description> 299 <value>4</value> 300 </enumeratedValue> 301 <enumeratedValue> 302 <name>div32</name> 303 <description>Divide by 32.</description> 304 <value>5</value> 305 </enumeratedValue> 306 <enumeratedValue> 307 <name>div64</name> 308 <description>Divide by 64.</description> 309 <value>6</value> 310 </enumeratedValue> 311 <enumeratedValue> 312 <name>div128</name> 313 <description>Divide by 128.</description> 314 <value>7</value> 315 </enumeratedValue> 316 </enumeratedValues> 317 </field> 318 <field> 319 <name>SYSCLK_SEL</name> 320 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 321 <bitOffset>9</bitOffset> 322 <bitWidth>3</bitWidth> 323 <enumeratedValues> 324 <enumeratedValue> 325 <name>ISO</name> 326 <description>The internal 60 MHz oscillator is used for the system clock.</description> 327 <value>0</value> 328 </enumeratedValue> 329 <enumeratedValue> 330 <name>ERFO</name> 331 <description>32MHz Crystal is used for the system clock.</description> 332 <value>2</value> 333 </enumeratedValue> 334 <enumeratedValue> 335 <name>INRO</name> 336 <description>8 kHz LIRC is used for the system clock.</description> 337 <value>3</value> 338 </enumeratedValue> 339 <enumeratedValue> 340 <name>IPO</name> 341 <description>The internal 96 MHz oscillator is used for the system clock.</description> 342 <value>4</value> 343 </enumeratedValue> 344 <enumeratedValue> 345 <name>IBRO</name> 346 <description>The internal 7.3725 MHz oscillator is used for the system clock.</description> 347 <value>5</value> 348 </enumeratedValue> 349 <enumeratedValue> 350 <name>ERTCO</name> 351 <description> 32 kHz is used for the system clock.</description> 352 <value>6</value> 353 </enumeratedValue> 354 <enumeratedValue> 355 <name>EXTCLK</name> 356 <description> External clock on GPIO0.30.</description> 357 <value>7</value> 358 </enumeratedValue> 359 </enumeratedValues> 360 </field> 361 <field> 362 <name>SYSCLK_RDY</name> 363 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 364 <bitOffset>13</bitOffset> 365 <bitWidth>1</bitWidth> 366 <access>read-only</access> 367 <enumeratedValues> 368 <enumeratedValue> 369 <name>busy</name> 370 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 371 <value>0</value> 372 </enumeratedValue> 373 <enumeratedValue> 374 <name>ready</name> 375 <description>System clock running from CLKSEL clock source.</description> 376 <value>1</value> 377 </enumeratedValue> 378 </enumeratedValues> 379 </field> 380 <field> 381 <name>ERFO_EN</name> 382 <description>32MHz Crystal Oscillator Enable.</description> 383 <bitOffset>16</bitOffset> 384 <bitWidth>1</bitWidth> 385 <enumeratedValues> 386 <enumeratedValue> 387 <name>dis</name> 388 <description>Is Disabled.</description> 389 <value>0</value> 390 </enumeratedValue> 391 <enumeratedValue> 392 <name>en</name> 393 <description>Is Enabled.</description> 394 <value>1</value> 395 </enumeratedValue> 396 </enumeratedValues> 397 </field> 398 <field> 399 <name>ERTCO_EN</name> 400 <description>32 kHz Crystal Oscillator Enable.</description> 401 <bitOffset>17</bitOffset> 402 <bitWidth>1</bitWidth> 403 <enumeratedValues> 404 <enumeratedValue> 405 <name>dis</name> 406 <description>Is Disabled.</description> 407 <value>0</value> 408 </enumeratedValue> 409 <enumeratedValue> 410 <name>en</name> 411 <description>Is Enabled.</description> 412 <value>1</value> 413 </enumeratedValue> 414 </enumeratedValues> 415 </field> 416 <field derivedFrom="ERTCO_EN"> 417 <name>ISO_EN</name> 418 <description>60 MHz High Frequency Internal Reference Clock Enable.</description> 419 <bitOffset>18</bitOffset> 420 <bitWidth>1</bitWidth> 421 </field> 422 <field derivedFrom="ERTCO_EN"> 423 <name>IPO_EN</name> 424 <description>100 MHz High Frequency Internal Reference Clock Enable.</description> 425 <bitOffset>19</bitOffset> 426 <bitWidth>1</bitWidth> 427 </field> 428 <field derivedFrom="ERTCO_EN"> 429 <name>IBRO_EN</name> 430 <description>7.3725 MHz High Frequency Internal Reference Clock Enable.</description> 431 <bitOffset>20</bitOffset> 432 <bitWidth>1</bitWidth> 433 </field> 434 <field> 435 <name>IBRO_VS</name> 436 <description>7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.</description> 437 <bitOffset>21</bitOffset> 438 <bitWidth>1</bitWidth> 439 <enumeratedValues> 440 <enumeratedValue> 441 <name>Vcor</name> 442 <description>VCore Supply</description> 443 <value>0</value> 444 </enumeratedValue> 445 <enumeratedValue> 446 <name>1V</name> 447 <description>Dedicated 1V regulated supply.</description> 448 <value>1</value> 449 </enumeratedValue> 450 </enumeratedValues> 451 </field> 452 <field> 453 <name>ERFO_RDY</name> 454 <description>32MHz Crystal Oscillator Ready</description> 455 <bitOffset>24</bitOffset> 456 <bitWidth>1</bitWidth> 457 <access>read-only</access> 458 <enumeratedValues> 459 <enumeratedValue> 460 <name>not</name> 461 <description>Is not Ready.</description> 462 <value>0</value> 463 </enumeratedValue> 464 <enumeratedValue> 465 <name>ready</name> 466 <description>Is Ready.</description> 467 <value>1</value> 468 </enumeratedValue> 469 </enumeratedValues> 470 </field> 471 <field> 472 <name>ERTCO_RDY</name> 473 <description>32 kHz Crystal Oscillator Ready</description> 474 <bitOffset>25</bitOffset> 475 <bitWidth>1</bitWidth> 476 <access>read-only</access> 477 <enumeratedValues> 478 <enumeratedValue> 479 <name>not</name> 480 <description>Is not Ready.</description> 481 <value>0</value> 482 </enumeratedValue> 483 <enumeratedValue> 484 <name>ready</name> 485 <description>Is Ready.</description> 486 <value>1</value> 487 </enumeratedValue> 488 </enumeratedValues> 489 </field> 490 <field derivedFrom="ERTCO_RDY"> 491 <name>ISO_RDY</name> 492 <description>60 MHz HIRC Ready.</description> 493 <bitOffset>26</bitOffset> 494 <bitWidth>1</bitWidth> 495 </field> 496 <field derivedFrom="ERTCO_RDY"> 497 <name>IPO_RDY</name> 498 <description>100 MHz HIRC Ready.</description> 499 <bitOffset>27</bitOffset> 500 <bitWidth>1</bitWidth> 501 </field> 502 <field derivedFrom="ERTCO_RDY"> 503 <name>IBRO_RDY</name> 504 <description>7.3725 MHz HIRC Ready.</description> 505 <bitOffset>28</bitOffset> 506 <bitWidth>1</bitWidth> 507 </field> 508 <field derivedFrom="ERTCO_RDY"> 509 <name>INRO_RDY</name> 510 <description>8 kHz Low Frequency Reference Clock Ready.</description> 511 <bitOffset>29</bitOffset> 512 <bitWidth>1</bitWidth> 513 </field> 514 </fields> 515 </register> 516 <register> 517 <name>PM</name> 518 <description>Power Management.</description> 519 <addressOffset>0x0C</addressOffset> 520 <fields> 521 <field> 522 <name>MODE</name> 523 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 524 <bitOffset>0</bitOffset> 525 <bitWidth>4</bitWidth> 526 <enumeratedValues> 527 <enumeratedValue> 528 <name>active</name> 529 <description>Active Mode.</description> 530 <value>0</value> 531 </enumeratedValue> 532 <enumeratedValue> 533 <name>sleep</name> 534 <description>Cortex-M4 Active, RISC-V Sleep Mode.</description> 535 <value>1</value> 536 </enumeratedValue> 537 <enumeratedValue> 538 <name>standby</name> 539 <description>Standby Mode.</description> 540 <value>2</value> 541 </enumeratedValue> 542 <enumeratedValue> 543 <name>backup</name> 544 <description>Backup Mode.</description> 545 <value>4</value> 546 </enumeratedValue> 547 <enumeratedValue> 548 <name>lpm</name> 549 <description>LPM or CM4 Deep Sleep Mode.</description> 550 <value>8</value> 551 </enumeratedValue> 552 <enumeratedValue> 553 <name>upm</name> 554 <description>UPM.</description> 555 <value>9</value> 556 </enumeratedValue> 557 <enumeratedValue> 558 <name>powerdown</name> 559 <description>Power Down Mode.</description> 560 <value>10</value> 561 </enumeratedValue> 562 </enumeratedValues> 563 </field> 564 <field> 565 <name>GPIO_WE</name> 566 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 567 <bitOffset>4</bitOffset> 568 <bitWidth>1</bitWidth> 569 <enumeratedValues> 570 <enumeratedValue> 571 <name>dis</name> 572 <description>Wake Up Disable.</description> 573 <value>0</value> 574 </enumeratedValue> 575 <enumeratedValue> 576 <name>en</name> 577 <description>Wake Up Enable.</description> 578 <value>1</value> 579 </enumeratedValue> 580 </enumeratedValues> 581 </field> 582 <field derivedFrom="GPIO_WE"> 583 <name>RTC_WE</name> 584 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 585 <bitOffset>5</bitOffset> 586 <bitWidth>1</bitWidth> 587 </field> 588 <field derivedFrom="GPIO_WE"> 589 <name>WUT_WE</name> 590 <description>WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source. </description> 591 <bitOffset>7</bitOffset> 592 <bitWidth>1</bitWidth> 593 </field> 594 <field derivedFrom="GPIO_WE"> 595 <name>AINCOMP_WE</name> 596 <description>AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source. </description> 597 <bitOffset>9</bitOffset> 598 <bitWidth>1</bitWidth> 599 </field> 600 <field> 601 <name>ISO_PD</name> 602 <description>60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode.</description> 603 <bitOffset>15</bitOffset> 604 <bitWidth>1</bitWidth> 605 <enumeratedValues> 606 <enumeratedValue> 607 <name>active</name> 608 <description>Mode is Active.</description> 609 <value>0</value> 610 </enumeratedValue> 611 <enumeratedValue> 612 <name>deepsleep</name> 613 <description>Powered down in DEEPSLEEP.</description> 614 <value>1</value> 615 </enumeratedValue> 616 </enumeratedValues> 617 </field> 618 <field derivedFrom="ISO_PD"> 619 <name>IPO_PD</name> 620 <description>100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. </description> 621 <bitOffset>16</bitOffset> 622 <bitWidth>1</bitWidth> 623 </field> 624 <field derivedFrom="ISO_PD"> 625 <name>IBRO_PD</name> 626 <description>7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. </description> 627 <bitOffset>17</bitOffset> 628 <bitWidth>1</bitWidth> 629 </field> 630 <field> 631 <name>ERFO_BP</name> 632 <description>32MHz Oscillator Bypass</description> 633 <bitOffset>20</bitOffset> 634 <bitWidth>1</bitWidth> 635 </field> 636 </fields> 637 </register> 638 <register> 639 <name>PCLKDIV</name> 640 <description>Peripheral Clock Divider.</description> 641 <addressOffset>0x18</addressOffset> 642 <resetValue>0x00000001</resetValue> 643 <fields> 644 <field> 645 <name>ADCFRQ</name> 646 <description>ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ)</description> 647 <bitOffset>10</bitOffset> 648 <bitWidth>4</bitWidth> 649 </field> 650 <field> 651 <name>CNNCLKDIV</name> 652 <description>CNN Clock Divider.</description> 653 <bitOffset>14</bitOffset> 654 <bitWidth>3</bitWidth> 655 <enumeratedValues> 656 <enumeratedValue> 657 <name>div2</name> 658 <value>0</value> 659 </enumeratedValue> 660 <enumeratedValue> 661 <name>div4</name> 662 <value>1</value> 663 </enumeratedValue> 664 <enumeratedValue> 665 <name>div8</name> 666 <value>2</value> 667 </enumeratedValue> 668 <enumeratedValue> 669 <name>div16</name> 670 <value>3</value> 671 </enumeratedValue> 672 <enumeratedValue> 673 <name>div1</name> 674 <value>4</value> 675 </enumeratedValue> 676 </enumeratedValues> 677 </field> 678 <field> 679 <name>CNNCLKSEL</name> 680 <description>CNN Clock Select.</description> 681 <bitOffset>17</bitOffset> 682 <bitWidth>1</bitWidth> 683 <enumeratedValues> 684 <enumeratedValue> 685 <name>system</name> 686 <value>0</value> 687 </enumeratedValue> 688 <enumeratedValue> 689 <name>IBRO60</name> 690 <value>1</value> 691 </enumeratedValue> 692 </enumeratedValues> 693 </field> 694 </fields> 695 </register> 696 <register> 697 <name>PCLKDIS0</name> 698 <description>Peripheral Clock Disable.</description> 699 <addressOffset>0x24</addressOffset> 700 <fields> 701 <field> 702 <name>GPIO0</name> 703 <description>GPIO0 Clock Disable.</description> 704 <bitOffset>0</bitOffset> 705 <bitWidth>1</bitWidth> 706 <enumeratedValues> 707 <enumeratedValue> 708 <name>en</name> 709 <description>enable it.</description> 710 <value>0</value> 711 </enumeratedValue> 712 <enumeratedValue> 713 <name>dis</name> 714 <description>disable it.</description> 715 <value>1</value> 716 </enumeratedValue> 717 </enumeratedValues> 718 </field> 719 <field derivedFrom="GPIO0"> 720 <name>GPIO1</name> 721 <description>GPIO1 Clock Disable.</description> 722 <bitOffset>1</bitOffset> 723 <bitWidth>1</bitWidth> 724 </field> 725 <field derivedFrom="GPIO0"> 726 <name>DMA</name> 727 <description>DMA Clock Disable.</description> 728 <bitOffset>5</bitOffset> 729 <bitWidth>1</bitWidth> 730 </field> 731 <field derivedFrom="GPIO0"> 732 <name>SPI1</name> 733 <description>SPI 1 Clock Disable.</description> 734 <bitOffset>6</bitOffset> 735 <bitWidth>1</bitWidth> 736 </field> 737 <field derivedFrom="GPIO0"> 738 <name>UART0</name> 739 <description>UART 0 Clock Disable.</description> 740 <bitOffset>9</bitOffset> 741 <bitWidth>1</bitWidth> 742 </field> 743 <field derivedFrom="GPIO0"> 744 <name>UART1</name> 745 <description>UART 1 Clock Disable.</description> 746 <bitOffset>10</bitOffset> 747 <bitWidth>1</bitWidth> 748 </field> 749 <field derivedFrom="GPIO0"> 750 <name>I2C0</name> 751 <description>I2C 0 Clock Disable.</description> 752 <bitOffset>13</bitOffset> 753 <bitWidth>1</bitWidth> 754 </field> 755 <field derivedFrom="GPIO0"> 756 <name>TMR0</name> 757 <description>Timer 0 Clock Disable.</description> 758 <bitOffset>15</bitOffset> 759 <bitWidth>1</bitWidth> 760 </field> 761 <field derivedFrom="GPIO0"> 762 <name>TMR1</name> 763 <description>Timer 1 Clock Disable.</description> 764 <bitOffset>16</bitOffset> 765 <bitWidth>1</bitWidth> 766 </field> 767 <field derivedFrom="GPIO0"> 768 <name>TMR2</name> 769 <description>Timer 2 Clock Disable.</description> 770 <bitOffset>17</bitOffset> 771 <bitWidth>1</bitWidth> 772 </field> 773 <field derivedFrom="GPIO0"> 774 <name>TMR3</name> 775 <description>Timer 3 Clock Disable.</description> 776 <bitOffset>18</bitOffset> 777 <bitWidth>1</bitWidth> 778 </field> 779 <field derivedFrom="GPIO0"> 780 <name>ADC</name> 781 <description>ADC Clock Disable.</description> 782 <bitOffset>23</bitOffset> 783 <bitWidth>1</bitWidth> 784 </field> 785 <field derivedFrom="GPIO0"> 786 <name>CNN</name> 787 <description>CNN Clock Disable.</description> 788 <bitOffset>25</bitOffset> 789 <bitWidth>1</bitWidth> 790 </field> 791 <field derivedFrom="GPIO0"> 792 <name>I2C1</name> 793 <description>I2C 1 Clock Disable.</description> 794 <bitOffset>28</bitOffset> 795 <bitWidth>1</bitWidth> 796 </field> 797 <field derivedFrom="GPIO0"> 798 <name>PT</name> 799 <description>Pluse Train Clock Disable.</description> 800 <bitOffset>29</bitOffset> 801 <bitWidth>1</bitWidth> 802 </field> 803 </fields> 804 </register> 805 <register> 806 <name>MEMCTRL</name> 807 <description>Memory Clock Control Register.</description> 808 <addressOffset>0x28</addressOffset> 809 <fields> 810 <field> 811 <name>FWS</name> 812 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 813 <bitOffset>0</bitOffset> 814 <bitWidth>3</bitWidth> 815 </field> 816 <field> 817 <name>SYSRAM0ECC</name> 818 <description>SYSRAM0 ECC Select.</description> 819 <bitOffset>16</bitOffset> 820 <bitWidth>1</bitWidth> 821 </field> 822 </fields> 823 </register> 824 <register> 825 <name>MEMZ</name> 826 <description>Memory Zeroize Control.</description> 827 <addressOffset>0x2C</addressOffset> 828 <fields> 829 <field> 830 <name>RAM0</name> 831 <description>System RAM Block 0 Zeroization.</description> 832 <bitOffset>0</bitOffset> 833 <bitWidth>1</bitWidth> 834 <enumeratedValues> 835 <enumeratedValue> 836 <name>nop</name> 837 <description>No operation/complete.</description> 838 <value>0</value> 839 </enumeratedValue> 840 <enumeratedValue> 841 <name>start</name> 842 <description>Start operation.</description> 843 <value>1</value> 844 </enumeratedValue> 845 </enumeratedValues> 846 </field> 847 <field derivedFrom="RAM0"> 848 <name>RAM1</name> 849 <description>System RAM Block 1 Zeroization.</description> 850 <bitOffset>1</bitOffset> 851 <bitWidth>1</bitWidth> 852 </field> 853 <field derivedFrom="RAM0"> 854 <name>RAM2</name> 855 <description>System RAM Block 2 Zeroization.</description> 856 <bitOffset>2</bitOffset> 857 <bitWidth>1</bitWidth> 858 </field> 859 <field derivedFrom="RAM0"> 860 <name>RAM3</name> 861 <description>System RAM Block 3 Zeroization.</description> 862 <bitOffset>3</bitOffset> 863 <bitWidth>1</bitWidth> 864 </field> 865 <field derivedFrom="RAM0"> 866 <name>SYSRAM0ECC</name> 867 <description>System RAM 0 ECC Zeroization.</description> 868 <bitOffset>4</bitOffset> 869 <bitWidth>1</bitWidth> 870 </field> 871 <field derivedFrom="RAM0"> 872 <name>ICC0</name> 873 <description>Instruction Cachei 0 Zeroization.</description> 874 <bitOffset>5</bitOffset> 875 <bitWidth>1</bitWidth> 876 </field> 877 <field derivedFrom="RAM0"> 878 <name>ICC1</name> 879 <description>Instruction Cachei 1 Zeroization.</description> 880 <bitOffset>6</bitOffset> 881 <bitWidth>1</bitWidth> 882 </field> 883 </fields> 884 </register> 885 <register> 886 <name>SYSST</name> 887 <description>System Status Register.</description> 888 <addressOffset>0x40</addressOffset> 889 <fields> 890 <field> 891 <name>ICELOCK</name> 892 <description>ARM ICE Lock Status.</description> 893 <bitOffset>0</bitOffset> 894 <bitWidth>1</bitWidth> 895 <enumeratedValues> 896 <enumeratedValue> 897 <name>unlocked</name> 898 <description>ICE is unlocked.</description> 899 <value>0</value> 900 </enumeratedValue> 901 <enumeratedValue> 902 <name>locked</name> 903 <description>ICE is locked.</description> 904 <value>1</value> 905 </enumeratedValue> 906 </enumeratedValues> 907 </field> 908 </fields> 909 </register> 910 <register> 911 <name>RST1</name> 912 <description>Reset 1.</description> 913 <addressOffset>0x44</addressOffset> 914 <fields> 915 <field> 916 <name>I2C1</name> 917 <description>I2C1 Reset.</description> 918 <bitOffset>0</bitOffset> 919 <bitWidth>1</bitWidth> 920 <enumeratedValues> 921 <name>reset_read</name> 922 <usage>read</usage> 923 <enumeratedValue> 924 <name>reset_done</name> 925 <description>Reset complete.</description> 926 <value>0</value> 927 </enumeratedValue> 928 <enumeratedValue> 929 <name>busy</name> 930 <description>Starts reset or indicates reset in progress.</description> 931 <value>1</value> 932 </enumeratedValue> 933 </enumeratedValues> 934 </field> 935 <field derivedFrom="I2C1"> 936 <name>PT</name> 937 <description>PT Reset.</description> 938 <bitOffset>1</bitOffset> 939 <bitWidth>1</bitWidth> 940 </field> 941 <field derivedFrom="I2C1"> 942 <name>OWM</name> 943 <description>OWM Reset.</description> 944 <bitOffset>7</bitOffset> 945 <bitWidth>1</bitWidth> 946 </field> 947 <field derivedFrom="I2C1"> 948 <name>CRC</name> 949 <description>CRC Reset.</description> 950 <bitOffset>9</bitOffset> 951 <bitWidth>1</bitWidth> 952 </field> 953 <field derivedFrom="I2C1"> 954 <name>AES</name> 955 <description>AES Reset.</description> 956 <bitOffset>10</bitOffset> 957 <bitWidth>1</bitWidth> 958 </field> 959 <field derivedFrom="I2C1"> 960 <name>SPI0</name> 961 <description>SPI 0 Reset.</description> 962 <bitOffset>11</bitOffset> 963 <bitWidth>1</bitWidth> 964 </field> 965 <field derivedFrom="I2C1"> 966 <name>SMPHR</name> 967 <description>SMPHR Reset.</description> 968 <bitOffset>16</bitOffset> 969 <bitWidth>1</bitWidth> 970 </field> 971 <field derivedFrom="I2C1"> 972 <name>I2S</name> 973 <description>I2S Reset.</description> 974 <bitOffset>19</bitOffset> 975 <bitWidth>1</bitWidth> 976 </field> 977 <field derivedFrom="I2C1"> 978 <name>I2C2</name> 979 <description>I2C2 Reset.</description> 980 <bitOffset>20</bitOffset> 981 <bitWidth>1</bitWidth> 982 </field> 983 <field derivedFrom="I2C1"> 984 <name>DVS</name> 985 <description>DVS Reset.</description> 986 <bitOffset>24</bitOffset> 987 <bitWidth>1</bitWidth> 988 </field> 989 <field derivedFrom="I2C1"> 990 <name>SIMO</name> 991 <description>SIMO Reset.</description> 992 <bitOffset>25</bitOffset> 993 <bitWidth>1</bitWidth> 994 </field> 995 <field derivedFrom="I2C1"> 996 <name>CPU1</name> 997 <description>CPU1 Reset.</description> 998 <bitOffset>31</bitOffset> 999 <bitWidth>1</bitWidth> 1000 </field> 1001 </fields> 1002 </register> 1003 <register> 1004 <name>PCLKDIS1</name> 1005 <description>Peripheral Clock Disable.</description> 1006 <addressOffset>0x48</addressOffset> 1007 <fields> 1008 <field> 1009 <name>BTLE</name> 1010 <description>Bluetooth Clock Disable.</description> 1011 <bitOffset>0</bitOffset> 1012 <bitWidth>1</bitWidth> 1013 </field> 1014 <field> 1015 <name>UART2</name> 1016 <description>UART2 Clock Disable.</description> 1017 <bitOffset>1</bitOffset> 1018 <bitWidth>1</bitWidth> 1019 <enumeratedValues> 1020 <enumeratedValue> 1021 <name>en</name> 1022 <description>Enable.</description> 1023 <value>0</value> 1024 </enumeratedValue> 1025 <enumeratedValue> 1026 <name>dis</name> 1027 <description>Disable.</description> 1028 <value>1</value> 1029 </enumeratedValue> 1030 </enumeratedValues> 1031 </field> 1032 <field derivedFrom="UART2"> 1033 <name>TRNG</name> 1034 <description>TRNG Clock Disable.</description> 1035 <bitOffset>2</bitOffset> 1036 <bitWidth>1</bitWidth> 1037 </field> 1038 <field derivedFrom="UART2"> 1039 <name>SMPHR</name> 1040 <description>SMPHR Clock Disable.</description> 1041 <bitOffset>9</bitOffset> 1042 <bitWidth>1</bitWidth> 1043 </field> 1044 <field derivedFrom="UART2"> 1045 <name>OWM</name> 1046 <description>One-Wire Clock Disable.</description> 1047 <bitOffset>13</bitOffset> 1048 <bitWidth>1</bitWidth> 1049 </field> 1050 <field derivedFrom="UART2"> 1051 <name>CRC</name> 1052 <description>CRC Clock Disable.</description> 1053 <bitOffset>14</bitOffset> 1054 <bitWidth>1</bitWidth> 1055 </field> 1056 <field derivedFrom="UART2"> 1057 <name>AES</name> 1058 <description>AES Clock Disable.</description> 1059 <bitOffset>15</bitOffset> 1060 <bitWidth>1</bitWidth> 1061 </field> 1062 <field derivedFrom="UART2"> 1063 <name>SPI0</name> 1064 <description>SPI 0 Clock Disable.</description> 1065 <bitOffset>16</bitOffset> 1066 <bitWidth>1</bitWidth> 1067 </field> 1068 <field derivedFrom="UART2"> 1069 <name>PCIF</name> 1070 <description>Parallel Camera Interface Clock Disable.</description> 1071 <bitOffset>18</bitOffset> 1072 <bitWidth>1</bitWidth> 1073 </field> 1074 <field derivedFrom="UART2"> 1075 <name>I2S</name> 1076 <description>I2S Clock Disable.</description> 1077 <bitOffset>23</bitOffset> 1078 <bitWidth>1</bitWidth> 1079 </field> 1080 <field derivedFrom="UART2"> 1081 <name>I2C2</name> 1082 <description>I2C2 Clock Disable.</description> 1083 <bitOffset>24</bitOffset> 1084 <bitWidth>1</bitWidth> 1085 </field> 1086 <field derivedFrom="UART2"> 1087 <name>WDT0</name> 1088 <description>Watch Dog Timer 0 Clock Disable.</description> 1089 <bitOffset>27</bitOffset> 1090 <bitWidth>1</bitWidth> 1091 </field> 1092 <field derivedFrom="UART2"> 1093 <name>CPU1</name> 1094 <description>CPU1 Clock Disable.</description> 1095 <bitOffset>31</bitOffset> 1096 <bitWidth>1</bitWidth> 1097 </field> 1098 </fields> 1099 </register> 1100 <register> 1101 <name>EVENTEN</name> 1102 <description>Event Enable Register.</description> 1103 <addressOffset>0x4C</addressOffset> 1104 <fields> 1105 <field> 1106 <name>DMA</name> 1107 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 1108 <bitOffset>0</bitOffset> 1109 <bitWidth>1</bitWidth> 1110 </field> 1111 <field> 1112 <name>RX</name> 1113 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO1.8 will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 1114 <bitOffset>1</bitOffset> 1115 <bitWidth>1</bitWidth> 1116 </field> 1117 <field> 1118 <name>TX</name> 1119 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9.</description> 1120 <bitOffset>2</bitOffset> 1121 <bitWidth>1</bitWidth> 1122 </field> 1123 </fields> 1124 </register> 1125 <register> 1126 <name>REVISION</name> 1127 <description>Revision Register.</description> 1128 <addressOffset>0x50</addressOffset> 1129 <access>read-only</access> 1130 <fields> 1131 <field> 1132 <name>REVISION</name> 1133 <description>Manufacturer Chip Revision.</description> 1134 <bitOffset>0</bitOffset> 1135 <bitWidth>16</bitWidth> 1136 </field> 1137 </fields> 1138 </register> 1139 <register> 1140 <name>SYSIE</name> 1141 <description>System Status Interrupt Enable Register.</description> 1142 <addressOffset>0x54</addressOffset> 1143 <fields> 1144 <field> 1145 <name>ICEUNLOCK</name> 1146 <description>ARM ICE Unlock Interrupt Enable.</description> 1147 <bitOffset>0</bitOffset> 1148 <bitWidth>1</bitWidth> 1149 <enumeratedValues> 1150 <enumeratedValue> 1151 <name>dis</name> 1152 <description>disabled.</description> 1153 <value>0</value> 1154 </enumeratedValue> 1155 <enumeratedValue> 1156 <name>en</name> 1157 <description>enabled.</description> 1158 <value>1</value> 1159 </enumeratedValue> 1160 </enumeratedValues> 1161 </field> 1162 </fields> 1163 </register> 1164 <register> 1165 <name>ECCERR</name> 1166 <description>ECC Error Register</description> 1167 <addressOffset>0x64</addressOffset> 1168 <fields> 1169 <field> 1170 <name>RAM</name> 1171 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 1172 <bitOffset>0</bitOffset> 1173 <bitWidth>1</bitWidth> 1174 </field> 1175 </fields> 1176 </register> 1177 <register> 1178 <name>ECCCED</name> 1179 <description>ECC Not Double Error Detect Register</description> 1180 <addressOffset>0x68</addressOffset> 1181 <fields> 1182 <field> 1183 <name>RAM</name> 1184 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 1185 <bitOffset>0</bitOffset> 1186 <bitWidth>1</bitWidth> 1187 </field> 1188 </fields> 1189 </register> 1190 <register> 1191 <name>ECCIE</name> 1192 <description>ECC IRQ Enable Register</description> 1193 <addressOffset>0x6C</addressOffset> 1194 <fields> 1195 <field> 1196 <name>RAM</name> 1197 <description>ECC System RAM0 Error Interrup Enable</description> 1198 <bitOffset>0</bitOffset> 1199 <bitWidth>1</bitWidth> 1200 </field> 1201 </fields> 1202 </register> 1203 <register> 1204 <name>ECCADDR</name> 1205 <description>ECC Error Address Register</description> 1206 <addressOffset>0x70</addressOffset> 1207 <fields> 1208 <field> 1209 <name>ECCERRAD</name> 1210 <description>ECC Error Address.</description> 1211 <bitOffset>0</bitOffset> 1212 <bitWidth>32</bitWidth> 1213 </field> 1214 </fields> 1215 </register> 1216 <register> 1217 <name>BTLELDOCTRL</name> 1218 <description>BTLE LDO Control Register</description> 1219 <addressOffset>0x74</addressOffset> 1220 <fields> 1221 <field> 1222 <name>LDOTXEN</name> 1223 <description>LDOTX Enable.</description> 1224 <bitOffset>0</bitOffset> 1225 <bitWidth>1</bitWidth> 1226 </field> 1227 <field> 1228 <name>LDOTXPULLD</name> 1229 <description>LDOTX Pull Down.</description> 1230 <bitOffset>1</bitOffset> 1231 <bitWidth>1</bitWidth> 1232 </field> 1233 <field> 1234 <name>LDOTXVSEL</name> 1235 <description>LDOTX Voltage Setting.</description> 1236 <bitOffset>2</bitOffset> 1237 <bitWidth>2</bitWidth> 1238 <enumeratedValues> 1239 <enumeratedValue> 1240 <name>0_7</name> 1241 <description>0.7V</description> 1242 <value>0</value> 1243 </enumeratedValue> 1244 <enumeratedValue> 1245 <name>0_85</name> 1246 <description>0.85V</description> 1247 <value>1</value> 1248 </enumeratedValue> 1249 <enumeratedValue> 1250 <name>0_9</name> 1251 <description>0.9V</description> 1252 <value>2</value> 1253 </enumeratedValue> 1254 <enumeratedValue> 1255 <name>1_1</name> 1256 <description>1.1V</description> 1257 <value>3</value> 1258 </enumeratedValue> 1259 </enumeratedValues> 1260 </field> 1261 <field deprecated="(2-6-2023)"> 1262 <name>LDOTXVSEL0</name> 1263 <description>LDOTX Voltage Setting.</description> 1264 <bitOffset>2</bitOffset> 1265 <bitWidth>1</bitWidth> 1266 </field> 1267 <field deprecated="(2-6-2023)"> 1268 <name>LDOTXVSEL1</name> 1269 <description>LDOTX Voltage Setting.</description> 1270 <bitOffset>3</bitOffset> 1271 <bitWidth>1</bitWidth> 1272 </field> 1273 <field> 1274 <name>LDORXEN</name> 1275 <description>LDORX Enable.</description> 1276 <bitOffset>4</bitOffset> 1277 <bitWidth>1</bitWidth> 1278 </field> 1279 <field> 1280 <name>LDORXPULLD</name> 1281 <description>LDOrX Pull Down.</description> 1282 <bitOffset>5</bitOffset> 1283 <bitWidth>1</bitWidth> 1284 </field> 1285 <field> 1286 <name>LDORXVSEL</name> 1287 <description>LDORX Voltage Setting.</description> 1288 <bitOffset>6</bitOffset> 1289 <bitWidth>2</bitWidth> 1290 <enumeratedValues> 1291 <enumeratedValue> 1292 <name>0_7</name> 1293 <description>0.7V</description> 1294 <value>0</value> 1295 </enumeratedValue> 1296 <enumeratedValue> 1297 <name>0_85</name> 1298 <description>0.85V</description> 1299 <value>1</value> 1300 </enumeratedValue> 1301 <enumeratedValue> 1302 <name>0_9</name> 1303 <description>0.9V</description> 1304 <value>2</value> 1305 </enumeratedValue> 1306 <enumeratedValue> 1307 <name>1_1</name> 1308 <description>1.1V</description> 1309 <value>3</value> 1310 </enumeratedValue> 1311 </enumeratedValues> 1312 </field> 1313 <field deprecated="(2-6-2023)"> 1314 <name>LDORXVSEL0</name> 1315 <description>LDORX Voltage Setting.</description> 1316 <bitOffset>6</bitOffset> 1317 <bitWidth>1</bitWidth> 1318 </field> 1319 <field deprecated="(2-6-2023)"> 1320 <name>LDORXVSEL1</name> 1321 <description>LDORX Voltage Setting.</description> 1322 <bitOffset>7</bitOffset> 1323 <bitWidth>1</bitWidth> 1324 </field> 1325 <field> 1326 <name>LDORXBYP</name> 1327 <description>LDORX Bypass Enable.</description> 1328 <bitOffset>8</bitOffset> 1329 <bitWidth>1</bitWidth> 1330 </field> 1331 <field> 1332 <name>LDORXDISCH</name> 1333 <description>LDORX Discharge.</description> 1334 <bitOffset>9</bitOffset> 1335 <bitWidth>1</bitWidth> 1336 </field> 1337 <field> 1338 <name>LDOTXBYP</name> 1339 <description>LDOTX Bypass Enable.</description> 1340 <bitOffset>10</bitOffset> 1341 <bitWidth>1</bitWidth> 1342 </field> 1343 <field> 1344 <name>LDOTXDISCH</name> 1345 <description>LDOTX Discharge.</description> 1346 <bitOffset>11</bitOffset> 1347 <bitWidth>1</bitWidth> 1348 </field> 1349 <field> 1350 <name>LDOTXENDLY</name> 1351 <description>LDOTX Enable Delay.</description> 1352 <bitOffset>12</bitOffset> 1353 <bitWidth>1</bitWidth> 1354 </field> 1355 <field> 1356 <name>LDORXENDLY</name> 1357 <description>LDORX Enable Delay.</description> 1358 <bitOffset>13</bitOffset> 1359 <bitWidth>1</bitWidth> 1360 </field> 1361 <field> 1362 <name>LDORXBYPENENDLY</name> 1363 <description>LDORX Bypass Enable Delay.</description> 1364 <bitOffset>14</bitOffset> 1365 <bitWidth>1</bitWidth> 1366 </field> 1367 <field> 1368 <name>LDOTXBYPENENDLY</name> 1369 <description>LDOTX Bypass Enable Delay.</description> 1370 <bitOffset>15</bitOffset> 1371 <bitWidth>1</bitWidth> 1372 </field> 1373 </fields> 1374 </register> 1375 <register> 1376 <name>BTLELDODLY</name> 1377 <description>BTLE LDO Delay Register</description> 1378 <addressOffset>0x78</addressOffset> 1379 <fields> 1380 <field> 1381 <name>BYPDLYCNT</name> 1382 <description>Bypass Delay Count.</description> 1383 <bitOffset>0</bitOffset> 1384 <bitWidth>8</bitWidth> 1385 </field> 1386 <field> 1387 <name>LDORXDLYCNT</name> 1388 <description>LDORX Delay Count.</description> 1389 <bitOffset>8</bitOffset> 1390 <bitWidth>9</bitWidth> 1391 </field> 1392 <field> 1393 <name>LDOTXDLYCNT</name> 1394 <description>LDOTX Delay Count.</description> 1395 <bitOffset>20</bitOffset> 1396 <bitWidth>9</bitWidth> 1397 </field> 1398 </fields> 1399 </register> 1400 <register> 1401 <name>GPR</name> 1402 <description>General Purpose Register.</description> 1403 <addressOffset>0x80</addressOffset> 1404 </register> 1405 </registers> 1406 </peripheral> 1407</device>
