1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SYSCTRL</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>SBUSARB</name> 21 <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description> 22 <bitOffset>1</bitOffset> 23 <bitWidth>2</bitWidth> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>fix</name> 27 <description>Fixed Burst abritration.</description> 28 <value>0</value> 29 </enumeratedValue> 30 <enumeratedValue> 31 <name>round</name> 32 <description>Round-robin scheme.</description> 33 <value>1</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>FPU_DIS</name> 39 <description>Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4</description> 40 <bitOffset>5</bitOffset> 41 <bitWidth>1</bitWidth> 42 </field> 43 <field> 44 <name>ICC0_FLUSH</name> 45 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 46 <bitOffset>6</bitOffset> 47 <bitWidth>1</bitWidth> 48 <enumeratedValues> 49 <enumeratedValue> 50 <name>normal</name> 51 <description>Normal Code Cache Operation</description> 52 <value>0</value> 53 </enumeratedValue> 54 <enumeratedValue> 55 <name>flush</name> 56 <description>Code Caches and CPU instruction buffer are flushed </description> 57 <value>1</value> 58 </enumeratedValue> 59 </enumeratedValues> 60 </field> 61 <field> 62 <name>ROMDONE</name> 63 <description>ROM_DONE status. Used to disable SWD interface during system initialization procedure</description> 64 <bitOffset>12</bitOffset> 65 <bitWidth>1</bitWidth> 66 </field> 67 <field> 68 <name>CCHK</name> 69 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 70 <bitOffset>13</bitOffset> 71 <bitWidth>1</bitWidth> 72 <enumeratedValues> 73 <enumeratedValue> 74 <name>complete</name> 75 <description>No operation/complete.</description> 76 <value>0</value> 77 </enumeratedValue> 78 <enumeratedValue> 79 <name>start</name> 80 <description>Start operation.</description> 81 <value>1</value> 82 </enumeratedValue> 83 </enumeratedValues> 84 </field> 85 <field> 86 <name>SWD_DIS</name> 87 <description> Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set) 88 </description> 89 <bitOffset>14</bitOffset> 90 <bitWidth>1</bitWidth> 91 </field> 92 <field> 93 <name>CHKRES</name> 94 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 95 <bitOffset>15</bitOffset> 96 <bitWidth>1</bitWidth> 97 <enumeratedValues> 98 <enumeratedValue> 99 <name>pass</name> 100 <description>ROM Checksum Correct.</description> 101 <value>0</value> 102 </enumeratedValue> 103 <enumeratedValue> 104 <name>fail</name> 105 <description>ROM Checksum Fail.</description> 106 <value>1</value> 107 </enumeratedValue> 108 </enumeratedValues> 109 </field> 110 </fields> 111 </register> 112 <register> 113 <name>RST0</name> 114 <description>Reset.</description> 115 <addressOffset>0x04</addressOffset> 116 <fields> 117 <field> 118 <name>DMA</name> 119 <description>DMA Reset.</description> 120 <bitOffset>0</bitOffset> 121 <bitWidth>1</bitWidth> 122 <enumeratedValues> 123 <name>reset</name> 124 <usage>read-write</usage> 125 <enumeratedValue> 126 <name>reset_done</name> 127 <description>Reset complete.</description> 128 <value>0</value> 129 </enumeratedValue> 130 <enumeratedValue> 131 <name>busy</name> 132 <description>Starts Reset or indicates reset in progress.</description> 133 <value>1</value> 134 </enumeratedValue> 135 </enumeratedValues> 136 </field> 137 <field derivedFrom="DMA"> 138 <name>WDT0</name> 139 <description>Watchdog Timer Reset.</description> 140 <bitOffset>1</bitOffset> 141 <bitWidth>1</bitWidth> 142 </field> 143 <field derivedFrom="DMA"> 144 <name>GPIO0</name> 145 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 146 <bitOffset>2</bitOffset> 147 <bitWidth>1</bitWidth> 148 </field> 149 <field derivedFrom="DMA"> 150 <name>GPIO1</name> 151 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 152 <bitOffset>3</bitOffset> 153 <bitWidth>1</bitWidth> 154 </field> 155 <field derivedFrom="DMA"> 156 <name>TMR0</name> 157 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 158 <bitOffset>5</bitOffset> 159 <bitWidth>1</bitWidth> 160 </field> 161 <field derivedFrom="DMA"> 162 <name>TMR1</name> 163 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 164 <bitOffset>6</bitOffset> 165 <bitWidth>1</bitWidth> 166 </field> 167 <field derivedFrom="DMA"> 168 <name>TMR2</name> 169 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 170 <bitOffset>7</bitOffset> 171 <bitWidth>1</bitWidth> 172 </field> 173 <field derivedFrom="DMA"> 174 <name>TMR3</name> 175 <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 176 <bitOffset>8</bitOffset> 177 <bitWidth>1</bitWidth> 178 </field> 179 <field derivedFrom="DMA"> 180 <name>UART0</name> 181 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 182 <bitOffset>11</bitOffset> 183 <bitWidth>1</bitWidth> 184 </field> 185 <field derivedFrom="DMA"> 186 <name>UART1</name> 187 <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 188 <bitOffset>12</bitOffset> 189 <bitWidth>1</bitWidth> 190 </field> 191 <field derivedFrom="DMA"> 192 <name>SPI0</name> 193 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 194 <bitOffset>13</bitOffset> 195 <bitWidth>1</bitWidth> 196 </field> 197 <field derivedFrom="DMA"> 198 <name>SPI1</name> 199 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 200 <bitOffset>14</bitOffset> 201 <bitWidth>1</bitWidth> 202 </field> 203 <field derivedFrom="DMA"> 204 <name>SPI2</name> 205 <description>SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description> 206 <bitOffset>15</bitOffset> 207 <bitWidth>1</bitWidth> 208 </field> 209 <field derivedFrom="DMA"> 210 <name>I2C0</name> 211 <description>I2C0 Reset.</description> 212 <bitOffset>16</bitOffset> 213 <bitWidth>1</bitWidth> 214 </field> 215 <field derivedFrom="DMA"> 216 <name>RTC</name> 217 <description>Real Time Clock Reset.</description> 218 <bitOffset>17</bitOffset> 219 <bitWidth>1</bitWidth> 220 </field> 221 <field derivedFrom="DMA"> 222 <name>TRNG</name> 223 <description>TRNG Reset.</description> 224 <bitOffset>24</bitOffset> 225 <bitWidth>1</bitWidth> 226 </field> 227 <field derivedFrom="DMA"> 228 <name>UART2</name> 229 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 230 <bitOffset>28</bitOffset> 231 <bitWidth>1</bitWidth> 232 </field> 233 <field derivedFrom="DMA"> 234 <name>SOFT</name> 235 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 236 <bitOffset>29</bitOffset> 237 <bitWidth>1</bitWidth> 238 </field> 239 <field derivedFrom="DMA"> 240 <name>PERIPH</name> 241 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 242 <bitOffset>30</bitOffset> 243 <bitWidth>1</bitWidth> 244 </field> 245 <field derivedFrom="DMA"> 246 <name>SYS</name> 247 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 248 <bitOffset>31</bitOffset> 249 <bitWidth>1</bitWidth> 250 </field> 251 </fields> 252 </register> 253 <register> 254 <name>CLKCTRL</name> 255 <description>Clock Control.</description> 256 <addressOffset>0x08</addressOffset> 257 <resetValue>0x00000008</resetValue> 258 <fields> 259 <field> 260 <name>SYSCLK_DIV</name> 261 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 262 <bitOffset>6</bitOffset> 263 <bitWidth>3</bitWidth> 264 <enumeratedValues> 265 <enumeratedValue> 266 <name>div1</name> 267 <description>Divide by 1.</description> 268 <value>0</value> 269 </enumeratedValue> 270 <enumeratedValue> 271 <name>div2</name> 272 <description>Divide by 2.</description> 273 <value>1</value> 274 </enumeratedValue> 275 <enumeratedValue> 276 <name>div4</name> 277 <description>Divide by 4.</description> 278 <value>2</value> 279 </enumeratedValue> 280 <enumeratedValue> 281 <name>div8</name> 282 <description>Divide by 8.</description> 283 <value>3</value> 284 </enumeratedValue> 285 <enumeratedValue> 286 <name>div16</name> 287 <description>Divide by 16.</description> 288 <value>4</value> 289 </enumeratedValue> 290 <enumeratedValue> 291 <name>div32</name> 292 <description>Divide by 32.</description> 293 <value>5</value> 294 </enumeratedValue> 295 <enumeratedValue> 296 <name>div64</name> 297 <description>Divide by 64.</description> 298 <value>6</value> 299 </enumeratedValue> 300 <enumeratedValue> 301 <name>div128</name> 302 <description>Divide by 128.</description> 303 <value>7</value> 304 </enumeratedValue> 305 </enumeratedValues> 306 </field> 307 <field> 308 <name>SYSCLK_SEL</name> 309 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 310 <bitOffset>9</bitOffset> 311 <bitWidth>3</bitWidth> 312 <enumeratedValues> 313 <enumeratedValue> 314 <name>ERFO</name> 315 <description>32MHz Crystal is used for the system clock.</description> 316 <value>2</value> 317 </enumeratedValue> 318 <enumeratedValue> 319 <name>INRO</name> 320 <description>80kHz LIRC is used for the system clock.</description> 321 <value>3</value> 322 </enumeratedValue> 323 <enumeratedValue> 324 <name>IPO</name> 325 <description>The internal 96 MHz oscillator is used for the system clock.</description> 326 <value>4</value> 327 </enumeratedValue> 328 <enumeratedValue> 329 <name>IBRO</name> 330 <description>The internal 8 MHz oscillator is used for the system clock.</description> 331 <value>5</value> 332 </enumeratedValue> 333 <enumeratedValue> 334 <name>ERTCO</name> 335 <description> 32kHz is used for the system clock.</description> 336 <value>6</value> 337 </enumeratedValue> 338 <enumeratedValue> 339 <name>EXTCLK</name> 340 <description> External clock on gpio0 11.</description> 341 <value>7</value> 342 </enumeratedValue> 343 </enumeratedValues> 344 </field> 345 <field> 346 <name>SYSCLK_RDY</name> 347 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 348 <bitOffset>13</bitOffset> 349 <bitWidth>1</bitWidth> 350 <access>read-only</access> 351 <enumeratedValues> 352 <enumeratedValue> 353 <name>busy</name> 354 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 355 <value>0</value> 356 </enumeratedValue> 357 <enumeratedValue> 358 <name>ready</name> 359 <description>System clock running from CLKSEL clock source.</description> 360 <value>1</value> 361 </enumeratedValue> 362 </enumeratedValues> 363 </field> 364 <field> 365 <name>IPO_DIV</name> 366 <description>Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration.</description> 367 <bitOffset>14</bitOffset> 368 <bitWidth>2</bitWidth> 369 <enumeratedValues> 370 <enumeratedValue> 371 <name>div1</name> 372 <description>divide clock by 1</description> 373 <value>0</value> 374 </enumeratedValue> 375 <enumeratedValue> 376 <name>div2</name> 377 <description>divide clock by 2</description> 378 <value>1</value> 379 </enumeratedValue> 380 <enumeratedValue> 381 <name>div4</name> 382 <description>divide clock by 4</description> 383 <value>2</value> 384 </enumeratedValue> 385 <enumeratedValue> 386 <name>div8</name> 387 <description>divide clock by 8</description> 388 <value>3</value> 389 </enumeratedValue> 390 </enumeratedValues> 391 </field> 392 <field> 393 <name>ERFO_EN</name> 394 <description>32MHz Crystal Oscillator Enable.</description> 395 <bitOffset>16</bitOffset> 396 <bitWidth>1</bitWidth> 397 <enumeratedValues> 398 <enumeratedValue> 399 <name>dis</name> 400 <description>Is Disabled.</description> 401 <value>0</value> 402 </enumeratedValue> 403 <enumeratedValue> 404 <name>en</name> 405 <description>Is Enabled.</description> 406 <value>1</value> 407 </enumeratedValue> 408 </enumeratedValues> 409 </field> 410 <field> 411 <name>ERTCO_EN</name> 412 <description>32kHz Crystal Oscillator Enable.</description> 413 <bitOffset>17</bitOffset> 414 <bitWidth>1</bitWidth> 415 <enumeratedValues> 416 <enumeratedValue> 417 <name>dis</name> 418 <description>Is Disabled.</description> 419 <value>0</value> 420 </enumeratedValue> 421 <enumeratedValue> 422 <name>en</name> 423 <description>Is Enabled.</description> 424 <value>1</value> 425 </enumeratedValue> 426 </enumeratedValues> 427 </field> 428 <field derivedFrom="ERTCO_EN"> 429 <name>IPO_EN</name> 430 <description>96MHz High Frequency Internal Reference Clock Enable.</description> 431 <bitOffset>19</bitOffset> 432 <bitWidth>1</bitWidth> 433 </field> 434 <field derivedFrom="ERTCO_EN"> 435 <name>IBRO_EN</name> 436 <description>8MHz High Frequency Internal Reference Clock Enable.</description> 437 <bitOffset>20</bitOffset> 438 <bitWidth>1</bitWidth> 439 </field> 440 <field> 441 <name>IBRO_VS</name> 442 <description>8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M.</description> 443 <bitOffset>21</bitOffset> 444 <bitWidth>1</bitWidth> 445 <enumeratedValues> 446 <enumeratedValue> 447 <name>Vcor</name> 448 <description>VCore Supply</description> 449 <value>0</value> 450 </enumeratedValue> 451 <enumeratedValue> 452 <name>1V</name> 453 <description>Dedicated 1v regulated supply.</description> 454 <value>1</value> 455 </enumeratedValue> 456 </enumeratedValues> 457 </field> 458 <field> 459 <name>ERFO_RDY</name> 460 <description>32MHz Crystal Oscillator Ready</description> 461 <bitOffset>24</bitOffset> 462 <bitWidth>1</bitWidth> 463 <access>read-only</access> 464 <enumeratedValues> 465 <enumeratedValue> 466 <name>not</name> 467 <description>Is not Ready.</description> 468 <value>0</value> 469 </enumeratedValue> 470 <enumeratedValue> 471 <name>ready</name> 472 <description>Is Ready.</description> 473 <value>1</value> 474 </enumeratedValue> 475 </enumeratedValues> 476 </field> 477 <field> 478 <name>ERTCO_RDY</name> 479 <description>32kHz Crystal Oscillator Ready</description> 480 <bitOffset>25</bitOffset> 481 <bitWidth>1</bitWidth> 482 <access>read-only</access> 483 <enumeratedValues> 484 <enumeratedValue> 485 <name>not</name> 486 <description>Is not Ready.</description> 487 <value>0</value> 488 </enumeratedValue> 489 <enumeratedValue> 490 <name>ready</name> 491 <description>Is Ready.</description> 492 <value>1</value> 493 </enumeratedValue> 494 </enumeratedValues> 495 </field> 496 <field derivedFrom="ERTCO_RDY"> 497 <name>IPO_RDY</name> 498 <description>96MHz HIRC Ready.</description> 499 <bitOffset>27</bitOffset> 500 <bitWidth>1</bitWidth> 501 </field> 502 <field derivedFrom="ERTCO_RDY"> 503 <name>IBRO_RDY</name> 504 <description>8MHz HIRC Ready.</description> 505 <bitOffset>28</bitOffset> 506 <bitWidth>1</bitWidth> 507 </field> 508 <field derivedFrom="ERTCO_RDY"> 509 <name>INRO_RDY</name> 510 <description>8kHz Low Frequency Reference Clock Ready.</description> 511 <bitOffset>29</bitOffset> 512 <bitWidth>1</bitWidth> 513 </field> 514 <field derivedFrom="ERTCO_RDY"> 515 <name>EXTCLK_RDY</name> 516 <description>External Clock (GPIO0[11] AF2) </description> 517 <bitOffset>31</bitOffset> 518 <bitWidth>1</bitWidth> 519 </field> 520 </fields> 521 </register> 522 <register> 523 <name>PM</name> 524 <description>Power Management.</description> 525 <addressOffset>0x0C</addressOffset> 526 <fields> 527 <field> 528 <name>MODE</name> 529 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 530 <bitOffset>0</bitOffset> 531 <bitWidth>3</bitWidth> 532 <enumeratedValues> 533 <enumeratedValue> 534 <name>active</name> 535 <description>Active Mode.</description> 536 <value>0</value> 537 </enumeratedValue> 538 <enumeratedValue> 539 <name>shutdown</name> 540 <description>Shutdown Mode.</description> 541 <value>3</value> 542 </enumeratedValue> 543 <enumeratedValue> 544 <name>backup</name> 545 <description>Backup Mode.</description> 546 <value>4</value> 547 </enumeratedValue> 548 </enumeratedValues> 549 </field> 550 <field> 551 <name>GPIO_WE</name> 552 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 553 <bitOffset>4</bitOffset> 554 <bitWidth>1</bitWidth> 555 <enumeratedValues> 556 <enumeratedValue> 557 <name>dis</name> 558 <description>Wake Up Disable.</description> 559 <value>0</value> 560 </enumeratedValue> 561 <enumeratedValue> 562 <name>en</name> 563 <description>Wake Up Enable.</description> 564 <value>1</value> 565 </enumeratedValue> 566 </enumeratedValues> 567 </field> 568 <field derivedFrom="GPIO_WE"> 569 <name>RTC_WE</name> 570 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 571 <bitOffset>5</bitOffset> 572 <bitWidth>1</bitWidth> 573 </field> 574 <field derivedFrom="GPIO_WE"> 575 <name>LPTMR0_WE</name> 576 <description>TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source. </description> 577 <bitOffset>6</bitOffset> 578 <bitWidth>1</bitWidth> 579 </field> 580 <field derivedFrom="GPIO_WE"> 581 <name>LPTMR1_WE</name> 582 <description>TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source. </description> 583 <bitOffset>7</bitOffset> 584 <bitWidth>1</bitWidth> 585 </field> 586 <field derivedFrom="GPIO_WE"> 587 <name>LPUART0_WE</name> 588 <description>LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source. </description> 589 <bitOffset>8</bitOffset> 590 <bitWidth>1</bitWidth> 591 </field> 592 <field> 593 <name>ERFO_PD</name> 594 <description>32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode.</description> 595 <bitOffset>12</bitOffset> 596 <bitWidth>1</bitWidth> 597 <enumeratedValues> 598 <enumeratedValue> 599 <name>active</name> 600 <description>Mode is Active.</description> 601 <value>0</value> 602 </enumeratedValue> 603 <enumeratedValue> 604 <name>deepsleep</name> 605 <description>Powered down in DEEPSLEEP.</description> 606 <value>1</value> 607 </enumeratedValue> 608 </enumeratedValues> 609 </field> 610 <field derivedFrom="ERFO_PD"> 611 <name>IPO_PD</name> 612 <description>96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. </description> 613 <bitOffset>16</bitOffset> 614 <bitWidth>1</bitWidth> 615 </field> 616 <field derivedFrom="ERFO_PD"> 617 <name>IBRO_PD</name> 618 <description>8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. </description> 619 <bitOffset>17</bitOffset> 620 <bitWidth>1</bitWidth> 621 </field> 622 <field> 623 <name>ERFO_BP</name> 624 <description>32MHz Oscillator Bypass</description> 625 <bitOffset>20</bitOffset> 626 <bitWidth>1</bitWidth> 627 </field> 628 </fields> 629 </register> 630 <register> 631 <name>PCLKDIV</name> 632 <description>Peripheral Clock Divider.</description> 633 <addressOffset>0x18</addressOffset> 634 <resetValue>0x00000001</resetValue> 635 <fields> 636 <field> 637 <name>AON_CLKDIV</name> 638 <description>Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider</description> 639 <bitOffset>0</bitOffset> 640 <bitWidth>2</bitWidth> 641 <enumeratedValues> 642 <enumeratedValue> 643 <name>div4</name> 644 <value>0</value> 645 </enumeratedValue> 646 <enumeratedValue> 647 <name>div8</name> 648 <value>1</value> 649 </enumeratedValue> 650 <enumeratedValue> 651 <name>div16</name> 652 <value>2</value> 653 </enumeratedValue> 654 <enumeratedValue> 655 <name>div32</name> 656 <value>3</value> 657 </enumeratedValue> 658 </enumeratedValues> 659 </field> 660 <field> 661 <name>DIV_CLK_OUT_CTRL</name> 662 <description>DIV_CLK_OUT Control</description> 663 <bitOffset>14</bitOffset> 664 <bitWidth>2</bitWidth> 665 </field> 666 <field> 667 <name>DIV_CLK_OUT_EN</name> 668 <description>DIV_CLK_OUT Enable</description> 669 <bitOffset>16</bitOffset> 670 <bitWidth>1</bitWidth> 671 </field> 672 </fields> 673 </register> 674 <register> 675 <name>PCLKDIS0</name> 676 <description>Peripheral Clock Disable.</description> 677 <addressOffset>0x24</addressOffset> 678 <fields> 679 <field> 680 <name>GPIO0</name> 681 <description>GPIO0 Disable.</description> 682 <bitOffset>0</bitOffset> 683 <bitWidth>1</bitWidth> 684 <enumeratedValues> 685 <enumeratedValue> 686 <name>en</name> 687 <description>enable it.</description> 688 <value>0</value> 689 </enumeratedValue> 690 <enumeratedValue> 691 <name>dis</name> 692 <description>disable it.</description> 693 <value>1</value> 694 </enumeratedValue> 695 </enumeratedValues> 696 </field> 697 <field derivedFrom="GPIO0"> 698 <name>GPIO1</name> 699 <description>GPIO1 Disable.</description> 700 <bitOffset>1</bitOffset> 701 <bitWidth>1</bitWidth> 702 </field> 703 <field derivedFrom="GPIO0"> 704 <name>DMA</name> 705 <description>DMA Disable.</description> 706 <bitOffset>5</bitOffset> 707 <bitWidth>1</bitWidth> 708 </field> 709 <field derivedFrom="GPIO0"> 710 <name>SPI0</name> 711 <description>SPI 0 Disable.</description> 712 <bitOffset>6</bitOffset> 713 <bitWidth>1</bitWidth> 714 </field> 715 <field derivedFrom="GPIO0"> 716 <name>SPI1</name> 717 <description>SPI 1 Disable.</description> 718 <bitOffset>7</bitOffset> 719 <bitWidth>1</bitWidth> 720 </field> 721 <field derivedFrom="GPIO0"> 722 <name>SPI2</name> 723 <description>SPI 2 Disable.</description> 724 <bitOffset>8</bitOffset> 725 <bitWidth>1</bitWidth> 726 </field> 727 <field derivedFrom="GPIO0"> 728 <name>UART0</name> 729 <description>UART 0 Disable.</description> 730 <bitOffset>9</bitOffset> 731 <bitWidth>1</bitWidth> 732 </field> 733 <field derivedFrom="GPIO0"> 734 <name>UART1</name> 735 <description>UART 1 Disable.</description> 736 <bitOffset>10</bitOffset> 737 <bitWidth>1</bitWidth> 738 </field> 739 <field derivedFrom="GPIO0"> 740 <name>I2C0</name> 741 <description>I2C 0 Disable.</description> 742 <bitOffset>13</bitOffset> 743 <bitWidth>1</bitWidth> 744 </field> 745 <field derivedFrom="GPIO0"> 746 <name>TMR0</name> 747 <description>Timer 0 Disable.</description> 748 <bitOffset>15</bitOffset> 749 <bitWidth>1</bitWidth> 750 </field> 751 <field derivedFrom="GPIO0"> 752 <name>TMR1</name> 753 <description>Timer 1 Disable.</description> 754 <bitOffset>16</bitOffset> 755 <bitWidth>1</bitWidth> 756 </field> 757 <field derivedFrom="GPIO0"> 758 <name>TMR2</name> 759 <description>Timer 2 Disable.</description> 760 <bitOffset>17</bitOffset> 761 <bitWidth>1</bitWidth> 762 </field> 763 <field derivedFrom="GPIO0"> 764 <name>TMR3</name> 765 <description>Timer 3 Disable.</description> 766 <bitOffset>18</bitOffset> 767 <bitWidth>1</bitWidth> 768 </field> 769 <field derivedFrom="GPIO0"> 770 <name>I2C1</name> 771 <description>I2C 1 Disable.</description> 772 <bitOffset>28</bitOffset> 773 <bitWidth>1</bitWidth> 774 </field> 775 </fields> 776 </register> 777 <register> 778 <name>MEMCTRL</name> 779 <description>Memory Clock Control Register.</description> 780 <addressOffset>0x28</addressOffset> 781 <fields> 782 <field> 783 <name>FWS</name> 784 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 785 <bitOffset>0</bitOffset> 786 <bitWidth>3</bitWidth> 787 </field> 788 <field> 789 <name>RAMWS_EN</name> 790 <description>System RAM Wait State enable</description> 791 <bitOffset>4</bitOffset> 792 <bitWidth>1</bitWidth> 793 </field> 794 <field> 795 <name>RAM0LS_EN</name> 796 <description>System RAM 0 Light Sleep Mode.</description> 797 <bitOffset>8</bitOffset> 798 <bitWidth>1</bitWidth> 799 <enumeratedValues> 800 <enumeratedValue> 801 <name>active</name> 802 <description>RAM is active.</description> 803 <value>0</value> 804 </enumeratedValue> 805 <enumeratedValue> 806 <name>light_sleep</name> 807 <description>RAM is in Light Sleep mode.</description> 808 <value>1</value> 809 </enumeratedValue> 810 </enumeratedValues> 811 </field> 812 <field derivedFrom="RAM0LS_EN"> 813 <name>RAM1LS_EN</name> 814 <description>System RAM 1 Light Sleep Mode.</description> 815 <bitOffset>9</bitOffset> 816 <bitWidth>1</bitWidth> 817 </field> 818 <field derivedFrom="RAM0LS_EN"> 819 <name>RAM2LS_EN</name> 820 <description>System RAM 2 Light Sleep Mode.</description> 821 <bitOffset>10</bitOffset> 822 <bitWidth>1</bitWidth> 823 </field> 824 <field derivedFrom="RAM0LS_EN"> 825 <name>RAM3LS_EN</name> 826 <description>System RAM 3 Light Sleep Mode.</description> 827 <bitOffset>11</bitOffset> 828 <bitWidth>1</bitWidth> 829 </field> 830 <field derivedFrom="RAM0LS_EN"> 831 <name>ICC0LS_EN</name> 832 <description>ICache RAM Light Sleep Mode.</description> 833 <bitOffset>12</bitOffset> 834 <bitWidth>1</bitWidth> 835 </field> 836 <field derivedFrom="RAM0LS_EN"> 837 <name>ROMLS_EN</name> 838 <description>ROM Light Sleep Mode.</description> 839 <bitOffset>13</bitOffset> 840 <bitWidth>1</bitWidth> 841 </field> 842 </fields> 843 </register> 844 <register> 845 <name>MEMZ</name> 846 <description>Memory Zeroize Control.</description> 847 <addressOffset>0x2C</addressOffset> 848 <fields> 849 <field> 850 <name>RAM</name> 851 <description>System RAM Block.</description> 852 <bitOffset>0</bitOffset> 853 <bitWidth>1</bitWidth> 854 <enumeratedValues> 855 <enumeratedValue> 856 <name>nop</name> 857 <description>No operation/complete.</description> 858 <value>0</value> 859 </enumeratedValue> 860 <enumeratedValue> 861 <name>start</name> 862 <description>Start operation.</description> 863 <value>1</value> 864 </enumeratedValue> 865 </enumeratedValues> 866 </field> 867 <field derivedFrom="RAM"> 868 <name>RAMCB</name> 869 <description>System RAM check bit zeroization.</description> 870 <bitOffset>1</bitOffset> 871 <bitWidth>1</bitWidth> 872 </field> 873 <field derivedFrom="RAM"> 874 <name>ICC0</name> 875 <description>Instruction Cache.</description> 876 <bitOffset>2</bitOffset> 877 <bitWidth>1</bitWidth> 878 </field> 879 </fields> 880 </register> 881 <register> 882 <name>SYSST</name> 883 <description>System Status Register.</description> 884 <addressOffset>0x40</addressOffset> 885 <fields> 886 <field> 887 <name>ICELOCK</name> 888 <description>ARM ICE Lock Status.</description> 889 <bitOffset>0</bitOffset> 890 <bitWidth>1</bitWidth> 891 <enumeratedValues> 892 <enumeratedValue> 893 <name>unlocked</name> 894 <description>ICE is unlocked.</description> 895 <value>0</value> 896 </enumeratedValue> 897 <enumeratedValue> 898 <name>locked</name> 899 <description>ICE is locked.</description> 900 <value>1</value> 901 </enumeratedValue> 902 </enumeratedValues> 903 </field> 904 </fields> 905 </register> 906 <register> 907 <name>RST1</name> 908 <description>Reset 1.</description> 909 <addressOffset>0x44</addressOffset> 910 <fields> 911 <field> 912 <name>I2C1</name> 913 <description>I2C1 Reset.</description> 914 <bitOffset>0</bitOffset> 915 <bitWidth>1</bitWidth> 916 <enumeratedValues> 917 <name>reset_read</name> 918 <usage>read</usage> 919 <enumeratedValue> 920 <name>reset_done</name> 921 <description>Reset complete.</description> 922 <value>0</value> 923 </enumeratedValue> 924 <enumeratedValue> 925 <name>busy</name> 926 <description>Starts reset or indicates reset in progress.</description> 927 <value>1</value> 928 </enumeratedValue> 929 </enumeratedValues> 930 </field> 931 <field derivedFrom="I2C1"> 932 <name>WDT1</name> 933 <description>WDT1 Reset.</description> 934 <bitOffset>8</bitOffset> 935 <bitWidth>1</bitWidth> 936 </field> 937 <field derivedFrom="I2C1"> 938 <name>CRC</name> 939 <description>CRC Reset.</description> 940 <bitOffset>9</bitOffset> 941 <bitWidth>1</bitWidth> 942 </field> 943 <field derivedFrom="I2C1"> 944 <name>AES</name> 945 <description>AES Reset.</description> 946 <bitOffset>10</bitOffset> 947 <bitWidth>1</bitWidth> 948 </field> 949 <field derivedFrom="I2C1"> 950 <name>AC</name> 951 <description>AC Reset.</description> 952 <bitOffset>14</bitOffset> 953 <bitWidth>1</bitWidth> 954 </field> 955 <field derivedFrom="I2C1"> 956 <name>I2C2</name> 957 <description>I2C2 Reset.</description> 958 <bitOffset>17</bitOffset> 959 <bitWidth>1</bitWidth> 960 </field> 961 <field derivedFrom="I2C1"> 962 <name>I2S</name> 963 <description>I2S Reset.</description> 964 <bitOffset>23</bitOffset> 965 <bitWidth>1</bitWidth> 966 </field> 967 <field derivedFrom="I2C1"> 968 <name>AFE</name> 969 <description>AFE Reset.</description> 970 <bitOffset>25</bitOffset> 971 <bitWidth>1</bitWidth> 972 </field> 973 </fields> 974 </register> 975 <register> 976 <name>PCLKDIS1</name> 977 <description>Peripheral Clock Disable.</description> 978 <addressOffset>0x48</addressOffset> 979 <fields> 980 <field> 981 <name>UART2</name> 982 <description>UART2 Disable.</description> 983 <bitOffset>1</bitOffset> 984 <bitWidth>1</bitWidth> 985 <enumeratedValues> 986 <enumeratedValue> 987 <name>en</name> 988 <description>Enable.</description> 989 <value>0</value> 990 </enumeratedValue> 991 <enumeratedValue> 992 <name>dis</name> 993 <description>Disable.</description> 994 <value>1</value> 995 </enumeratedValue> 996 </enumeratedValues> 997 </field> 998 <field derivedFrom="UART2"> 999 <name>TRNG</name> 1000 <description>TRNG Disable.</description> 1001 <bitOffset>2</bitOffset> 1002 <bitWidth>1</bitWidth> 1003 </field> 1004 <field derivedFrom="UART2"> 1005 <name>WWDT0</name> 1006 <description>WDT0 Disable.</description> 1007 <bitOffset>4</bitOffset> 1008 <bitWidth>1</bitWidth> 1009 </field> 1010 <field derivedFrom="UART2"> 1011 <name>WWDT1</name> 1012 <description>WDT1 Disable.</description> 1013 <bitOffset>5</bitOffset> 1014 <bitWidth>1</bitWidth> 1015 </field> 1016 <field derivedFrom="UART2"> 1017 <name>ICC0</name> 1018 <description>ICACHE Disable.</description> 1019 <bitOffset>11</bitOffset> 1020 <bitWidth>1</bitWidth> 1021 </field> 1022 <field derivedFrom="UART2"> 1023 <name>CRC</name> 1024 <description>CRC Disable.</description> 1025 <bitOffset>14</bitOffset> 1026 <bitWidth>1</bitWidth> 1027 </field> 1028 <field derivedFrom="UART2"> 1029 <name>AES</name> 1030 <description>AES Disable.</description> 1031 <bitOffset>15</bitOffset> 1032 <bitWidth>1</bitWidth> 1033 </field> 1034 <field derivedFrom="UART2"> 1035 <name>I2C2</name> 1036 <description>I2C2 Disable.</description> 1037 <bitOffset>21</bitOffset> 1038 <bitWidth>1</bitWidth> 1039 </field> 1040 <field derivedFrom="UART2"> 1041 <name>I2S</name> 1042 <description>I2S Clock Disable.</description> 1043 <bitOffset>23</bitOffset> 1044 <bitWidth>1</bitWidth> 1045 </field> 1046 </fields> 1047 </register> 1048 <register> 1049 <name>EVENTEN</name> 1050 <description>Event Enable Register.</description> 1051 <addressOffset>0x4C</addressOffset> 1052 <fields> 1053 <field> 1054 <name>DMA</name> 1055 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 1056 <bitOffset>0</bitOffset> 1057 <bitWidth>1</bitWidth> 1058 </field> 1059 <field> 1060 <name>RX</name> 1061 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[20] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 1062 <bitOffset>1</bitOffset> 1063 <bitWidth>1</bitWidth> 1064 </field> 1065 <field> 1066 <name>TX</name> 1067 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[21].</description> 1068 <bitOffset>2</bitOffset> 1069 <bitWidth>1</bitWidth> 1070 </field> 1071 </fields> 1072 </register> 1073 <register> 1074 <name>REVISION</name> 1075 <description>Revision Register.</description> 1076 <addressOffset>0x50</addressOffset> 1077 <access>read-only</access> 1078 <fields> 1079 <field> 1080 <name>REVISION</name> 1081 <description>Manufacturer Chip Revision. </description> 1082 <bitOffset>0</bitOffset> 1083 <bitWidth>16</bitWidth> 1084 </field> 1085 </fields> 1086 </register> 1087 <register> 1088 <name>SYSIE</name> 1089 <description>System Status Interrupt Enable Register.</description> 1090 <addressOffset>0x54</addressOffset> 1091 <fields> 1092 <field> 1093 <name>ICEUNLOCK</name> 1094 <description>ARM ICE Unlock Interrupt Enable.</description> 1095 <bitOffset>0</bitOffset> 1096 <bitWidth>1</bitWidth> 1097 <enumeratedValues> 1098 <enumeratedValue> 1099 <name>dis</name> 1100 <description>disabled.</description> 1101 <value>0</value> 1102 </enumeratedValue> 1103 <enumeratedValue> 1104 <name>en</name> 1105 <description>enabled.</description> 1106 <value>1</value> 1107 </enumeratedValue> 1108 </enumeratedValues> 1109 </field> 1110 </fields> 1111 </register> 1112 <register> 1113 <name>ECCERR</name> 1114 <description>ECC Error Register</description> 1115 <addressOffset>0x64</addressOffset> 1116 <fields> 1117 <field> 1118 <name>RAM</name> 1119 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 1120 <bitOffset>0</bitOffset> 1121 <bitWidth>1</bitWidth> 1122 </field> 1123 <field> 1124 <name>ICC0</name> 1125 <description>ECC Icache Error Flag. Write 1 to clear.</description> 1126 <bitOffset>1</bitOffset> 1127 <bitWidth>1</bitWidth> 1128 </field> 1129 <field> 1130 <name>FLASH</name> 1131 <description>ECC Flash Error Flag. Write 1 to clear.</description> 1132 <bitOffset>2</bitOffset> 1133 <bitWidth>1</bitWidth> 1134 </field> 1135 </fields> 1136 </register> 1137 <register> 1138 <name>ECCCED</name> 1139 <description>ECC Not Double Error Detect Register</description> 1140 <addressOffset>0x68</addressOffset> 1141 <fields> 1142 <field> 1143 <name>RAM</name> 1144 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 1145 <bitOffset>0</bitOffset> 1146 <bitWidth>1</bitWidth> 1147 </field> 1148 <field> 1149 <name>ICC0</name> 1150 <description>ECC Icache Not Double Error Detect. Write 1 to clear.</description> 1151 <bitOffset>1</bitOffset> 1152 <bitWidth>1</bitWidth> 1153 </field> 1154 <field> 1155 <name>FLASH</name> 1156 <description>ECC Flash0 Not Double Error Detect. Write 1 to clear.</description> 1157 <bitOffset>2</bitOffset> 1158 <bitWidth>1</bitWidth> 1159 </field> 1160 </fields> 1161 </register> 1162 <register> 1163 <name>ECCIE</name> 1164 <description>ECC IRQ Enable Register</description> 1165 <addressOffset>0x6C</addressOffset> 1166 <fields> 1167 <field> 1168 <name>RAM</name> 1169 <description>ECC System RAM0 Error Interrup Enable</description> 1170 <bitOffset>0</bitOffset> 1171 <bitWidth>1</bitWidth> 1172 </field> 1173 <field> 1174 <name>ICC0</name> 1175 <description>ECC Icache0 Error Interrup Enable</description> 1176 <bitOffset>1</bitOffset> 1177 <bitWidth>1</bitWidth> 1178 </field> 1179 <field> 1180 <name>FLASH</name> 1181 <description>ECC Flash0 NError Interrup Enable</description> 1182 <bitOffset>2</bitOffset> 1183 <bitWidth>1</bitWidth> 1184 </field> 1185 </fields> 1186 </register> 1187 <register> 1188 <name>ECCADDR</name> 1189 <description>ECC Error Address Register</description> 1190 <addressOffset>0x70</addressOffset> 1191 <fields> 1192 <field> 1193 <name>DATARAMADDR</name> 1194 <description>ECC Error Address/TAG RAM Error Address.</description> 1195 <bitOffset>0</bitOffset> 1196 <bitWidth>14</bitWidth> 1197 </field> 1198 <field> 1199 <name>DATARAMBANK</name> 1200 <description>ECC Error Address/DATA RAM Error Bank.</description> 1201 <bitOffset>14</bitOffset> 1202 <bitWidth>1</bitWidth> 1203 </field> 1204 <field> 1205 <name>DATARAMERR</name> 1206 <description>ECC Error Address/DATA RAM Error Address.</description> 1207 <bitOffset>15</bitOffset> 1208 <bitWidth>1</bitWidth> 1209 </field> 1210 <field> 1211 <name>TAGRAMADDR</name> 1212 <description>ECC Error Address/TAG RAM Error Address.</description> 1213 <bitOffset>16</bitOffset> 1214 <bitWidth>14</bitWidth> 1215 </field> 1216 <field> 1217 <name>TAGRAMBANK</name> 1218 <description>ECC Error Address/TAG RAM Error Bank.</description> 1219 <bitOffset>30</bitOffset> 1220 <bitWidth>1</bitWidth> 1221 </field> 1222 <field> 1223 <name>TAGRAMERR</name> 1224 <description>ECC Error Address/TAG RAM Error.</description> 1225 <bitOffset>31</bitOffset> 1226 <bitWidth>1</bitWidth> 1227 </field> 1228 </fields> 1229 </register> 1230 </registers> 1231 </peripheral> 1232</device>
