1<?xml version="1.0" encoding="utf-8" standalone="no"?>
2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd">
3  <peripheral>
4    <name>GCR</name>
5    <description>Global Control Registers.</description>
6    <baseAddress>0x40000000</baseAddress>
7    <addressBlock>
8      <offset>0</offset>
9      <size>0x400</size>
10      <usage>registers</usage>
11    </addressBlock>
12    <registers>
13      <register>
14        <name>SCON</name>
15        <description>System Control.</description>
16        <addressOffset>0x00</addressOffset>
17        <resetMask>0xFFFFFFFE</resetMask>
18        <fields>
19          <field>
20            <name>BSTAPEN</name>
21            <description>Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.</description>
22            <bitOffset>0</bitOffset>
23            <bitWidth>1</bitWidth>
24            <enumeratedValues>
25              <enumeratedValue>
26                <name>dis</name>
27                <description>Boundary Scan TAP port disabled.</description>
28                <value>0</value>
29              </enumeratedValue>
30              <enumeratedValue>
31                <name>en</name>
32                <description>Boundary Scan TAP port enabled.</description>
33                <value>1</value>
34              </enumeratedValue>
35            </enumeratedValues>
36          </field>
37          <field>
38            <name>SBUSARB</name>
39            <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description>
40            <bitOffset>1</bitOffset>
41            <bitWidth>2</bitWidth>
42            <enumeratedValues>
43              <enumeratedValue>
44                <name>fix</name>
45                <description>Fixed Burst abritration.</description>
46                <value>0</value>
47              </enumeratedValue>
48              <enumeratedValue>
49                <name>round</name>
50                <description>Round-robin scheme.</description>
51                <value>1</value>
52              </enumeratedValue>
53            </enumeratedValues>
54          </field>
55          <field>
56            <name>FLASH_PAGE_FLIP</name>
57            <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description>
58            <bitOffset>4</bitOffset>
59            <bitWidth>1</bitWidth>
60            <enumeratedValues>
61              <enumeratedValue>
62                <name>normal</name>
63                <description>Physical layout matches logical layout.</description>
64                <value>0</value>
65              </enumeratedValue>
66              <enumeratedValue>
67                <name>swapped</name>
68                <description>Bottom half mapped to logical top half and vice versa.</description>
69                <value>1</value>
70              </enumeratedValue>
71            </enumeratedValues>
72          </field>
73          <field>
74            <name>CCACHE_FLUSH</name>
75            <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description>
76            <bitOffset>6</bitOffset>
77            <bitWidth>1</bitWidth>
78            <enumeratedValues>
79              <enumeratedValue>
80                <name>normal</name>
81                <description>Normal Code Cache Operation</description>
82                <value>0</value>
83              </enumeratedValue>
84              <enumeratedValue>
85                <name>flush</name>
86                <description>Code Caches and CPU instruction buffer are flushed </description>
87                <value>1</value>
88              </enumeratedValue>
89            </enumeratedValues>
90          </field>
91          <field>
92            <name>DCACHE_FLUSH</name>
93            <description>Data Cache Flush. The system cache(s) will be flushed when this bit is set. </description>
94            <bitOffset>7</bitOffset>
95            <bitWidth>1</bitWidth>
96            <enumeratedValues>
97              <enumeratedValue>
98                <name>normal</name>
99                <description>Normal System Cache Operation</description>
100                <value>0</value>
101              </enumeratedValue>
102              <enumeratedValue>
103                <name>flush</name>
104                <description>System Cache is flushed </description>
105                <value>1</value>
106              </enumeratedValue>
107            </enumeratedValues>
108          </field>
109          <field>
110            <name>SRCC_DIS</name>
111            <description>SPIXR Cache Controller Disable. Disables the SRCC used for SPIXR code and data cache. Setting this field disables the cache and bypasses the cache line buffer.</description>
112            <bitOffset>9</bitOffset>
113            <bitWidth>1</bitWidth>
114            <enumeratedValues>
115              <enumeratedValue>
116                <name>en</name>
117                <description>Is enabled.</description>
118                <value>0</value>
119              </enumeratedValue>
120              <enumeratedValue>
121                <name>dis</name>
122                <description>Is Disabled.</description>
123                <value>1</value>
124              </enumeratedValue>
125            </enumeratedValues>
126          </field>
127          <field>
128            <name>CCHK</name>
129            <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description>
130            <bitOffset>13</bitOffset>
131            <bitWidth>1</bitWidth>
132            <enumeratedValues>
133              <enumeratedValue>
134                <name>complete</name>
135                <description>No operation/complete.</description>
136                <value>0</value>
137              </enumeratedValue>
138              <enumeratedValue>
139                <name>start</name>
140                <description>Start operation.</description>
141                <value>1</value>
142              </enumeratedValue>
143            </enumeratedValues>
144          </field>
145          <field>
146            <name>CHKRES</name>
147            <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description>
148            <bitOffset>15</bitOffset>
149            <bitWidth>1</bitWidth>
150            <enumeratedValues>
151              <enumeratedValue>
152                <name>pass</name>
153                <description>ROM Checksum Correct.</description>
154                <value>0</value>
155              </enumeratedValue>
156              <enumeratedValue>
157                <name>fail</name>
158                <description>ROM Checksum Fail.</description>
159                <value>1</value>
160              </enumeratedValue>
161            </enumeratedValues>
162          </field>
163          <field>
164            <name>OVR</name>
165            <description>Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range.</description>
166            <bitOffset>16</bitOffset>
167            <bitWidth>2</bitWidth>
168            <enumeratedValues>
169              <enumeratedValue>
170                <name>0_9V</name>
171                <description>0.9V +/- 10%</description>
172                <value>0</value>
173              </enumeratedValue>
174              <enumeratedValue>
175                <name>1_0V</name>
176                <description>1.0V +/- 10%</description>
177                <value>1</value>
178              </enumeratedValue>
179              <enumeratedValue>
180                <name>1_1V</name>
181                <description>1.1V +/- 10%</description>
182                <value>2</value>
183              </enumeratedValue>
184            </enumeratedValues>
185          </field>
186        </fields>
187      </register>
188      <register>
189        <name>RSTR0</name>
190        <description>Reset.</description>
191        <addressOffset>0x04</addressOffset>
192        <fields>
193          <field>
194            <name>DMA</name>
195            <description>DMA Reset.</description>
196            <bitOffset>0</bitOffset>
197            <bitWidth>1</bitWidth>
198            <enumeratedValues>
199              <name>reset</name>
200              <usage>read-write</usage>
201              <enumeratedValue>
202                <name>reset_done</name>
203                <description>Reset complete.</description>
204                <value>0</value>
205              </enumeratedValue>
206              <enumeratedValue>
207                <name>busy</name>
208                <description>Starts Reset or indicates reset in progress.</description>
209                <value>1</value>
210              </enumeratedValue>
211            </enumeratedValues>
212          </field>
213          <field derivedFrom="DMA">
214            <name>WDT0</name>
215            <description>Watchdog Timer Reset.</description>
216            <bitOffset>1</bitOffset>
217            <bitWidth>1</bitWidth>
218          </field>
219          <field derivedFrom="DMA">
220            <name>GPIO0</name>
221            <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description>
222            <bitOffset>2</bitOffset>
223            <bitWidth>1</bitWidth>
224          </field>
225          <field derivedFrom="DMA">
226            <name>GPIO1</name>
227            <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description>
228            <bitOffset>3</bitOffset>
229            <bitWidth>1</bitWidth>
230          </field>
231          <field derivedFrom="DMA">
232            <name>TIMER0</name>
233            <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description>
234            <bitOffset>5</bitOffset>
235            <bitWidth>1</bitWidth>
236          </field>
237          <field derivedFrom="DMA">
238            <name>TIMER1</name>
239            <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description>
240            <bitOffset>6</bitOffset>
241            <bitWidth>1</bitWidth>
242          </field>
243          <field derivedFrom="DMA">
244            <name>TIMER2</name>
245            <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description>
246            <bitOffset>7</bitOffset>
247            <bitWidth>1</bitWidth>
248          </field>
249          <field derivedFrom="DMA">
250            <name>TIMER3</name>
251            <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description>
252            <bitOffset>8</bitOffset>
253            <bitWidth>1</bitWidth>
254          </field>
255          <field derivedFrom="DMA">
256            <name>TIMER4</name>
257            <description>Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks.</description>
258            <bitOffset>9</bitOffset>
259            <bitWidth>1</bitWidth>
260          </field>
261          <field derivedFrom="DMA">
262            <name>TIMER5</name>
263            <description>Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks.</description>
264            <bitOffset>10</bitOffset>
265            <bitWidth>1</bitWidth>
266          </field>
267          <field derivedFrom="DMA">
268            <name>UART0</name>
269            <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description>
270            <bitOffset>11</bitOffset>
271            <bitWidth>1</bitWidth>
272          </field>
273          <field derivedFrom="DMA">
274            <name>UART1</name>
275            <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description>
276            <bitOffset>12</bitOffset>
277            <bitWidth>1</bitWidth>
278          </field>
279          <field derivedFrom="DMA">
280            <name>SPI1</name>
281            <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description>
282            <bitOffset>13</bitOffset>
283            <bitWidth>1</bitWidth>
284          </field>
285          <field derivedFrom="DMA">
286            <name>SPI2</name>
287            <description>SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description>
288            <bitOffset>14</bitOffset>
289            <bitWidth>1</bitWidth>
290          </field>
291          <field derivedFrom="DMA">
292            <name>I2C0</name>
293            <description>I2C0 Reset.</description>
294            <bitOffset>16</bitOffset>
295            <bitWidth>1</bitWidth>
296          </field>
297          <field derivedFrom="DMA">
298            <name>RTC</name>
299            <description>Real Time Clock Reset.</description>
300            <bitOffset>17</bitOffset>
301            <bitWidth>1</bitWidth>
302          </field>
303          <field derivedFrom="DMA">
304            <name>CRYPTO</name>
305            <description>Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.</description>
306            <bitOffset>18</bitOffset>
307            <bitWidth>1</bitWidth>
308          </field>
309          <field derivedFrom="DMA">
310            <name>SMPHR</name>
311            <description>SMPHR Reset. Setting this bit to 1 resets the SMPHR block.</description>
312            <bitOffset>22</bitOffset>
313            <bitWidth>1</bitWidth>
314          </field>
315          <field derivedFrom="DMA">
316            <name>USB</name>
317            <description>USB Reset. Setting this bit resets both USB blocks.</description>
318            <bitOffset>23</bitOffset>
319            <bitWidth>1</bitWidth>
320          </field>
321          <field derivedFrom="DMA">
322            <name>ADC</name>
323            <description>Analog to Digital Reset.</description>
324            <bitOffset>26</bitOffset>
325            <bitWidth>1</bitWidth>
326          </field>
327          <field derivedFrom="DMA">
328            <name>DMA1</name>
329            <description>DMA 1 Reset.</description>
330            <bitOffset>27</bitOffset>
331            <bitWidth>1</bitWidth>
332          </field>
333          <field derivedFrom="DMA">
334            <name>UART2</name>
335            <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description>
336            <bitOffset>28</bitOffset>
337            <bitWidth>1</bitWidth>
338          </field>
339          <field derivedFrom="DMA">
340            <name>SRST</name>
341            <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description>
342            <bitOffset>29</bitOffset>
343            <bitWidth>1</bitWidth>
344          </field>
345          <field derivedFrom="DMA">
346            <name>PRST</name>
347            <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description>
348            <bitOffset>30</bitOffset>
349            <bitWidth>1</bitWidth>
350          </field>
351          <field derivedFrom="DMA">
352            <name>SYSTEM</name>
353            <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description>
354            <bitOffset>31</bitOffset>
355            <bitWidth>1</bitWidth>
356          </field>
357        </fields>
358      </register>
359      <register>
360        <name>CLKCN</name>
361        <description>Clock Control.</description>
362        <addressOffset>0x08</addressOffset>
363        <resetValue>0x00000008</resetValue>
364        <fields>
365          <field>
366            <name>PSC</name>
367            <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description>
368            <bitOffset>6</bitOffset>
369            <bitWidth>3</bitWidth>
370            <enumeratedValues>
371              <enumeratedValue>
372                <name>div1</name>
373                <description>Divide by 1.</description>
374                <value>0</value>
375              </enumeratedValue>
376              <enumeratedValue>
377                <name>div2</name>
378                <description>Divide by 2.</description>
379                <value>1</value>
380              </enumeratedValue>
381              <enumeratedValue>
382                <name>div4</name>
383                <description>Divide by 4.</description>
384                <value>2</value>
385              </enumeratedValue>
386              <enumeratedValue>
387                <name>div8</name>
388                <description>Divide by 8.</description>
389                <value>3</value>
390              </enumeratedValue>
391              <enumeratedValue>
392                <name>div16</name>
393                <description>Divide by 16.</description>
394                <value>4</value>
395              </enumeratedValue>
396              <enumeratedValue>
397                <name>div32</name>
398                <description>Divide by 32.</description>
399                <value>5</value>
400              </enumeratedValue>
401              <enumeratedValue>
402                <name>div64</name>
403                <description>Divide by 64.</description>
404                <value>6</value>
405              </enumeratedValue>
406              <enumeratedValue>
407                <name>div128</name>
408                <description>Divide by 128.</description>
409                <value>7</value>
410              </enumeratedValue>
411            </enumeratedValues>
412          </field>
413          <field>
414            <name>CLKSEL</name>
415            <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description>
416            <bitOffset>9</bitOffset>
417            <bitWidth>3</bitWidth>
418            <enumeratedValues>
419              <enumeratedValue>
420                <name>HIRC</name>
421                <description>HIRC Clock</description>
422                <value>0</value>
423              </enumeratedValue>
424              <enumeratedValue>
425                <name>XTAL32M</name>
426                <description>32MHz Crystal is used for the system clock.</description>
427                <value>2</value>
428              </enumeratedValue>
429              <enumeratedValue>
430                <name>LIRC8</name>
431                <description>8kHz LIRC is used for the system clock.</description>
432                <value>3</value>
433              </enumeratedValue>
434              <enumeratedValue>
435                <name>HIRC96</name>
436                <description>The internal 96 MHz oscillator is used for the system clock.</description>
437                <value>4</value>
438              </enumeratedValue>
439              <enumeratedValue>
440                <name>HIRC8</name>
441                <description>The internal 8 MHz oscillator is used for the system clock.</description>
442                <value>5</value>
443              </enumeratedValue>
444              <enumeratedValue>
445                <name>XTAL32k</name>
446                <description> 32kHz is used for the system clock.</description>
447                <value>6</value>
448              </enumeratedValue>
449            </enumeratedValues>
450          </field>
451          <field>
452            <name>CKRDY</name>
453            <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description>
454            <bitOffset>13</bitOffset>
455            <bitWidth>1</bitWidth>
456            <access>read-only</access>
457            <enumeratedValues>
458              <enumeratedValue>
459                <name>busy</name>
460                <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description>
461                <value>0</value>
462              </enumeratedValue>
463              <enumeratedValue>
464                <name>ready</name>
465                <description>System clock running from CLKSEL clock source.</description>
466                <value>1</value>
467              </enumeratedValue>
468            </enumeratedValues>
469          </field>
470          <field>
471            <name>CCD</name>
472            <description>Cryptographic clock divider</description>
473            <bitOffset>15</bitOffset>
474            <bitWidth>1</bitWidth>
475            <access>read-only</access>
476            <enumeratedValues>
477              <enumeratedValue>
478                <name>non_div</name>
479                <description>The cryptographic accelerator clock is running in non-divided mode.</description>
480                <value>0</value>
481              </enumeratedValue>
482              <enumeratedValue>
483                <name>div</name>
484                <description>The cryptographic accelerator clock is running in divided mode.</description>
485                <value>1</value>
486              </enumeratedValue>
487            </enumeratedValues>
488          </field>
489          <field>
490            <name>X32M_EN</name>
491            <description>32MHz Crystal Oscillator Enable.</description>
492            <bitOffset>16</bitOffset>
493            <bitWidth>1</bitWidth>
494            <enumeratedValues>
495              <enumeratedValue>
496                <name>dis</name>
497                <description>Is Disabled.</description>
498                <value>0</value>
499              </enumeratedValue>
500              <enumeratedValue>
501                <name>en</name>
502                <description>Is Enabled.</description>
503                <value>1</value>
504              </enumeratedValue>
505            </enumeratedValues>
506          </field>
507          <field>
508            <name>X32K_EN</name>
509            <description>32kHz Crystal Oscillator Enable.</description>
510            <bitOffset>17</bitOffset>
511            <bitWidth>1</bitWidth>
512            <enumeratedValues>
513              <enumeratedValue>
514                <name>dis</name>
515                <description>Is Disabled.</description>
516                <value>0</value>
517              </enumeratedValue>
518              <enumeratedValue>
519                <name>en</name>
520                <description>Is Enabled.</description>
521                <value>1</value>
522              </enumeratedValue>
523            </enumeratedValues>
524          </field>
525          <field derivedFrom="X32K_EN">
526            <name>HIRC_EN</name>
527            <description>60MHz High Frequency Internal Reference Clock Enable.</description>
528            <bitOffset>18</bitOffset>
529            <bitWidth>1</bitWidth>
530          </field>
531          <field derivedFrom="X32K_EN">
532            <name>HIRC96M_EN</name>
533            <description>96MHz High Frequency Internal Reference Clock Enable.</description>
534            <bitOffset>19</bitOffset>
535            <bitWidth>1</bitWidth>
536          </field>
537          <field derivedFrom="X32K_EN">
538            <name>HIRC8M_EN</name>
539            <description>8MHz High Frequency Internal Reference Clock Enable.</description>
540            <bitOffset>20</bitOffset>
541            <bitWidth>1</bitWidth>
542          </field>
543          <field>
544            <name>HIRC8M_VS</name>
545            <description>8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M.</description>
546            <bitOffset>21</bitOffset>
547            <bitWidth>1</bitWidth>
548            <enumeratedValues>
549              <enumeratedValue>
550                <name>Vcor</name>
551                <description>VCore Supply</description>
552                <value>0</value>
553              </enumeratedValue>
554              <enumeratedValue>
555                <name>1V</name>
556                <description>Dedicated 1v regulated supply.</description>
557                <value>1</value>
558              </enumeratedValue>
559            </enumeratedValues>
560          </field>
561          <field>
562            <name>X32M_RDY</name>
563            <description>32MHz Crystal Oscillator Ready</description>
564            <bitOffset>24</bitOffset>
565            <bitWidth>1</bitWidth>
566            <access>read-only</access>
567            <enumeratedValues>
568              <enumeratedValue>
569                <name>not</name>
570                <description>Is not Ready.</description>
571                <value>0</value>
572              </enumeratedValue>
573              <enumeratedValue>
574                <name>ready</name>
575                <description>Is Ready.</description>
576                <value>1</value>
577              </enumeratedValue>
578            </enumeratedValues>
579          </field>
580          <field>
581            <name>X32K_RDY</name>
582            <description>32kHz Crystal Oscillator Ready</description>
583            <bitOffset>25</bitOffset>
584            <bitWidth>1</bitWidth>
585            <access>read-only</access>
586            <enumeratedValues>
587              <enumeratedValue>
588                <name>not</name>
589                <description>Is not Ready.</description>
590                <value>0</value>
591              </enumeratedValue>
592              <enumeratedValue>
593                <name>ready</name>
594                <description>Is Ready.</description>
595                <value>1</value>
596              </enumeratedValue>
597            </enumeratedValues>
598          </field>
599          <field derivedFrom="X32K_RDY">
600            <name>HIRC_RDY</name>
601            <description>60MHz HIRC Ready.</description>
602            <bitOffset>26</bitOffset>
603            <bitWidth>1</bitWidth>
604          </field>
605          <field derivedFrom="X32K_RDY">
606            <name>HIRC96M_RDY</name>
607            <description>96MHz HIRC Ready.</description>
608            <bitOffset>27</bitOffset>
609            <bitWidth>1</bitWidth>
610          </field>
611          <field derivedFrom="X32K_RDY">
612            <name>HIRC8M_RDY</name>
613            <description>8MHz HIRC Ready.</description>
614            <bitOffset>28</bitOffset>
615            <bitWidth>1</bitWidth>
616          </field>
617        </fields>
618      </register>
619      <register>
620        <name>PM</name>
621        <description>Power Management.</description>
622        <addressOffset>0x0C</addressOffset>
623        <fields>
624          <field>
625            <name>MODE</name>
626            <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description>
627            <bitOffset>0</bitOffset>
628            <bitWidth>3</bitWidth>
629            <enumeratedValues>
630              <enumeratedValue>
631                <name>active</name>
632                <description>Active Mode.</description>
633                <value>0</value>
634              </enumeratedValue>
635              <enumeratedValue>
636                <name>deepsleep</name>
637                <description>DeepSleep Mode.</description>
638                <value>2</value>
639              </enumeratedValue>
640              <enumeratedValue>
641                <name>shutdown</name>
642                <description>Shutdown Mode.</description>
643                <value>3</value>
644              </enumeratedValue>
645              <enumeratedValue>
646                <name>backup</name>
647                <description>Backup Mode.</description>
648                <value>4</value>
649              </enumeratedValue>
650            </enumeratedValues>
651          </field>
652          <field>
653            <name>GPIOWKEN</name>
654            <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description>
655            <bitOffset>4</bitOffset>
656            <bitWidth>1</bitWidth>
657            <enumeratedValues>
658              <enumeratedValue>
659                <name>dis</name>
660                <description>Wake Up Disable.</description>
661                <value>0</value>
662              </enumeratedValue>
663              <enumeratedValue>
664                <name>en</name>
665                <description>Wake Up Enable.</description>
666                <value>1</value>
667              </enumeratedValue>
668            </enumeratedValues>
669          </field>
670          <field derivedFrom="GPIOWKEN">
671            <name>RTCWKEN</name>
672            <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description>
673            <bitOffset>5</bitOffset>
674            <bitWidth>1</bitWidth>
675          </field>
676          <field derivedFrom="GPIOWKEN">
677            <name>USBWKEN</name>
678            <description>USB Wake Up Enable. This bit enables USB activity as wakeup source.</description>
679            <bitOffset>6</bitOffset>
680            <bitWidth>1</bitWidth>
681          </field>
682          <field derivedFrom="GPIOWKEN">
683            <name>WUTWKEN</name>
684            <description>WUT Wake Up Enable. This bit enables WUT IRQ as wakeup source.</description>
685            <bitOffset>7</bitOffset>
686            <bitWidth>1</bitWidth>
687          </field>
688          <field derivedFrom="GPIOWKEN">
689            <name>compwken</name>
690            <description>COMPARATOR Input Wake Up Enable. This bit enables COMP IRQ activity as wakeup source.</description>
691            <bitOffset>8</bitOffset>
692            <bitWidth>1</bitWidth>
693          </field>
694          <field>
695            <name>HIRCPD</name>
696            <description>HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. </description>
697            <bitOffset>15</bitOffset>
698            <bitWidth>1</bitWidth>
699            <enumeratedValues>
700              <enumeratedValue>
701                <name>active</name>
702                <description>Mode is Active.</description>
703                <value>0</value>
704              </enumeratedValue>
705              <enumeratedValue>
706                <name>deepsleep</name>
707                <description>Powered down in DEEPSLEEP.</description>
708                <value>1</value>
709              </enumeratedValue>
710            </enumeratedValues>
711          </field>
712          <field derivedFrom="HIRCPD">
713            <name>HIRC96MPD</name>
714            <description>96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. </description>
715            <bitOffset>16</bitOffset>
716            <bitWidth>1</bitWidth>
717          </field>
718          <field derivedFrom="HIRCPD">
719            <name>HIRC8MPD</name>
720            <description>8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. </description>
721            <bitOffset>17</bitOffset>
722            <bitWidth>1</bitWidth>
723          </field>
724          <field>
725            <name>XTALPB</name>
726            <description>32MHz Bluetooth Oscillator Bypass. </description>
727            <bitOffset>20</bitOffset>
728            <bitWidth>1</bitWidth>
729          </field>
730        </fields>
731      </register>
732      <register>
733        <name>PCKDIV</name>
734        <description>Peripheral Clock Divider.</description>
735        <addressOffset>0x18</addressOffset>
736        <resetValue>0x00000001</resetValue>
737        <fields>
738          <field>
739            <name>SDHCFRQ</name>
740            <description>SDHC Clock Frequency. This bits defines the clock frequency of SDHC.</description>
741            <bitOffset>7</bitOffset>
742            <bitWidth>1</bitWidth>
743            <enumeratedValues>
744              <enumeratedValue>
745                <name>48MHz</name>
746                <value>0</value>
747              </enumeratedValue>
748              <enumeratedValue>
749                <name>24MHz</name>
750                <value>1</value>
751              </enumeratedValue>
752            </enumeratedValues>
753          </field>
754          <field>
755            <name>ADCFRQ</name>
756            <description>ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ).</description>
757            <bitOffset>10</bitOffset>
758            <bitWidth>4</bitWidth>
759          </field>
760          <field>
761            <name>AONCD</name>
762            <description>Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.</description>
763            <bitOffset>14</bitOffset>
764            <bitWidth>2</bitWidth>
765            <enumeratedValues>
766              <enumeratedValue>
767                <name>div_4</name>
768                <description>PCLK divide by 4.</description>
769                <value>0</value>
770              </enumeratedValue>
771              <enumeratedValue>
772                <name>div_8</name>
773                <description>PCLK divide by 8.</description>
774                <value>1</value>
775              </enumeratedValue>
776              <enumeratedValue>
777                <name>div_16</name>
778                <description>PCLK divide by 16.</description>
779                <value>2</value>
780              </enumeratedValue>
781              <enumeratedValue>
782                <name>div_32</name>
783                <description>PCLK divide by 32.</description>
784                <value>3</value>
785              </enumeratedValue>
786            </enumeratedValues>
787          </field>
788        </fields>
789      </register>
790      <register>
791        <name>PERCKCN0</name>
792        <description>Peripheral Clock Disable.</description>
793        <addressOffset>0x24</addressOffset>
794        <fields>
795          <field>
796            <name>GPIO0D</name>
797            <description>GPIO0 Disable.</description>
798            <bitOffset>0</bitOffset>
799            <bitWidth>1</bitWidth>
800            <enumeratedValues>
801              <enumeratedValue>
802                <name>en</name>
803                <description>enable it.</description>
804                <value>0</value>
805              </enumeratedValue>
806              <enumeratedValue>
807                <name>dis</name>
808                <description>disable it.</description>
809                <value>1</value>
810              </enumeratedValue>
811            </enumeratedValues>
812          </field>
813          <field derivedFrom="GPIO0D">
814            <name>GPIO1D</name>
815            <description>GPIO1 Disable.</description>
816            <bitOffset>1</bitOffset>
817            <bitWidth>1</bitWidth>
818          </field>
819          <field derivedFrom="GPIO0D">
820            <name>USBD</name>
821            <description>USB Disable.</description>
822            <bitOffset>3</bitOffset>
823            <bitWidth>1</bitWidth>
824          </field>
825          <field derivedFrom="GPIO0D">
826            <name>DMAD</name>
827            <description>DMA Disable.</description>
828            <bitOffset>5</bitOffset>
829            <bitWidth>1</bitWidth>
830          </field>
831          <field derivedFrom="GPIO0D">
832            <name>SPI1D</name>
833            <description>SPI 1 Disable.</description>
834            <bitOffset>6</bitOffset>
835            <bitWidth>1</bitWidth>
836          </field>
837          <field derivedFrom="GPIO0D">
838            <name>SPI2D</name>
839            <description>SPI 2 Disable.</description>
840            <bitOffset>7</bitOffset>
841            <bitWidth>1</bitWidth>
842          </field>
843          <field derivedFrom="GPIO0D">
844            <name>UART0D</name>
845            <description>UART 0 Disable.</description>
846            <bitOffset>9</bitOffset>
847            <bitWidth>1</bitWidth>
848          </field>
849          <field derivedFrom="GPIO0D">
850            <name>UART1D</name>
851            <description>UART 1 Disable.</description>
852            <bitOffset>10</bitOffset>
853            <bitWidth>1</bitWidth>
854          </field>
855          <field derivedFrom="GPIO0D">
856            <name>I2C0D</name>
857            <description>I2C 0 Disable.</description>
858            <bitOffset>13</bitOffset>
859            <bitWidth>1</bitWidth>
860          </field>
861          <field derivedFrom="GPIO0D">
862            <name>CRYPTOD</name>
863            <description>Crypto Disable.</description>
864            <bitOffset>14</bitOffset>
865            <bitWidth>1</bitWidth>
866          </field>
867          <field derivedFrom="GPIO0D">
868            <name>TIMER0D</name>
869            <description>Timer 0 Disable.</description>
870            <bitOffset>15</bitOffset>
871            <bitWidth>1</bitWidth>
872          </field>
873          <field derivedFrom="GPIO0D">
874            <name>TIMER1D</name>
875            <description>Timer 1 Disable.</description>
876            <bitOffset>16</bitOffset>
877            <bitWidth>1</bitWidth>
878          </field>
879          <field derivedFrom="GPIO0D">
880            <name>TIMER2D</name>
881            <description>Timer 2 Disable.</description>
882            <bitOffset>17</bitOffset>
883            <bitWidth>1</bitWidth>
884          </field>
885          <field derivedFrom="GPIO0D">
886            <name>TIMER3D</name>
887            <description>Timer 3 Disable.</description>
888            <bitOffset>18</bitOffset>
889            <bitWidth>1</bitWidth>
890          </field>
891          <field derivedFrom="GPIO0D">
892            <name>TIMER4D</name>
893            <description>Timer 4 Disable.</description>
894            <bitOffset>19</bitOffset>
895            <bitWidth>1</bitWidth>
896          </field>
897          <field derivedFrom="GPIO0D">
898            <name>TIMER5D</name>
899            <description>Timer 5 Disable.</description>
900            <bitOffset>20</bitOffset>
901            <bitWidth>1</bitWidth>
902          </field>
903          <field derivedFrom="GPIO0D">
904            <name>ADCD</name>
905            <description>ADC Disable.</description>
906            <bitOffset>23</bitOffset>
907            <bitWidth>1</bitWidth>
908          </field>
909          <field derivedFrom="GPIO0D">
910            <name>I2C1D</name>
911            <description>I2C 1 Disable.</description>
912            <bitOffset>28</bitOffset>
913            <bitWidth>1</bitWidth>
914          </field>
915          <field derivedFrom="GPIO0D">
916            <name>PTD</name>
917            <description>PT Clock Disable.</description>
918            <bitOffset>29</bitOffset>
919            <bitWidth>1</bitWidth>
920          </field>
921          <field derivedFrom="GPIO0D">
922            <name>SPIXIPD</name>
923            <description>SPI XiP Disable.</description>
924            <bitOffset>30</bitOffset>
925            <bitWidth>1</bitWidth>
926          </field>
927          <field derivedFrom="GPIO0D">
928            <name>SPIMD</name>
929            <description>SPI XiP Master Controller Disable.</description>
930            <bitOffset>31</bitOffset>
931            <bitWidth>1</bitWidth>
932          </field>
933        </fields>
934      </register>
935      <register>
936        <name>MEMCKCN</name>
937        <description>Memory Clock Control Register.</description>
938        <addressOffset>0x28</addressOffset>
939        <fields>
940          <field>
941            <name>FWS</name>
942            <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description>
943            <bitOffset>0</bitOffset>
944            <bitWidth>3</bitWidth>
945          </field>
946          <field>
947            <name>SYSRAM0LS</name>
948            <description>System RAM 0 Light Sleep Mode.</description>
949            <bitOffset>16</bitOffset>
950            <bitWidth>1</bitWidth>
951            <enumeratedValues>
952              <enumeratedValue>
953                <name>active</name>
954                <description>RAM is active.</description>
955                <value>0</value>
956              </enumeratedValue>
957              <enumeratedValue>
958                <name>light_sleep</name>
959                <description>RAM is in Light Sleep mode.</description>
960                <value>1</value>
961              </enumeratedValue>
962            </enumeratedValues>
963          </field>
964          <field derivedFrom="SYSRAM0LS">
965            <name>SYSRAM1LS</name>
966            <description>System RAM 1 Light Sleep Mode.</description>
967            <bitOffset>17</bitOffset>
968            <bitWidth>1</bitWidth>
969          </field>
970          <field derivedFrom="SYSRAM0LS">
971            <name>SYSRAM2LS</name>
972            <description>System RAM 2 Light Sleep Mode.</description>
973            <bitOffset>18</bitOffset>
974            <bitWidth>1</bitWidth>
975          </field>
976          <field derivedFrom="SYSRAM0LS">
977            <name>SYSRAM3LS</name>
978            <description>System RAM 3 Light Sleep Mode.</description>
979            <bitOffset>19</bitOffset>
980            <bitWidth>1</bitWidth>
981          </field>
982          <field derivedFrom="SYSRAM0LS">
983            <name>SYSRAM4LS</name>
984            <description>System RAM 4 Light Sleep Mode.</description>
985            <bitOffset>20</bitOffset>
986            <bitWidth>1</bitWidth>
987          </field>
988          <field derivedFrom="SYSRAM0LS">
989            <name>SYSRAM5LS</name>
990            <description>System RAM 5 Light Sleep Mode.</description>
991            <bitOffset>21</bitOffset>
992            <bitWidth>1</bitWidth>
993          </field>
994          <field derivedFrom="SYSRAM0LS">
995            <name>SYSRAM6LS</name>
996            <description>System RAM 6 Light Sleep Mode.</description>
997            <bitOffset>22</bitOffset>
998            <bitWidth>1</bitWidth>
999          </field>
1000          <field derivedFrom="SYSRAM0LS">
1001            <name>ICACHELS</name>
1002            <description>ICache RAM Light Sleep Mode.</description>
1003            <bitOffset>24</bitOffset>
1004            <bitWidth>1</bitWidth>
1005          </field>
1006          <field derivedFrom="SYSRAM0LS">
1007            <name>ICACHEXIPLS</name>
1008            <description>ICACHE-XIP RAM Light Sleep Mode.</description>
1009            <bitOffset>25</bitOffset>
1010            <bitWidth>1</bitWidth>
1011          </field>
1012          <field derivedFrom="SYSRAM0LS">
1013            <name>SCACHELS</name>
1014            <description>SysCache RAM Light Sleep Mode.</description>
1015            <bitOffset>26</bitOffset>
1016            <bitWidth>1</bitWidth>
1017          </field>
1018          <field derivedFrom="SYSRAM0LS">
1019            <name>CRYPTOLS</name>
1020            <description>CRYPTO RAM Light Sleep Mode.</description>
1021            <bitOffset>27</bitOffset>
1022            <bitWidth>1</bitWidth>
1023          </field>
1024          <field derivedFrom="SYSRAM0LS">
1025            <name>USBLS</name>
1026            <description>USB FIFO Light Sleep Mode.</description>
1027            <bitOffset>28</bitOffset>
1028            <bitWidth>1</bitWidth>
1029          </field>
1030          <field derivedFrom="SYSRAM0LS">
1031            <name>ROM0LS</name>
1032            <description>ROM Light Sleep Mode.</description>
1033            <bitOffset>29</bitOffset>
1034            <bitWidth>1</bitWidth>
1035          </field>
1036          <field derivedFrom="SYSRAM0LS">
1037            <name>ROM1LS</name>
1038            <description>ROM1 Light Sleep Mode.</description>
1039            <bitOffset>30</bitOffset>
1040            <bitWidth>1</bitWidth>
1041          </field>
1042          <field derivedFrom="SYSRAM0LS">
1043            <name>ICACHE1LS</name>
1044            <description>ICache RAM Light Sleep Mode.</description>
1045            <bitOffset>31</bitOffset>
1046            <bitWidth>1</bitWidth>
1047          </field>
1048        </fields>
1049      </register>
1050      <register>
1051        <name>MEMZCN</name>
1052        <description>Memory Zeroize Control.</description>
1053        <addressOffset>0x2C</addressOffset>
1054        <fields>
1055          <field>
1056            <name>SRAM0Z</name>
1057            <description>System RAM Block 0.</description>
1058            <bitOffset>0</bitOffset>
1059            <bitWidth>1</bitWidth>
1060            <enumeratedValues>
1061              <enumeratedValue>
1062                <name>nop</name>
1063                <description>No operation/complete.</description>
1064                <value>0</value>
1065              </enumeratedValue>
1066              <enumeratedValue>
1067                <name>start</name>
1068                <description>Start operation.</description>
1069                <value>1</value>
1070              </enumeratedValue>
1071            </enumeratedValues>
1072          </field>
1073          <field derivedFrom="SRAM0Z">
1074            <name>SRAM1Z</name>
1075            <description>System RAM Block 1.</description>
1076            <bitOffset>1</bitOffset>
1077            <bitWidth>1</bitWidth>
1078          </field>
1079          <field derivedFrom="SRAM0Z">
1080            <name>SRAM2</name>
1081            <description>System RAM Block 2.</description>
1082            <bitOffset>2</bitOffset>
1083            <bitWidth>1</bitWidth>
1084          </field>
1085          <field derivedFrom="SRAM0Z">
1086            <name>SRAM3Z</name>
1087            <description>System RAM Block 3.</description>
1088            <bitOffset>3</bitOffset>
1089            <bitWidth>1</bitWidth>
1090          </field>
1091          <field derivedFrom="SRAM0Z">
1092            <name>SRAM4Z</name>
1093            <description>System RAM Block 4.</description>
1094            <bitOffset>4</bitOffset>
1095            <bitWidth>1</bitWidth>
1096          </field>
1097          <field derivedFrom="SRAM0Z">
1098            <name>SRAM5Z</name>
1099            <description>System RAM Block 5.</description>
1100            <bitOffset>5</bitOffset>
1101            <bitWidth>1</bitWidth>
1102          </field>
1103          <field derivedFrom="SRAM0Z">
1104            <name>SRAM6Z</name>
1105            <description>System RAM Block 6.</description>
1106            <bitOffset>6</bitOffset>
1107            <bitWidth>1</bitWidth>
1108          </field>
1109          <field derivedFrom="SRAM0Z">
1110            <name>ICACHEZ</name>
1111            <description>Instruction Cache.</description>
1112            <bitOffset>8</bitOffset>
1113            <bitWidth>1</bitWidth>
1114          </field>
1115          <field derivedFrom="SRAM0Z">
1116            <name>ICACHEXIPZ</name>
1117            <description>Instruction Cache XIP Data and Tag Ram zeroizatoin.</description>
1118            <bitOffset>9</bitOffset>
1119            <bitWidth>1</bitWidth>
1120          </field>
1121          <field derivedFrom="SRAM0Z">
1122            <name>SCACHEDATAZ</name>
1123            <description>System Cache Data Ram Zeroization.</description>
1124            <bitOffset>10</bitOffset>
1125            <bitWidth>1</bitWidth>
1126          </field>
1127          <field derivedFrom="SRAM0Z">
1128            <name>SCACHETAGZ</name>
1129            <description>System Cache Tag Zeroization.</description>
1130            <bitOffset>11</bitOffset>
1131            <bitWidth>1</bitWidth>
1132          </field>
1133          <field derivedFrom="SRAM0Z">
1134            <name>CRYPTOZ</name>
1135            <description>Crypto (MAA) Memory.</description>
1136            <bitOffset>12</bitOffset>
1137            <bitWidth>1</bitWidth>
1138          </field>
1139          <field derivedFrom="SRAM0Z">
1140            <name>USBFIFOZ</name>
1141            <description>USB FIFO Zeroizatoin.</description>
1142            <bitOffset>13</bitOffset>
1143            <bitWidth>1</bitWidth>
1144          </field>
1145          <field derivedFrom="SRAM0Z">
1146            <name>ICACHE1Z</name>
1147            <description>Instruction Cache.</description>
1148            <bitOffset>14</bitOffset>
1149            <bitWidth>1</bitWidth>
1150          </field>
1151        </fields>
1152      </register>
1153      <register>
1154        <name>SYSST</name>
1155        <description>System Status Register.</description>
1156        <addressOffset>0x40</addressOffset>
1157        <fields>
1158          <field>
1159            <name>ICELOCK</name>
1160            <description>ARM ICE Lock Status.</description>
1161            <bitOffset>0</bitOffset>
1162            <bitWidth>1</bitWidth>
1163            <enumeratedValues>
1164              <enumeratedValue>
1165                <name>unlocked</name>
1166                <description>ICE is unlocked.</description>
1167                <value>0</value>
1168              </enumeratedValue>
1169              <enumeratedValue>
1170                <name>locked</name>
1171                <description>ICE is locked.</description>
1172                <value>1</value>
1173              </enumeratedValue>
1174            </enumeratedValues>
1175          </field>
1176          <field>
1177            <name>CODEINTERR</name>
1178            <description>Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. </description>
1179            <bitOffset>1</bitOffset>
1180            <bitWidth>1</bitWidth>
1181            <enumeratedValues>
1182              <enumeratedValue>
1183                <name>norm</name>
1184                <description>Normal Operating Condition.</description>
1185                <value>0</value>
1186              </enumeratedValue>
1187              <enumeratedValue>
1188                <name>code</name>
1189                <description>Code Integrity Error.</description>
1190                <value>1</value>
1191              </enumeratedValue>
1192            </enumeratedValues>
1193          </field>
1194          <field>
1195            <name>SCMEMF</name>
1196            <description>System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.</description>
1197            <bitOffset>5</bitOffset>
1198            <bitWidth>1</bitWidth>
1199            <enumeratedValues>
1200              <enumeratedValue>
1201                <name>norm</name>
1202                <description>Normal Operating Condition.</description>
1203                <value>0</value>
1204              </enumeratedValue>
1205              <enumeratedValue>
1206                <name>memory</name>
1207                <description>Memory Fault.</description>
1208                <value>1</value>
1209              </enumeratedValue>
1210            </enumeratedValues>
1211          </field>
1212        </fields>
1213      </register>
1214      <register>
1215        <name>RSTR1</name>
1216        <description>Reset 1.</description>
1217        <addressOffset>0x44</addressOffset>
1218        <fields>
1219          <field>
1220            <name>I2C1</name>
1221            <description>I2C1 Reset.</description>
1222            <bitOffset>0</bitOffset>
1223            <bitWidth>1</bitWidth>
1224            <enumeratedValues>
1225              <name>reset_read</name>
1226              <usage>read</usage>
1227              <enumeratedValue>
1228                <name>reset_done</name>
1229                <description>Reset complete.</description>
1230                <value>0</value>
1231              </enumeratedValue>
1232              <enumeratedValue>
1233                <name>busy</name>
1234                <description>Starts reset or indicates reset in progress.</description>
1235                <value>1</value>
1236              </enumeratedValue>
1237            </enumeratedValues>
1238          </field>
1239          <field derivedFrom="I2C1">
1240            <name>PT</name>
1241            <description>PT Reset.</description>
1242            <bitOffset>1</bitOffset>
1243            <bitWidth>1</bitWidth>
1244          </field>
1245          <field derivedFrom="I2C1">
1246            <name>SPIXIP</name>
1247            <description>SPI XiP Master Reset.</description>
1248            <bitOffset>3</bitOffset>
1249            <bitWidth>1</bitWidth>
1250          </field>
1251          <field derivedFrom="I2C1">
1252            <name>XSPIM</name>
1253            <description>GSPI XiP Master Controller Reset.</description>
1254            <bitOffset>4</bitOffset>
1255            <bitWidth>1</bitWidth>
1256          </field>
1257          <field derivedFrom="I2C1">
1258            <name>SDHC</name>
1259            <description>SDHC/SDIO Reset.</description>
1260            <bitOffset>6</bitOffset>
1261            <bitWidth>1</bitWidth>
1262          </field>
1263          <field derivedFrom="I2C1">
1264            <name>OWIRE</name>
1265            <description>OWIRE Reset.</description>
1266            <bitOffset>7</bitOffset>
1267            <bitWidth>1</bitWidth>
1268          </field>
1269          <field derivedFrom="I2C1">
1270            <name>WDT1</name>
1271            <description>WDT1 Reset.</description>
1272            <bitOffset>8</bitOffset>
1273            <bitWidth>1</bitWidth>
1274          </field>
1275          <field derivedFrom="I2C1">
1276            <name>SPI0</name>
1277            <description>SPI0 Reset.</description>
1278            <bitOffset>9</bitOffset>
1279            <bitWidth>1</bitWidth>
1280          </field>
1281          <field derivedFrom="I2C1">
1282            <name>SPIXMEM</name>
1283            <description>SPIXMEM Reset.</description>
1284            <bitOffset>15</bitOffset>
1285            <bitWidth>1</bitWidth>
1286          </field>
1287          <field derivedFrom="I2C1">
1288            <name>SMPHR</name>
1289            <description>SMPHR Reset.</description>
1290            <bitOffset>16</bitOffset>
1291            <bitWidth>1</bitWidth>
1292          </field>
1293          <field derivedFrom="I2C1">
1294            <name>WDT2</name>
1295            <description>WDT2 Reset.</description>
1296            <bitOffset>17</bitOffset>
1297            <bitWidth>1</bitWidth>
1298          </field>
1299          <field derivedFrom="I2C1">
1300            <name>BTLE</name>
1301            <description>BTLE Reset.</description>
1302            <bitOffset>18</bitOffset>
1303            <bitWidth>1</bitWidth>
1304          </field>
1305          <field derivedFrom="I2C1">
1306            <name>AUDIO</name>
1307            <description>AUDIO Reset.</description>
1308            <bitOffset>19</bitOffset>
1309            <bitWidth>1</bitWidth>
1310          </field>
1311          <field derivedFrom="I2C1">
1312            <name>I2C2</name>
1313            <description>I2C2 Reset.</description>
1314            <bitOffset>20</bitOffset>
1315            <bitWidth>1</bitWidth>
1316          </field>
1317          <field derivedFrom="I2C1">
1318            <name>RPU</name>
1319            <description>RPU Reset.</description>
1320            <bitOffset>21</bitOffset>
1321            <bitWidth>1</bitWidth>
1322          </field>
1323          <field derivedFrom="I2C1">
1324            <name>HTMR0</name>
1325            <description>HTMR0 Reset.</description>
1326            <bitOffset>22</bitOffset>
1327            <bitWidth>1</bitWidth>
1328          </field>
1329          <field derivedFrom="I2C1">
1330            <name>HTMR1</name>
1331            <description>HTMR1 Reset.</description>
1332            <bitOffset>23</bitOffset>
1333            <bitWidth>1</bitWidth>
1334          </field>
1335          <field derivedFrom="I2C1">
1336            <name>DVS</name>
1337            <description>DVS Reset.</description>
1338            <bitOffset>24</bitOffset>
1339            <bitWidth>1</bitWidth>
1340          </field>
1341          <field derivedFrom="I2C1">
1342            <name>SIMO</name>
1343            <description>SIMO Reset.</description>
1344            <bitOffset>25</bitOffset>
1345            <bitWidth>1</bitWidth>
1346          </field>
1347        </fields>
1348      </register>
1349      <register>
1350        <name>PERCKCN1</name>
1351        <description>Peripheral Clock Disable.</description>
1352        <addressOffset>0x48</addressOffset>
1353        <fields>
1354          <field>
1355            <name>BTLED</name>
1356            <description>BTLE Disable.</description>
1357            <bitOffset>0</bitOffset>
1358            <bitWidth>1</bitWidth>
1359            <enumeratedValues>
1360              <enumeratedValue>
1361                <name>en</name>
1362                <description>Enable.</description>
1363                <value>0</value>
1364              </enumeratedValue>
1365              <enumeratedValue>
1366                <name>dis</name>
1367                <description>Disable.</description>
1368                <value>1</value>
1369              </enumeratedValue>
1370            </enumeratedValues>
1371          </field>
1372          <field>
1373            <name>UART2D</name>
1374            <description>UART2 Disable.</description>
1375            <bitOffset>1</bitOffset>
1376            <bitWidth>1</bitWidth>
1377            <enumeratedValues>
1378              <enumeratedValue>
1379                <name>en</name>
1380                <description>Enable.</description>
1381                <value>0</value>
1382              </enumeratedValue>
1383              <enumeratedValue>
1384                <name>dis</name>
1385                <description>Disable.</description>
1386                <value>1</value>
1387              </enumeratedValue>
1388            </enumeratedValues>
1389          </field>
1390          <field derivedFrom="UART2D">
1391            <name>TRNGD</name>
1392            <description>TRNG Disable.</description>
1393            <bitOffset>2</bitOffset>
1394            <bitWidth>1</bitWidth>
1395          </field>
1396          <field derivedFrom="UART2D">
1397            <name>SCACHED</name>
1398            <description>System Cache Clock Disable.</description>
1399            <bitOffset>7</bitOffset>
1400            <bitWidth>1</bitWidth>
1401          </field>
1402          <field derivedFrom="UART2D">
1403            <name>SDMAD</name>
1404            <description>SDMA Clock Disable.</description>
1405            <bitOffset>8</bitOffset>
1406            <bitWidth>1</bitWidth>
1407          </field>
1408          <field derivedFrom="UART2D">
1409            <name>SMPHRD</name>
1410            <description>Semaphore Clock Disable.</description>
1411            <bitOffset>9</bitOffset>
1412            <bitWidth>1</bitWidth>
1413          </field>
1414          <field derivedFrom="UART2D">
1415            <name>SDHCD</name>
1416            <description>SDHC/SDIO Clock Disable.</description>
1417            <bitOffset>10</bitOffset>
1418            <bitWidth>1</bitWidth>
1419          </field>
1420          <field derivedFrom="UART2D">
1421            <name>ICACHEXIPD</name>
1422            <description>ICache XIP Clock Disable.</description>
1423            <bitOffset>12</bitOffset>
1424            <bitWidth>1</bitWidth>
1425          </field>
1426          <field derivedFrom="UART2D">
1427            <name>OWIRED</name>
1428            <description>One-Wire Clock Disable.</description>
1429            <bitOffset>13</bitOffset>
1430            <bitWidth>1</bitWidth>
1431          </field>
1432          <field derivedFrom="UART2D">
1433            <name>SPI0D</name>
1434            <description>SPI0 Clock Disable.</description>
1435            <bitOffset>14</bitOffset>
1436            <bitWidth>1</bitWidth>
1437          </field>
1438          <field derivedFrom="UART2D">
1439            <name>SPIXIPDD</name>
1440            <description>SPI-XIP Data Clock Disable</description>
1441            <bitOffset>20</bitOffset>
1442            <bitWidth>1</bitWidth>
1443          </field>
1444          <field derivedFrom="UART2D">
1445            <name>DMA1D</name>
1446            <description>DMA1 Clock Disable</description>
1447            <bitOffset>21</bitOffset>
1448            <bitWidth>1</bitWidth>
1449          </field>
1450          <field derivedFrom="UART2D">
1451            <name>AUDIOD</name>
1452            <description>AUDIO Clock Disable</description>
1453            <bitOffset>23</bitOffset>
1454            <bitWidth>1</bitWidth>
1455          </field>
1456          <field derivedFrom="UART2D">
1457            <name>I2C2D</name>
1458            <description>I2C 2 Clock Disable</description>
1459            <bitOffset>24</bitOffset>
1460            <bitWidth>1</bitWidth>
1461          </field>
1462          <field derivedFrom="UART2D">
1463            <name>HTMR0D</name>
1464            <description>HTMR 0 Clock Disable</description>
1465            <bitOffset>25</bitOffset>
1466            <bitWidth>1</bitWidth>
1467          </field>
1468          <field derivedFrom="UART2D">
1469            <name>HTMR1D</name>
1470            <description>HTMR 1 Clock Disable</description>
1471            <bitOffset>26</bitOffset>
1472            <bitWidth>1</bitWidth>
1473          </field>
1474          <field derivedFrom="UART2D">
1475            <name>WDT0D</name>
1476            <description>WDT0 Clock Disable</description>
1477            <bitOffset>27</bitOffset>
1478            <bitWidth>1</bitWidth>
1479          </field>
1480          <field derivedFrom="UART2D">
1481            <name>WDT1D</name>
1482            <description>WDT1 Clock Disable</description>
1483            <bitOffset>28</bitOffset>
1484            <bitWidth>1</bitWidth>
1485          </field>
1486          <field derivedFrom="UART2D">
1487            <name>WDT2D</name>
1488            <description>WDT2 Clock Disable</description>
1489            <bitOffset>29</bitOffset>
1490            <bitWidth>1</bitWidth>
1491          </field>
1492          <field derivedFrom="UART2D">
1493            <name>CPU1D</name>
1494            <description>CPU1 Clock Disable</description>
1495            <bitOffset>31</bitOffset>
1496            <bitWidth>1</bitWidth>
1497          </field>
1498        </fields>
1499      </register>
1500      <register>
1501        <name>EVENT_EN</name>
1502        <description>Event Enable Register.</description>
1503        <addressOffset>0x4C</addressOffset>
1504        <fields>
1505          <field>
1506            <name>CPU0DMAEVENT</name>
1507            <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description>
1508            <bitOffset>0</bitOffset>
1509            <bitWidth>1</bitWidth>
1510          </field>
1511          <field>
1512            <name>CPU0DMA1EVENT</name>
1513            <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description>
1514            <bitOffset>1</bitOffset>
1515            <bitWidth>1</bitWidth>
1516          </field>
1517          <field>
1518            <name>CPU0TXEVENT</name>
1519            <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].</description>
1520            <bitOffset>2</bitOffset>
1521            <bitWidth>1</bitWidth>
1522          </field>
1523          <field>
1524            <name>CPU1DMAEVENT</name>
1525            <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description>
1526            <bitOffset>3</bitOffset>
1527            <bitWidth>1</bitWidth>
1528          </field>
1529          <field>
1530            <name>CPU1DMA1EVENT</name>
1531            <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description>
1532            <bitOffset>4</bitOffset>
1533            <bitWidth>1</bitWidth>
1534          </field>
1535          <field>
1536            <name>CPU1TXEVENT</name>
1537            <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].</description>
1538            <bitOffset>5</bitOffset>
1539            <bitWidth>1</bitWidth>
1540          </field>
1541        </fields>
1542      </register>
1543      <register>
1544        <name>REVISION</name>
1545        <description>Revision Register.</description>
1546        <addressOffset>0x50</addressOffset>
1547        <access>read-only</access>
1548        <fields>
1549          <field>
1550            <name>REVISION</name>
1551            <description>Manufacturer Chip Revision. </description>
1552            <bitOffset>0</bitOffset>
1553            <bitWidth>16</bitWidth>
1554          </field>
1555        </fields>
1556      </register>
1557      <register>
1558        <name>SYSSIE</name>
1559        <description>System Status Interrupt Enable Register.</description>
1560        <addressOffset>0x54</addressOffset>
1561        <fields>
1562          <field>
1563            <name>ICEULIE</name>
1564            <description>ARM ICE Unlock Interrupt Enable.</description>
1565            <bitOffset>0</bitOffset>
1566            <bitWidth>1</bitWidth>
1567            <enumeratedValues>
1568              <enumeratedValue>
1569                <name>dis</name>
1570                <description>disabled.</description>
1571                <value>0</value>
1572              </enumeratedValue>
1573              <enumeratedValue>
1574                <name>en</name>
1575                <description>enabled.</description>
1576                <value>1</value>
1577              </enumeratedValue>
1578            </enumeratedValues>
1579          </field>
1580          <field derivedFrom="ICEULIE">
1581            <name>CIEIE</name>
1582            <description>Code Integrity Error Interrupt Enable.</description>
1583            <bitOffset>1</bitOffset>
1584            <bitWidth>1</bitWidth>
1585          </field>
1586          <field derivedFrom="ICEULIE">
1587            <name>SCMFIE</name>
1588            <description>System Cache Memory Fault Interrupt Enable.</description>
1589            <bitOffset>5</bitOffset>
1590            <bitWidth>1</bitWidth>
1591          </field>
1592        </fields>
1593      </register>
1594      <register>
1595        <name>ECC_ER</name>
1596        <description>ECC Error Register</description>
1597        <addressOffset>0x64</addressOffset>
1598        <fields>
1599          <field>
1600            <name>SYSRAM0ECCERR</name>
1601            <description>ECC System RAM0 Error Flag. Write 1 to clear.</description>
1602            <bitOffset>0</bitOffset>
1603            <bitWidth>1</bitWidth>
1604          </field>
1605          <field>
1606            <name>SYSRAM1ECCERR</name>
1607            <description>ECC System RAM1 Error Flag. Write 1 to clear.</description>
1608            <bitOffset>1</bitOffset>
1609            <bitWidth>1</bitWidth>
1610          </field>
1611          <field>
1612            <name>SYSRAM2ECCERR</name>
1613            <description>ECC System RAM2 Error Flag. Write 1 to clear.</description>
1614            <bitOffset>2</bitOffset>
1615            <bitWidth>1</bitWidth>
1616          </field>
1617          <field>
1618            <name>SYSRAM3ECCERR</name>
1619            <description>ECC System RAM3 Error Flag. Write 1 to clear.</description>
1620            <bitOffset>3</bitOffset>
1621            <bitWidth>1</bitWidth>
1622          </field>
1623          <field>
1624            <name>SYSRAM4ECCERR</name>
1625            <description>ECC System RAM4 Error Flag. Write 1 to clear.</description>
1626            <bitOffset>4</bitOffset>
1627            <bitWidth>1</bitWidth>
1628          </field>
1629          <field>
1630            <name>SYSRAM5ECCERR</name>
1631            <description>ECC System RAM5 Error Flag. Write 1 to clear.</description>
1632            <bitOffset>5</bitOffset>
1633            <bitWidth>1</bitWidth>
1634          </field>
1635          <field>
1636            <name>SYSRAM6ECCERR</name>
1637            <description>ECC System RAM6 Error Flag. Write 1 to clear.</description>
1638            <bitOffset>6</bitOffset>
1639            <bitWidth>1</bitWidth>
1640          </field>
1641          <field>
1642            <name>IC0ECCERR</name>
1643            <description>ECC Icache0 Error Flag. Write 1 to clear.</description>
1644            <bitOffset>8</bitOffset>
1645            <bitWidth>1</bitWidth>
1646          </field>
1647          <field>
1648            <name>IC1ECCERR</name>
1649            <description>ECC Icache1 Error Flag. Write 1 to clear.</description>
1650            <bitOffset>9</bitOffset>
1651            <bitWidth>1</bitWidth>
1652          </field>
1653          <field>
1654            <name>ICXIPECCERR</name>
1655            <description>ECC IcacheXIP Error Flag. Write 1 to clear.</description>
1656            <bitOffset>10</bitOffset>
1657            <bitWidth>1</bitWidth>
1658          </field>
1659          <field>
1660            <name>FL0ECCERR</name>
1661            <description>ECC Flash0 Error Flag. Write 1 to clear.</description>
1662            <bitOffset>11</bitOffset>
1663            <bitWidth>1</bitWidth>
1664          </field>
1665          <field>
1666            <name>FL1ECCERR</name>
1667            <description>ECC Flash1 Error Flag. Write 1 to clear.</description>
1668            <bitOffset>12</bitOffset>
1669            <bitWidth>1</bitWidth>
1670          </field>
1671        </fields>
1672      </register>
1673      <register>
1674        <name>ECC_CED</name>
1675        <description>ECC Correctable Error Detected Register</description>
1676        <addressOffset>0x68</addressOffset>
1677        <fields>
1678          <field>
1679            <name>SYSRAM0ECCNDED</name>
1680            <description>ECC System RAM0 Error Flag. Write 1 to clear.</description>
1681            <bitOffset>0</bitOffset>
1682            <bitWidth>1</bitWidth>
1683          </field>
1684          <field>
1685            <name>SYSRAM1ECCNDED</name>
1686            <description>ECC System RAM1 Not Double Error Detect. Write 1 to clear.</description>
1687            <bitOffset>1</bitOffset>
1688            <bitWidth>1</bitWidth>
1689          </field>
1690          <field>
1691            <name>SYSRAM2ECCNDED</name>
1692            <description>ECC System RAM2 Not Double Error Detect. Write 1 to clear.</description>
1693            <bitOffset>2</bitOffset>
1694            <bitWidth>1</bitWidth>
1695          </field>
1696          <field>
1697            <name>SYSRAM3ECCNDED</name>
1698            <description>ECC System RAM3 Not Double Error Detect. Write 1 to clear.</description>
1699            <bitOffset>3</bitOffset>
1700            <bitWidth>1</bitWidth>
1701          </field>
1702          <field>
1703            <name>SYSRAM4ECCNDED</name>
1704            <description>ECC System RAM4 Not Double Error Detect. Write 1 to clear.</description>
1705            <bitOffset>4</bitOffset>
1706            <bitWidth>1</bitWidth>
1707          </field>
1708          <field>
1709            <name>SYSRAM5ECCNDED</name>
1710            <description>ECC System RAM5 Not Double Error Detect. Write 1 to clear.</description>
1711            <bitOffset>5</bitOffset>
1712            <bitWidth>1</bitWidth>
1713          </field>
1714          <field>
1715            <name>IC0ECCNDED</name>
1716            <description>ECC Icache0 Not Double Error Detect. Write 1 to clear.</description>
1717            <bitOffset>8</bitOffset>
1718            <bitWidth>1</bitWidth>
1719          </field>
1720          <field>
1721            <name>IC1ECCNDED</name>
1722            <description>ECC Icache1 Not Double Error Detect. Write 1 to clear.</description>
1723            <bitOffset>9</bitOffset>
1724            <bitWidth>1</bitWidth>
1725          </field>
1726          <field>
1727            <name>ICXIPECCNDED</name>
1728            <description>ECC IcacheXIP Not Double Error Detect. Write 1 to clear.</description>
1729            <bitOffset>10</bitOffset>
1730            <bitWidth>1</bitWidth>
1731          </field>
1732          <field>
1733            <name>FL0ECCNDED</name>
1734            <description>ECC Flash0 Not Double Error Detect. Write 1 to clear.</description>
1735            <bitOffset>11</bitOffset>
1736            <bitWidth>1</bitWidth>
1737          </field>
1738          <field>
1739            <name>FL1ECCNDED</name>
1740            <description>ECC Flash1 Not Double Error Detect. Write 1 to clear.</description>
1741            <bitOffset>12</bitOffset>
1742            <bitWidth>1</bitWidth>
1743          </field>
1744        </fields>
1745      </register>
1746      <register>
1747        <name>ECC_IRQEN</name>
1748        <description>ECC IRQ Enable Register</description>
1749        <addressOffset>0x6C</addressOffset>
1750        <fields>
1751          <field>
1752            <name>SYSRAM0ECCEN</name>
1753            <description>System RAM0 ECC Error Interrupt Enable</description>
1754            <bitOffset>0</bitOffset>
1755            <bitWidth>1</bitWidth>
1756          </field>
1757          <field>
1758            <name>SYSRAM1ECCEN</name>
1759            <description>System RAM1 ECC Error Interrupt Enable</description>
1760            <bitOffset>1</bitOffset>
1761            <bitWidth>1</bitWidth>
1762          </field>
1763          <field>
1764            <name>SYSRAM2ECCEN</name>
1765            <description>System RAM2 ECC Error Interrupt Enable</description>
1766            <bitOffset>2</bitOffset>
1767            <bitWidth>1</bitWidth>
1768          </field>
1769          <field>
1770            <name>SYSRAM3ECCEN</name>
1771            <description>System RAM3 ECC Error Interrupt Enable</description>
1772            <bitOffset>3</bitOffset>
1773            <bitWidth>1</bitWidth>
1774          </field>
1775          <field>
1776            <name>SYSRAM4ECCEN</name>
1777            <description>System RAM4 ECC Error Interrupt Enable</description>
1778            <bitOffset>4</bitOffset>
1779            <bitWidth>1</bitWidth>
1780          </field>
1781          <field>
1782            <name>SYSRAM5ECCEN</name>
1783            <description>System RAM5 ECC Error Interrupt Enable</description>
1784            <bitOffset>5</bitOffset>
1785            <bitWidth>1</bitWidth>
1786          </field>
1787          <field>
1788            <name>IC0ECCEN</name>
1789            <description>Icache0 ECC Error Interrupt Enable</description>
1790            <bitOffset>8</bitOffset>
1791            <bitWidth>1</bitWidth>
1792          </field>
1793          <field>
1794            <name>IC1ECCEN</name>
1795            <description>Icache1 ECC Error Interrupt Enable</description>
1796            <bitOffset>9</bitOffset>
1797            <bitWidth>1</bitWidth>
1798          </field>
1799          <field>
1800            <name>ICXIPECCEN</name>
1801            <description>IcacheXIP ECC Error Interrupt Enable</description>
1802            <bitOffset>10</bitOffset>
1803            <bitWidth>1</bitWidth>
1804          </field>
1805          <field>
1806            <name>FL0ECCEN</name>
1807            <description>Flash0 NError ECC Interrupt Enable</description>
1808            <bitOffset>11</bitOffset>
1809            <bitWidth>1</bitWidth>
1810          </field>
1811          <field>
1812            <name>FL1ECCEN</name>
1813            <description>Flash1 ECC Error Interrupt Enable</description>
1814            <bitOffset>12</bitOffset>
1815            <bitWidth>1</bitWidth>
1816          </field>
1817        </fields>
1818      </register>
1819      <register>
1820        <name>ECC_ERRAD</name>
1821        <description>ECC Error Address Register</description>
1822        <addressOffset>0x70</addressOffset>
1823        <fields>
1824          <field>
1825            <name>DATARAMADDR</name>
1826            <description>ECC Error Address.Data Ram Address.</description>
1827            <bitOffset>0</bitOffset>
1828            <bitWidth>13</bitWidth>
1829          </field>
1830          <field>
1831            <name>DATARAMBANK</name>
1832            <description>ECC Error Address.Data Error Bank.</description>
1833            <bitOffset>14</bitOffset>
1834            <bitWidth>1</bitWidth>
1835          </field>
1836          <field>
1837            <name>DATARAMERR</name>
1838            <description>ECC Error Address.Data Ram Error.</description>
1839            <bitOffset>15</bitOffset>
1840            <bitWidth>1</bitWidth>
1841          </field>
1842          <field>
1843            <name>TAGRAMADDR</name>
1844            <description>ECC Error Address.Tag Ram Address.</description>
1845            <bitOffset>16</bitOffset>
1846            <bitWidth>13</bitWidth>
1847          </field>
1848          <field>
1849            <name>TAGRAMBANK</name>
1850            <description>ECC Error Address.Tag Ram Bank.</description>
1851            <bitOffset>30</bitOffset>
1852            <bitWidth>1</bitWidth>
1853          </field>
1854          <field>
1855            <name>TAGRAMERR</name>
1856            <description>ECC Error Address.Tag Ram Error.</description>
1857            <bitOffset>31</bitOffset>
1858            <bitWidth>1</bitWidth>
1859          </field>
1860        </fields>
1861      </register>
1862      <register>
1863        <name>BTLE_LDOCR</name>
1864        <description>BTLE LDO Control Register</description>
1865        <addressOffset>0x74</addressOffset>
1866        <fields>
1867          <field>
1868            <name>LDOTXEN</name>
1869            <description>LDOTX Enable</description>
1870            <bitOffset>0</bitOffset>
1871            <bitWidth>1</bitWidth>
1872            <enumeratedValues>
1873              <enumeratedValue>
1874                <name>dis</name>
1875                <description>disabled.</description>
1876                <value>0</value>
1877              </enumeratedValue>
1878              <enumeratedValue>
1879                <name>en</name>
1880                <description>enabled.</description>
1881                <value>1</value>
1882              </enumeratedValue>
1883            </enumeratedValues>
1884          </field>
1885          <field>
1886            <name>LDOTXOPULLD</name>
1887            <description>LDOTX PULL Disable</description>
1888            <bitOffset>1</bitOffset>
1889            <bitWidth>1</bitWidth>
1890            <enumeratedValues>
1891              <enumeratedValue>
1892                <name>en</name>
1893                <description>enabled.</description>
1894                <value>0</value>
1895              </enumeratedValue>
1896              <enumeratedValue>
1897                <name>dis</name>
1898                <description>disabled.</description>
1899                <value>1</value>
1900              </enumeratedValue>
1901            </enumeratedValues>
1902          </field>
1903          <field>
1904            <name>LDOTXVSEL</name>
1905            <description>LDOTX Voltage Setting</description>
1906            <bitOffset>2</bitOffset>
1907            <bitWidth>2</bitWidth>
1908            <enumeratedValues>
1909              <enumeratedValue>
1910                <name>0_7</name>
1911                <description>0.7V</description>
1912                <value>0</value>
1913              </enumeratedValue>
1914              <enumeratedValue>
1915                <name>0_85</name>
1916                <description>0.85V</description>
1917                <value>1</value>
1918              </enumeratedValue>
1919              <enumeratedValue>
1920                <name>0_9</name>
1921                <description>0.9V</description>
1922                <value>2</value>
1923              </enumeratedValue>
1924              <enumeratedValue>
1925                <name>1_1</name>
1926                <description>1.1V</description>
1927                <value>3</value>
1928              </enumeratedValue>
1929            </enumeratedValues>
1930          </field>
1931          <field>
1932            <name>LDORXEN</name>
1933            <description>LDORX Enable</description>
1934            <bitOffset>4</bitOffset>
1935            <bitWidth>1</bitWidth>
1936            <enumeratedValues>
1937              <enumeratedValue>
1938                <name>dis</name>
1939                <description>disabled.</description>
1940                <value>0</value>
1941              </enumeratedValue>
1942              <enumeratedValue>
1943                <name>en</name>
1944                <description>enabled.</description>
1945                <value>1</value>
1946              </enumeratedValue>
1947            </enumeratedValues>
1948          </field>
1949          <field>
1950            <name>LDORXPULLD</name>
1951            <description>LDORX Pulldown</description>
1952            <bitOffset>5</bitOffset>
1953            <bitWidth>1</bitWidth>
1954            <enumeratedValues>
1955              <enumeratedValue>
1956                <name>en</name>
1957                <description>enabled.</description>
1958                <value>0</value>
1959              </enumeratedValue>
1960              <enumeratedValue>
1961                <name>dis</name>
1962                <description>disabled.</description>
1963                <value>1</value>
1964              </enumeratedValue>
1965            </enumeratedValues>
1966          </field>
1967          <field>
1968            <name>LDORXVSEL</name>
1969            <description>LDORX Output Voltage Setting</description>
1970            <bitOffset>6</bitOffset>
1971            <bitWidth>2</bitWidth>
1972            <enumeratedValues>
1973              <enumeratedValue>
1974                <name>0_7</name>
1975                <description>0.7V</description>
1976                <value>0</value>
1977              </enumeratedValue>
1978              <enumeratedValue>
1979                <name>0_85</name>
1980                <description>0.85V</description>
1981                <value>1</value>
1982              </enumeratedValue>
1983              <enumeratedValue>
1984                <name>0_9</name>
1985                <description>0.9V</description>
1986                <value>2</value>
1987              </enumeratedValue>
1988              <enumeratedValue>
1989                <name>1_1</name>
1990                <description>1.1V</description>
1991                <value>3</value>
1992              </enumeratedValue>
1993            </enumeratedValues>
1994          </field>
1995          <field>
1996            <name>LDORXBYP</name>
1997            <description>LDORX Bypass Enable</description>
1998            <bitOffset>8</bitOffset>
1999            <bitWidth>1</bitWidth>
2000            <enumeratedValues>
2001              <enumeratedValue>
2002                <name>dis</name>
2003                <description>disabled.</description>
2004                <value>0</value>
2005              </enumeratedValue>
2006              <enumeratedValue>
2007                <name>en</name>
2008                <description>enabled.</description>
2009                <value>1</value>
2010              </enumeratedValue>
2011            </enumeratedValues>
2012          </field>
2013          <field>
2014            <name>LDORXDISCH</name>
2015            <description>LDORX Discharge</description>
2016            <bitOffset>9</bitOffset>
2017            <bitWidth>1</bitWidth>
2018            <enumeratedValues>
2019              <enumeratedValue>
2020                <name>dis</name>
2021                <description>disabled.</description>
2022                <value>0</value>
2023              </enumeratedValue>
2024              <enumeratedValue>
2025                <name>en</name>
2026                <description>enabled.</description>
2027                <value>1</value>
2028              </enumeratedValue>
2029            </enumeratedValues>
2030          </field>
2031          <field>
2032            <name>LDOTXBYP</name>
2033            <description>LDOTX Bypass Enable</description>
2034            <bitOffset>10</bitOffset>
2035            <bitWidth>1</bitWidth>
2036            <enumeratedValues>
2037              <enumeratedValue>
2038                <name>dis</name>
2039                <description>disabled.</description>
2040                <value>0</value>
2041              </enumeratedValue>
2042              <enumeratedValue>
2043                <name>en</name>
2044                <description>enabled.</description>
2045                <value>1</value>
2046              </enumeratedValue>
2047            </enumeratedValues>
2048          </field>
2049          <field>
2050            <name>LDOTXDISCH</name>
2051            <description>LDOTX Discharge</description>
2052            <bitOffset>11</bitOffset>
2053            <bitWidth>1</bitWidth>
2054            <enumeratedValues>
2055              <enumeratedValue>
2056                <name>dis</name>
2057                <description>disabled.</description>
2058                <value>0</value>
2059              </enumeratedValue>
2060              <enumeratedValue>
2061                <name>en</name>
2062                <description>enabled.</description>
2063                <value>1</value>
2064              </enumeratedValue>
2065            </enumeratedValues>
2066          </field>
2067          <field>
2068            <name>LDOTXENDLY</name>
2069            <description>LDOTX Enable Delay</description>
2070            <bitOffset>12</bitOffset>
2071            <bitWidth>1</bitWidth>
2072            <enumeratedValues>
2073              <enumeratedValue>
2074                <name>dis</name>
2075                <description>disabled.</description>
2076                <value>0</value>
2077              </enumeratedValue>
2078              <enumeratedValue>
2079                <name>en</name>
2080                <description>enabled.</description>
2081                <value>1</value>
2082              </enumeratedValue>
2083            </enumeratedValues>
2084          </field>
2085          <field>
2086            <name>LDORXENDLY</name>
2087            <description>LDORX Enable Delay</description>
2088            <bitOffset>13</bitOffset>
2089            <bitWidth>1</bitWidth>
2090            <enumeratedValues>
2091              <enumeratedValue>
2092                <name>dis</name>
2093                <description>disabled.</description>
2094                <value>0</value>
2095              </enumeratedValue>
2096              <enumeratedValue>
2097                <name>en</name>
2098                <description>enabled.</description>
2099                <value>1</value>
2100              </enumeratedValue>
2101            </enumeratedValues>
2102          </field>
2103          <field>
2104            <name>LDORXBYPENENDLY</name>
2105            <description>LDOTX Bypass Enable Delay</description>
2106            <bitOffset>14</bitOffset>
2107            <bitWidth>1</bitWidth>
2108          </field>
2109          <field>
2110            <name>LDOTXBYPENENDLY</name>
2111            <description>LDORX Bypass Enable Delay</description>
2112            <bitOffset>15</bitOffset>
2113            <bitWidth>1</bitWidth>
2114          </field>
2115        </fields>
2116      </register>
2117      <register>
2118        <name>BTLE_LDODCR</name>
2119        <description>BTLE LDO Delay Register</description>
2120        <addressOffset>0x78</addressOffset>
2121        <fields>
2122          <field>
2123            <name>BYPDLYCNT</name>
2124            <description>Bypass Delay Count. Count delay base on PCLK.</description>
2125            <bitOffset>0</bitOffset>
2126            <bitWidth>8</bitWidth>
2127          </field>
2128          <field>
2129            <name>LDORXDLYCNT</name>
2130            <description>LDORX Delay Count. Count delay base on PCLK/128.</description>
2131            <bitOffset>8</bitOffset>
2132            <bitWidth>9</bitWidth>
2133          </field>
2134          <field>
2135            <name>LDOTXDLYCNT</name>
2136            <description>LDOTX Delay Count. Count delay base on PCLK/128.</description>
2137            <bitOffset>20</bitOffset>
2138            <bitWidth>9</bitWidth>
2139          </field>
2140        </fields>
2141      </register>
2142      <register>
2143        <name>GP0</name>
2144        <description>General Purpose Register 0</description>
2145        <addressOffset>0x80</addressOffset>
2146        <fields>
2147          <field>
2148            <name>GPR0</name>
2149            <description>User-defined register RAM.</description>
2150            <bitOffset>0</bitOffset>
2151            <bitWidth>32</bitWidth>
2152          </field>
2153        </fields>
2154      </register>
2155      <register>
2156        <name>APB_ASYNC</name>
2157        <description>APB Asynchronous Bridge Select Register</description>
2158        <addressOffset>0x84</addressOffset>
2159        <fields>
2160          <field>
2161            <name>APBASYNCI2C0</name>
2162            <description>Feeds I2C0 with either PCLK or 7.37MHz Clk</description>
2163            <bitOffset>0</bitOffset>
2164            <bitWidth>1</bitWidth>
2165            <enumeratedValues>
2166              <enumeratedValue>
2167                <name>pclk</name>
2168                <description>PCLK Source</description>
2169                <value>0</value>
2170              </enumeratedValue>
2171              <enumeratedValue>
2172                <name>7mclk</name>
2173                <description>7.37MHz Source</description>
2174                <value>1</value>
2175              </enumeratedValue>
2176            </enumeratedValues>
2177          </field>
2178          <field derivedFrom="APBASYNCI2C0">
2179            <name>APBASYNCI2C1</name>
2180            <description>Feeds I2C1 with either PCLK or 7.37MHz Clk</description>
2181            <bitOffset>1</bitOffset>
2182            <bitWidth>1</bitWidth>
2183          </field>
2184          <field derivedFrom="APBASYNCI2C0">
2185            <name>APBASYNCI2C2</name>
2186            <description>Feeds I2C2 with either PCLK or 7.37MHz Clk</description>
2187            <bitOffset>2</bitOffset>
2188            <bitWidth>1</bitWidth>
2189          </field>
2190          <field derivedFrom="APBASYNCI2C0">
2191            <name>APBASYNCPT</name>
2192            <description>Feeds PT with either PCLK or 7.37MHz Clk</description>
2193            <bitOffset>3</bitOffset>
2194            <bitWidth>1</bitWidth>
2195          </field>
2196        </fields>
2197      </register>
2198    </registers>
2199  </peripheral>
2200</device>