1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SYSCTRL</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>SBUSARB</name> 21 <description>System bus arbitration scheme. These bits are used to select between Fixed burst arbitration and Round Robin scheme. The Round Robin scheme is selected by default.</description> 22 <bitOffset>1</bitOffset> 23 <bitWidth>2</bitWidth> 24 </field> 25 <field> 26 <name>FPUS_DIS</name> 27 <description>Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4.</description> 28 <bitOffset>5</bitOffset> 29 <bitWidth>1</bitWidth> 30 </field> 31 <field> 32 <name>ICC0_FLUSH</name> 33 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 34 <bitOffset>6</bitOffset> 35 <bitWidth>1</bitWidth> 36 <enumeratedValues> 37 <enumeratedValue> 38 <name>normal</name> 39 <description>Normal Code Cache Operation</description> 40 <value>0</value> 41 </enumeratedValue> 42 <enumeratedValue> 43 <name>flush</name> 44 <description>Code Caches and CPU instruction buffer are flushed </description> 45 <value>1</value> 46 </enumeratedValue> 47 </enumeratedValues> 48 </field> 49 <field> 50 <name>CCHK</name> 51 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 52 <bitOffset>13</bitOffset> 53 <bitWidth>1</bitWidth> 54 <enumeratedValues> 55 <enumeratedValue> 56 <name>complete</name> 57 <description>No operation/complete.</description> 58 <value>0</value> 59 </enumeratedValue> 60 <enumeratedValue> 61 <name>start</name> 62 <description>Start operation.</description> 63 <value>1</value> 64 </enumeratedValue> 65 </enumeratedValues> 66 </field> 67 <field> 68 <name>SWD_DIS</name> 69 <description> Serial Wire Debug Disable.</description> 70 <bitOffset>14</bitOffset> 71 <bitWidth>1</bitWidth> 72 </field> 73 <field> 74 <name>CHKRES</name> 75 <description>ROM Checksum Result. This bit is valid when the checksum is done and the CCHK bit is cleared.</description> 76 <bitOffset>15</bitOffset> 77 <bitWidth>1</bitWidth> 78 <enumeratedValues> 79 <enumeratedValue> 80 <name>pass</name> 81 <description>ROM Checksum Correct.</description> 82 <value>0</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>fail</name> 86 <description>ROM Checksum Fail.</description> 87 <value>1</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 </fields> 92 </register> 93 <register> 94 <name>RST0</name> 95 <description>Reset.</description> 96 <addressOffset>0x04</addressOffset> 97 <fields> 98 <field> 99 <name>DMA</name> 100 <description>DMA Reset.</description> 101 <bitOffset>0</bitOffset> 102 <bitWidth>1</bitWidth> 103 <enumeratedValues> 104 <name>reset</name> 105 <usage>read-write</usage> 106 <enumeratedValue> 107 <name>reset_done</name> 108 <description>Reset complete.</description> 109 <value>0</value> 110 </enumeratedValue> 111 <enumeratedValue> 112 <name>busy</name> 113 <description>Starts Reset or indicates reset in progress.</description> 114 <value>1</value> 115 </enumeratedValue> 116 </enumeratedValues> 117 </field> 118 <field derivedFrom="DMA"> 119 <name>WDT</name> 120 <description>Watchdog Timer 0 Reset.</description> 121 <bitOffset>1</bitOffset> 122 <bitWidth>1</bitWidth> 123 </field> 124 <field derivedFrom="DMA"> 125 <name>GPIO0</name> 126 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 127 <bitOffset>2</bitOffset> 128 <bitWidth>1</bitWidth> 129 </field> 130 <field derivedFrom="DMA"> 131 <name>TMR0</name> 132 <description>Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 133 <bitOffset>5</bitOffset> 134 <bitWidth>1</bitWidth> 135 </field> 136 <field derivedFrom="DMA"> 137 <name>TMR1</name> 138 <description>Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 139 <bitOffset>6</bitOffset> 140 <bitWidth>1</bitWidth> 141 </field> 142 <field derivedFrom="DMA"> 143 <name>TMR2</name> 144 <description>Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 145 <bitOffset>7</bitOffset> 146 <bitWidth>1</bitWidth> 147 </field> 148 <field derivedFrom="DMA"> 149 <name>UART0</name> 150 <description>UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 151 <bitOffset>11</bitOffset> 152 <bitWidth>1</bitWidth> 153 </field> 154 <field derivedFrom="DMA"> 155 <name>UART1</name> 156 <description>UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 157 <bitOffset>12</bitOffset> 158 <bitWidth>1</bitWidth> 159 </field> 160 <field derivedFrom="DMA"> 161 <name>SPI0</name> 162 <description>SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 163 <bitOffset>13</bitOffset> 164 <bitWidth>1</bitWidth> 165 </field> 166 <field derivedFrom="DMA"> 167 <name>SPI1</name> 168 <description>SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 169 <bitOffset>14</bitOffset> 170 <bitWidth>1</bitWidth> 171 </field> 172 <field derivedFrom="DMA"> 173 <name>I2C0</name> 174 <description>I2C 0 Reset.</description> 175 <bitOffset>16</bitOffset> 176 <bitWidth>1</bitWidth> 177 </field> 178 <field derivedFrom="DMA"> 179 <name>CAN</name> 180 <description>CAN Reset.</description> 181 <bitOffset>19</bitOffset> 182 <bitWidth>1</bitWidth> 183 </field> 184 <field derivedFrom="DMA"> 185 <name>TRNG</name> 186 <description>TRNG Reset. This reset is only available during the manufacture testing phase.</description> 187 <bitOffset>24</bitOffset> 188 <bitWidth>1</bitWidth> 189 </field> 190 <field derivedFrom="DMA"> 191 <name>ADC</name> 192 <description>ADC Reset.</description> 193 <bitOffset>26</bitOffset> 194 <bitWidth>1</bitWidth> 195 </field> 196 <field derivedFrom="DMA"> 197 <name>SOFT</name> 198 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 199 <bitOffset>29</bitOffset> 200 <bitWidth>1</bitWidth> 201 </field> 202 <field derivedFrom="DMA"> 203 <name>PERIPH</name> 204 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 205 <bitOffset>30</bitOffset> 206 <bitWidth>1</bitWidth> 207 </field> 208 <field derivedFrom="DMA"> 209 <name>SYS</name> 210 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 211 <bitOffset>31</bitOffset> 212 <bitWidth>1</bitWidth> 213 </field> 214 </fields> 215 </register> 216 <register> 217 <name>CLKCTRL</name> 218 <description>Clock Control.</description> 219 <addressOffset>0x08</addressOffset> 220 <resetValue>0x00000008</resetValue> 221 <fields> 222 <field> 223 <name>SYSCLK_DIV</name> 224 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 225 <bitOffset>6</bitOffset> 226 <bitWidth>3</bitWidth> 227 <enumeratedValues> 228 <enumeratedValue> 229 <name>div1</name> 230 <description>Divide by 1.</description> 231 <value>0</value> 232 </enumeratedValue> 233 <enumeratedValue> 234 <name>div2</name> 235 <description>Divide by 2.</description> 236 <value>1</value> 237 </enumeratedValue> 238 <enumeratedValue> 239 <name>div4</name> 240 <description>Divide by 4.</description> 241 <value>2</value> 242 </enumeratedValue> 243 <enumeratedValue> 244 <name>div8</name> 245 <description>Divide by 8.</description> 246 <value>3</value> 247 </enumeratedValue> 248 <enumeratedValue> 249 <name>div16</name> 250 <description>Divide by 16.</description> 251 <value>4</value> 252 </enumeratedValue> 253 <enumeratedValue> 254 <name>div32</name> 255 <description>Divide by 32.</description> 256 <value>5</value> 257 </enumeratedValue> 258 <enumeratedValue> 259 <name>div64</name> 260 <description>Divide by 64.</description> 261 <value>6</value> 262 </enumeratedValue> 263 <enumeratedValue> 264 <name>div128</name> 265 <description>Divide by 128.</description> 266 <value>7</value> 267 </enumeratedValue> 268 </enumeratedValues> 269 </field> 270 <field> 271 <name>SYSCLK_SEL</name> 272 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 273 <bitOffset>9</bitOffset> 274 <bitWidth>3</bitWidth> 275 <enumeratedValues> 276 <enumeratedValue> 277 <name>ERFO</name> 278 <description>The external 32 MHz input is used for the system clock.</description> 279 <value>2</value> 280 </enumeratedValue> 281 <enumeratedValue> 282 <name>INRO</name> 283 <description>8 kHz LIRC is used for the system clock.</description> 284 <value>3</value> 285 </enumeratedValue> 286 <enumeratedValue> 287 <name>IPO</name> 288 <description>The internal 100 MHz oscillator is used for the system clock.</description> 289 <value>4</value> 290 </enumeratedValue> 291 <enumeratedValue> 292 <name>IBRO</name> 293 <description>The internal 7.3725 MHz oscillator is used for the system clock.</description> 294 <value>5</value> 295 </enumeratedValue> 296 <enumeratedValue> 297 <name>ERTCO</name> 298 <description>External 32 kHz input is used for the system clock.</description> 299 <value>6</value> 300 </enumeratedValue> 301 <enumeratedValue> 302 <name>EXTCLK</name> 303 <description>External clock input is used for the system clock.</description> 304 <value>7</value> 305 </enumeratedValue> 306 </enumeratedValues> 307 </field> 308 <field> 309 <name>SYSCLK_RDY</name> 310 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 311 <bitOffset>13</bitOffset> 312 <bitWidth>1</bitWidth> 313 <access>read-only</access> 314 <enumeratedValues> 315 <enumeratedValue> 316 <name>busy</name> 317 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 318 <value>0</value> 319 </enumeratedValue> 320 <enumeratedValue> 321 <name>ready</name> 322 <description>System clock running from CLKSEL clock source.</description> 323 <value>1</value> 324 </enumeratedValue> 325 </enumeratedValues> 326 </field> 327 <field> 328 <name>IPO_DIV</name> 329 <description>HIRC96M Source Clock Divider.</description> 330 <bitOffset>14</bitOffset> 331 <bitWidth>2</bitWidth> 332 <enumeratedValues> 333 <enumeratedValue> 334 <name>DIV1</name> 335 <description>Div 1</description> 336 <value>0</value> 337 </enumeratedValue> 338 <enumeratedValue> 339 <name>DIV2</name> 340 <description>Div 2</description> 341 <value>1</value> 342 </enumeratedValue> 343 <enumeratedValue> 344 <name>DIV4</name> 345 <description>Div 4</description> 346 <value>2</value> 347 </enumeratedValue> 348 <enumeratedValue> 349 <name>DIV8</name> 350 <description>Div 8</description> 351 <value>3</value> 352 </enumeratedValue> 353 </enumeratedValues> 354 </field> 355 <field> 356 <name>ERFO_EN</name> 357 <description>32 MHz Crystal Oscillator Enable.</description> 358 <bitOffset>16</bitOffset> 359 <bitWidth>1</bitWidth> 360 <enumeratedValues> 361 <enumeratedValue> 362 <name>dis</name> 363 <description>Is Disabled.</description> 364 <value>0</value> 365 </enumeratedValue> 366 <enumeratedValue> 367 <name>en</name> 368 <description>Is Enabled.</description> 369 <value>1</value> 370 </enumeratedValue> 371 </enumeratedValues> 372 </field> 373 <field derivedFrom="ERFO_EN"> 374 <name>IPO_EN</name> 375 <description>100 MHz Clock Enable.</description> 376 <bitOffset>19</bitOffset> 377 <bitWidth>1</bitWidth> 378 </field> 379 <field derivedFrom="ERFO_EN"> 380 <name>IBRO_EN</name> 381 <description>7.3725 MHz Clock Enable.</description> 382 <bitOffset>20</bitOffset> 383 <bitWidth>1</bitWidth> 384 </field> 385 <field> 386 <name>IBRO_VS</name> 387 <description>7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.</description> 388 <bitOffset>21</bitOffset> 389 <bitWidth>1</bitWidth> 390 <enumeratedValues> 391 <enumeratedValue> 392 <name>Vcor</name> 393 <description>VCore Supply</description> 394 <value>0</value> 395 </enumeratedValue> 396 <enumeratedValue> 397 <name>1V</name> 398 <description>Dedicated 1V regulated supply.</description> 399 <value>1</value> 400 </enumeratedValue> 401 </enumeratedValues> 402 </field> 403 <field> 404 <name>ERFO_RDY</name> 405 <description>32 MHz Oscillator Ready</description> 406 <bitOffset>24</bitOffset> 407 <bitWidth>1</bitWidth> 408 <access>read-only</access> 409 <enumeratedValues> 410 <enumeratedValue> 411 <name>not</name> 412 <description>Is not Ready.</description> 413 <value>0</value> 414 </enumeratedValue> 415 <enumeratedValue> 416 <name>ready</name> 417 <description>Is Ready.</description> 418 <value>1</value> 419 </enumeratedValue> 420 </enumeratedValues> 421 </field> 422 <field derivedFrom="ERFO_RDY"> 423 <name>ERTCO_RDY</name> 424 <description>32 kHz Crystal Oscillator Ready</description> 425 <bitOffset>25</bitOffset> 426 <bitWidth>1</bitWidth> 427 </field> 428 <field derivedFrom="ERFO_RDY"> 429 <name>IPO_RDY</name> 430 <description>100 MHz Clock Ready.</description> 431 <bitOffset>27</bitOffset> 432 <bitWidth>1</bitWidth> 433 </field> 434 <field derivedFrom="ERFO_RDY"> 435 <name>IBRO_RDY</name> 436 <description>7.3725 MHz HIRC Ready.</description> 437 <bitOffset>28</bitOffset> 438 <bitWidth>1</bitWidth> 439 </field> 440 <field derivedFrom="ERFO_RDY"> 441 <name>INRO_RDY</name> 442 <description>8 kHz Low Frequency Reference Clock Ready.</description> 443 <bitOffset>29</bitOffset> 444 <bitWidth>1</bitWidth> 445 </field> 446 <field derivedFrom="ERFO_RDY"> 447 <name>EXTCLK_RDY</name> 448 <description>External Clock GPIO0_28 AF2 Ready. Clock is ready when AF2 is enabled for GPIO0_28 449</description> 450 <bitOffset>31</bitOffset> 451 <bitWidth>1</bitWidth> 452 </field> 453 </fields> 454 </register> 455 <register> 456 <name>PM</name> 457 <description>Power Management.</description> 458 <addressOffset>0x0C</addressOffset> 459 <fields> 460 <field> 461 <name>MODE</name> 462 <description>Operating Mode. This three bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 463 <bitOffset>0</bitOffset> 464 <bitWidth>3</bitWidth> 465 <enumeratedValues> 466 <enumeratedValue> 467 <name>active</name> 468 <description>Active Mode.</description> 469 <value>0</value> 470 </enumeratedValue> 471 <enumeratedValue> 472 <name>backup</name> 473 <description>Backup Mode.</description> 474 <value>4</value> 475 </enumeratedValue> 476 <enumeratedValue> 477 <name>shutdown</name> 478 <description>Shutdown Mode</description> 479 <value>7</value> 480 </enumeratedValue> 481 </enumeratedValues> 482 </field> 483 <field> 484 <name>GPIO_WE</name> 485 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 486 <bitOffset>4</bitOffset> 487 <bitWidth>1</bitWidth> 488 <enumeratedValues> 489 <enumeratedValue> 490 <name>dis</name> 491 <description>Wake Up Disable.</description> 492 <value>0</value> 493 </enumeratedValue> 494 <enumeratedValue> 495 <name>en</name> 496 <description>Wake Up Enable.</description> 497 <value>1</value> 498 </enumeratedValue> 499 </enumeratedValues> 500 </field> 501 <field derivedFrom="GPIO_WE"> 502 <name>RTC_WE</name> 503 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 504 <bitOffset>5</bitOffset> 505 <bitWidth>1</bitWidth> 506 </field> 507 <field derivedFrom="GPIO_WE"> 508 <name>TMR3_WE</name> 509 <description>TMR3 (LPTMR0) Wake Up Enable. This bit enables TMR3 IRQ as wakeup source</description> 510 <bitOffset>6</bitOffset> 511 <bitWidth>1</bitWidth> 512 </field> 513 <field derivedFrom="GPIO_WE"> 514 <name>AINCOMP_WE</name> 515 <description>AINCOMP Wake Up Enable. This bit enables the AINCOMP Timer as wakeup source. </description> 516 <bitOffset>7</bitOffset> 517 <bitWidth>1</bitWidth> 518 </field> 519 <field> 520 <name>ERFO_BP</name> 521 <description>ERFO Bypass</description> 522 <bitOffset>20</bitOffset> 523 <bitWidth>1</bitWidth> 524 </field> 525 </fields> 526 </register> 527 <register> 528 <name>PCLKDIV</name> 529 <description>Peripheral Clock Divider.</description> 530 <addressOffset>0x18</addressOffset> 531 <resetValue>0x00000001</resetValue> 532 <fields> 533 <field> 534 <name>AON_CLKDIV</name> 535 <description>Always-ON (AON) domain Clock Divider. These bits define the AON 536domain clock divider.</description> 537 <bitOffset>0</bitOffset> 538 <bitWidth>2</bitWidth> 539 <enumeratedValues> 540 <enumeratedValue> 541 <name>DIV4</name> 542 <description>div4</description> 543 <value>0</value> 544 </enumeratedValue> 545 <enumeratedValue> 546 <name>DIV8</name> 547 <description>div8</description> 548 <value>1</value> 549 </enumeratedValue> 550 <enumeratedValue> 551 <name>DIV16</name> 552 <description>div16</description> 553 <value>2</value> 554 </enumeratedValue> 555 <enumeratedValue> 556 <name>DIV32</name> 557 <description>div8</description> 558 <value>3</value> 559 </enumeratedValue> 560 </enumeratedValues> 561 </field> 562 </fields> 563 </register> 564 <register> 565 <name>PCLKDIS0</name> 566 <description>Peripheral Clock Disable.</description> 567 <addressOffset>0x24</addressOffset> 568 <fields> 569 <field> 570 <name>GPIO0</name> 571 <description>GPIO0 Clock Disable.</description> 572 <bitOffset>0</bitOffset> 573 <bitWidth>1</bitWidth> 574 <enumeratedValues> 575 <enumeratedValue> 576 <name>en</name> 577 <description>enable it.</description> 578 <value>0</value> 579 </enumeratedValue> 580 <enumeratedValue> 581 <name>dis</name> 582 <description>disable it.</description> 583 <value>1</value> 584 </enumeratedValue> 585 </enumeratedValues> 586 </field> 587 <field derivedFrom="GPIO0"> 588 <name>DMA</name> 589 <description>DMA Clock Disable.</description> 590 <bitOffset>5</bitOffset> 591 <bitWidth>1</bitWidth> 592 </field> 593 <field derivedFrom="GPIO0"> 594 <name>SPI0</name> 595 <description>SPI 0 Clock Disable.</description> 596 <bitOffset>6</bitOffset> 597 <bitWidth>1</bitWidth> 598 </field> 599 <field derivedFrom="GPIO0"> 600 <name>SPI1</name> 601 <description>SPI 1 Clock Disable.</description> 602 <bitOffset>7</bitOffset> 603 <bitWidth>1</bitWidth> 604 </field> 605 <field derivedFrom="GPIO0"> 606 <name>UART0</name> 607 <description>UART 0 Clock Disable.</description> 608 <bitOffset>9</bitOffset> 609 <bitWidth>1</bitWidth> 610 </field> 611 <field derivedFrom="GPIO0"> 612 <name>UART1</name> 613 <description>UART 1 Clock Disable.</description> 614 <bitOffset>10</bitOffset> 615 <bitWidth>1</bitWidth> 616 </field> 617 <field derivedFrom="GPIO0"> 618 <name>I2C0</name> 619 <description>I2C 0 Clock Disable.</description> 620 <bitOffset>13</bitOffset> 621 <bitWidth>1</bitWidth> 622 </field> 623 <field derivedFrom="GPIO0"> 624 <name>TMR0</name> 625 <description>Timer 0 Clock Disable.</description> 626 <bitOffset>15</bitOffset> 627 <bitWidth>1</bitWidth> 628 </field> 629 <field derivedFrom="GPIO0"> 630 <name>TMR1</name> 631 <description>Timer 1 Clock Disable.</description> 632 <bitOffset>16</bitOffset> 633 <bitWidth>1</bitWidth> 634 </field> 635 <field derivedFrom="GPIO0"> 636 <name>TMR2</name> 637 <description>Timer 2 Clock Disable.</description> 638 <bitOffset>17</bitOffset> 639 <bitWidth>1</bitWidth> 640 </field> 641 <field derivedFrom="GPIO0"> 642 <name>ADC</name> 643 <description>ADC Clock Disable.</description> 644 <bitOffset>23</bitOffset> 645 <bitWidth>1</bitWidth> 646 </field> 647 <field derivedFrom="GPIO0"> 648 <name>I2C1</name> 649 <description>I2C 1 Clock Disable.</description> 650 <bitOffset>28</bitOffset> 651 <bitWidth>1</bitWidth> 652 </field> 653 <field derivedFrom="GPIO0"> 654 <name>PT</name> 655 <description>Pluse Train Clock Disable.</description> 656 <bitOffset>29</bitOffset> 657 <bitWidth>1</bitWidth> 658 </field> 659 </fields> 660 </register> 661 <register> 662 <name>MEMCTRL</name> 663 <description>Memory Clock Control Register.</description> 664 <addressOffset>0x28</addressOffset> 665 <fields> 666 <field> 667 <name>FWS</name> 668 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 669 <bitOffset>0</bitOffset> 670 <bitWidth>3</bitWidth> 671 </field> 672 <field> 673 <name>RAMWS_EN</name> 674 <description>System RAM Wait State enable.</description> 675 <bitOffset>4</bitOffset> 676 <bitWidth>1</bitWidth> 677 </field> 678 <field> 679 <name>RAM0LS_EN</name> 680 <description>System RAM 0 Light Sleep mode.</description> 681 <bitOffset>8</bitOffset> 682 <bitWidth>1</bitWidth> 683 </field> 684 <field> 685 <name>RAM1LS_EN</name> 686 <description>System RAM 1 Light Sleep mode.</description> 687 <bitOffset>9</bitOffset> 688 <bitWidth>1</bitWidth> 689 </field> 690 <field> 691 <name>RAM2LS_EN</name> 692 <description>System RAM 2 Light Sleep mode.</description> 693 <bitOffset>10</bitOffset> 694 <bitWidth>1</bitWidth> 695 </field> 696 <field> 697 <name>RAM3LS_EN</name> 698 <description>System RAM 3 Light Sleep mode.</description> 699 <bitOffset>11</bitOffset> 700 <bitWidth>1</bitWidth> 701 </field> 702 <field> 703 <name>ICC0LS_EN</name> 704 <description>Internal Cache Controller RAM Light Sleep mode.</description> 705 <bitOffset>12</bitOffset> 706 <bitWidth>1</bitWidth> 707 </field> 708 <field> 709 <name>ROMLS_EN</name> 710 <description>ROM Light Sleep mode.</description> 711 <bitOffset>13</bitOffset> 712 <bitWidth>1</bitWidth> 713 </field> 714 </fields> 715 </register> 716 <register> 717 <name>MEMZ</name> 718 <description>Memory Zeroize Control.</description> 719 <addressOffset>0x2C</addressOffset> 720 <fields> 721 <field> 722 <name>RAM0</name> 723 <description>System RAM Block 0 Zeroization.</description> 724 <bitOffset>0</bitOffset> 725 <bitWidth>1</bitWidth> 726 <enumeratedValues> 727 <enumeratedValue> 728 <name>nop</name> 729 <description>No operation/complete.</description> 730 <value>0</value> 731 </enumeratedValue> 732 <enumeratedValue> 733 <name>start</name> 734 <description>Start operation.</description> 735 <value>1</value> 736 </enumeratedValue> 737 </enumeratedValues> 738 </field> 739 <field derivedFrom="RAM0"> 740 <name>RAM1</name> 741 <description>System RAM Block 1 Zeroization.</description> 742 <bitOffset>1</bitOffset> 743 <bitWidth>1</bitWidth> 744 </field> 745 <field derivedFrom="RAM0"> 746 <name>RAM2</name> 747 <description>System RAM Block 2 Zeroization.</description> 748 <bitOffset>2</bitOffset> 749 <bitWidth>1</bitWidth> 750 </field> 751 <field derivedFrom="RAM0"> 752 <name>RAMCB</name> 753 <description>System RAM Check Bit Block Zeroization.</description> 754 <bitOffset>3</bitOffset> 755 <bitWidth>1</bitWidth> 756 </field> 757 <field derivedFrom="RAM0"> 758 <name>ICC0</name> 759 <description>Internal Cache Controller Data and Tag RAM Zeroization.</description> 760 <bitOffset>4</bitOffset> 761 <bitWidth>1</bitWidth> 762 </field> 763 </fields> 764 </register> 765 <register> 766 <name>SYSST</name> 767 <description>System Status Register.</description> 768 <addressOffset>0x40</addressOffset> 769 <fields> 770 <field> 771 <name>ICELOCK</name> 772 <description>ARM ICE Lock Status.</description> 773 <bitOffset>0</bitOffset> 774 <bitWidth>1</bitWidth> 775 <enumeratedValues> 776 <enumeratedValue> 777 <name>unlocked</name> 778 <description>ICE is unlocked.</description> 779 <value>0</value> 780 </enumeratedValue> 781 <enumeratedValue> 782 <name>locked</name> 783 <description>ICE is locked.</description> 784 <value>1</value> 785 </enumeratedValue> 786 </enumeratedValues> 787 </field> 788 </fields> 789 </register> 790 <register> 791 <name>RST1</name> 792 <description>Reset 1.</description> 793 <addressOffset>0x44</addressOffset> 794 <fields> 795 <field> 796 <name>I2C1</name> 797 <description>I2C1 Reset.</description> 798 <bitOffset>0</bitOffset> 799 <bitWidth>1</bitWidth> 800 <enumeratedValues> 801 <name>reset_read</name> 802 <usage>read</usage> 803 <enumeratedValue> 804 <name>reset_done</name> 805 <description>Reset complete.</description> 806 <value>0</value> 807 </enumeratedValue> 808 <enumeratedValue> 809 <name>busy</name> 810 <description>Starts reset or indicates reset in progress.</description> 811 <value>1</value> 812 </enumeratedValue> 813 </enumeratedValues> 814 </field> 815 <field derivedFrom="I2C1"> 816 <name>PT</name> 817 <description>PT Reset.</description> 818 <bitOffset>1</bitOffset> 819 <bitWidth>1</bitWidth> 820 </field> 821 <field derivedFrom="I2C1"> 822 <name>AES</name> 823 <description>AES Reset.</description> 824 <bitOffset>10</bitOffset> 825 <bitWidth>1</bitWidth> 826 </field> 827 <field derivedFrom="I2C1"> 828 <name>AC</name> 829 <description>AC Reset.</description> 830 <bitOffset>14</bitOffset> 831 <bitWidth>1</bitWidth> 832 </field> 833 <field derivedFrom="I2C1"> 834 <name>I2S</name> 835 <description>I2S Reset.</description> 836 <bitOffset>23</bitOffset> 837 <bitWidth>1</bitWidth> 838 </field> 839 </fields> 840 </register> 841 <register> 842 <name>PCLKDIS1</name> 843 <description>Peripheral Clock Disable.</description> 844 <addressOffset>0x48</addressOffset> 845 <fields> 846 <field> 847 <name>TRNG</name> 848 <description>TRNG Clock Disable.</description> 849 <bitOffset>2</bitOffset> 850 <bitWidth>1</bitWidth> 851 </field> 852 <field derivedFrom="TRNG"> 853 <name>WDT</name> 854 <description>Watchdog Timer 0 Disable.</description> 855 <bitOffset>4</bitOffset> 856 <bitWidth>1</bitWidth> 857 </field> 858 <field derivedFrom="TRNG"> 859 <name>CAN</name> 860 <description>CAN Clock Disable.</description> 861 <bitOffset>11</bitOffset> 862 <bitWidth>1</bitWidth> 863 </field> 864 <field derivedFrom="TRNG"> 865 <name>AES</name> 866 <description>AES Clock Disable.</description> 867 <bitOffset>15</bitOffset> 868 <bitWidth>1</bitWidth> 869 </field> 870 <field derivedFrom="TRNG"> 871 <name>AES_KEY</name> 872 <description>AES Keys Clock Disable.</description> 873 <bitOffset>16</bitOffset> 874 <bitWidth>1</bitWidth> 875 </field> 876 <field derivedFrom="TRNG"> 877 <name>I2S</name> 878 <description>I2S Clock Disable.</description> 879 <bitOffset>23</bitOffset> 880 <bitWidth>1</bitWidth> 881 </field> 882 </fields> 883 </register> 884 <register> 885 <name>EVENTEN</name> 886 <description>Event Enable Register.</description> 887 <addressOffset>0x4C</addressOffset> 888 <fields> 889 <field> 890 <name>DMA</name> 891 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 892 <bitOffset>0</bitOffset> 893 <bitWidth>1</bitWidth> 894 </field> 895 <field> 896 <name>RX</name> 897 <description>Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9.</description> 898 <bitOffset>1</bitOffset> 899 <bitWidth>1</bitWidth> 900 </field> 901 <field> 902 <name>TX</name> 903 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9.</description> 904 <bitOffset>2</bitOffset> 905 <bitWidth>1</bitWidth> 906 </field> 907 </fields> 908 </register> 909 <register> 910 <name>REVISION</name> 911 <description>Revision Register.</description> 912 <addressOffset>0x50</addressOffset> 913 <access>read-only</access> 914 <fields> 915 <field> 916 <name>REVISION</name> 917 <description>Manufacturer Chip Revision.</description> 918 <bitOffset>0</bitOffset> 919 <bitWidth>16</bitWidth> 920 </field> 921 </fields> 922 </register> 923 <register> 924 <name>SYSIE</name> 925 <description>System Status Interrupt Enable Register.</description> 926 <addressOffset>0x54</addressOffset> 927 <fields> 928 <field> 929 <name>ICEUNLOCK</name> 930 <description>ARM ICE Unlock Interrupt Enable.</description> 931 <bitOffset>0</bitOffset> 932 <bitWidth>1</bitWidth> 933 <enumeratedValues> 934 <enumeratedValue> 935 <name>dis</name> 936 <description>disabled.</description> 937 <value>0</value> 938 </enumeratedValue> 939 <enumeratedValue> 940 <name>en</name> 941 <description>enabled.</description> 942 <value>1</value> 943 </enumeratedValue> 944 </enumeratedValues> 945 </field> 946 </fields> 947 </register> 948 <register> 949 <name>ECCERR</name> 950 <description>ECC Error Register</description> 951 <addressOffset>0x64</addressOffset> 952 <fields> 953 <field> 954 <name>RAM0_1</name> 955 <description>ECC System RAM0 or RAM1 Error Flag. Write 1 to clear.</description> 956 <bitOffset>0</bitOffset> 957 <bitWidth>1</bitWidth> 958 </field> 959 <field> 960 <name>RAM2</name> 961 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 962 <bitOffset>1</bitOffset> 963 <bitWidth>1</bitWidth> 964 </field> 965 <field> 966 <name>RAM3</name> 967 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 968 <bitOffset>2</bitOffset> 969 <bitWidth>1</bitWidth> 970 </field> 971 <field> 972 <name>ICC0</name> 973 <description>ECC ICACHE Error Flag. Write 1 to clear.</description> 974 <bitOffset>3</bitOffset> 975 <bitWidth>1</bitWidth> 976 </field> 977 <field> 978 <name>FLASH0</name> 979 <description>ECC Flash 0 Error Flag. Write 1 to clear.</description> 980 <bitOffset>4</bitOffset> 981 <bitWidth>1</bitWidth> 982 </field> 983 <field> 984 <name>FLASH1</name> 985 <description>ECC Flash 1 Error Flag. Write 1 to clear.</description> 986 <bitOffset>5</bitOffset> 987 <bitWidth>1</bitWidth> 988 </field> 989 </fields> 990 </register> 991 <register> 992 <name>ECCCED</name> 993 <description>ECC Not Double Error Detect Register</description> 994 <addressOffset>0x68</addressOffset> 995 <fields> 996 <field> 997 <name>RAM0_1</name> 998 <description>ECC System RAM0 or RAM1 Not Double Error Flag. Write 1 to clear.</description> 999 <bitOffset>0</bitOffset> 1000 <bitWidth>1</bitWidth> 1001 </field> 1002 <field> 1003 <name>RAM2</name> 1004 <description>ECC System RAM2 Not Double Error Flag. Write 1 to clear.</description> 1005 <bitOffset>1</bitOffset> 1006 <bitWidth>1</bitWidth> 1007 </field> 1008 <field> 1009 <name>RAM3</name> 1010 <description>ECC System RAM3 Not Double Error Flag. Write 1 to clear.</description> 1011 <bitOffset>2</bitOffset> 1012 <bitWidth>1</bitWidth> 1013 </field> 1014 <field> 1015 <name>ICC0</name> 1016 <description>ECC ICACHE Not Double Error Flag. Write 1 to clear.</description> 1017 <bitOffset>3</bitOffset> 1018 <bitWidth>1</bitWidth> 1019 </field> 1020 <field> 1021 <name>FLASH0</name> 1022 <description>ECC Flash 0 Not Double Error Flag. Write 1 to clear.</description> 1023 <bitOffset>4</bitOffset> 1024 <bitWidth>1</bitWidth> 1025 </field> 1026 <field> 1027 <name>FLASH1</name> 1028 <description>ECC Flash 1 Not Double Error Flag. Write 1 to clear.</description> 1029 <bitOffset>5</bitOffset> 1030 <bitWidth>1</bitWidth> 1031 </field> 1032 </fields> 1033 </register> 1034 <register> 1035 <name>ECCIE</name> 1036 <description>ECC IRQ Enable Register</description> 1037 <addressOffset>0x6C</addressOffset> 1038 <fields> 1039 <field> 1040 <name>RAM0_1</name> 1041 <description>System RAM0 or RAM1 ECC Interrupt Enable.</description> 1042 <bitOffset>0</bitOffset> 1043 <bitWidth>1</bitWidth> 1044 </field> 1045 <field> 1046 <name>RAM2</name> 1047 <description>System RAM2 ECC Interrupt Enable.</description> 1048 <bitOffset>1</bitOffset> 1049 <bitWidth>1</bitWidth> 1050 </field> 1051 <field> 1052 <name>RAM3</name> 1053 <description>System RAM3 ECC Interrupt Enable.</description> 1054 <bitOffset>2</bitOffset> 1055 <bitWidth>1</bitWidth> 1056 </field> 1057 <field> 1058 <name>ICC0</name> 1059 <description>ICACHE ECC Interrupt Enable.</description> 1060 <bitOffset>3</bitOffset> 1061 <bitWidth>1</bitWidth> 1062 </field> 1063 <field> 1064 <name>FLASH0</name> 1065 <description>Flash 0 ECC Interrupt Enable.</description> 1066 <bitOffset>4</bitOffset> 1067 <bitWidth>1</bitWidth> 1068 </field> 1069 <field> 1070 <name>FLASH1</name> 1071 <description>Flash 1 ECC Interrupt Enable.</description> 1072 <bitOffset>5</bitOffset> 1073 <bitWidth>1</bitWidth> 1074 </field> 1075 </fields> 1076 </register> 1077 <register> 1078 <name>ECCADDR</name> 1079 <description>ECC Error Address Register</description> 1080 <addressOffset>0x70</addressOffset> 1081 <fields> 1082 <field> 1083 <name>ERRADDR</name> 1084 <description>Error Address.</description> 1085 <bitOffset>0</bitOffset> 1086 <bitWidth>32</bitWidth> 1087 </field> 1088 </fields> 1089 </register> 1090 </registers> 1091 </peripheral> 1092</device>
