1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SCON</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>FLASH_PAGE_FLIP</name> 21 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 22 <bitOffset>4</bitOffset> 23 <bitWidth>1</bitWidth> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>normal</name> 27 <description>Physical layout matches logical layout.</description> 28 <value>0</value> 29 </enumeratedValue> 30 <enumeratedValue> 31 <name>swapped</name> 32 <description>Bottom half mapped to logical top half and vice versa.</description> 33 <value>1</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>FPU_DIS</name> 39 <description>Floating Point Unit Disable </description> 40 <bitOffset>5</bitOffset> 41 <bitWidth>1</bitWidth> 42 <enumeratedValues> 43 <enumeratedValue> 44 <name>enable</name> 45 <description>enable Floating point unit</description> 46 <value>0</value> 47 </enumeratedValue> 48 <enumeratedValue> 49 <name>disable</name> 50 <description>disable floating point unit </description> 51 <value>1</value> 52 </enumeratedValue> 53 </enumeratedValues> 54 </field> 55 <field> 56 <name>ICC0_FLUSH</name> 57 <description>Instruction Cache Controller Flush. Write 1 to flush the internal flash cache. This bit is cleared by hardware when the flush is complete.</description> 58 <bitOffset>6</bitOffset> 59 <bitWidth>1</bitWidth> 60 <enumeratedValues> 61 <enumeratedValue> 62 <name>normal</name> 63 <description>Normal Code Cache Operation</description> 64 <value>0</value> 65 </enumeratedValue> 66 <enumeratedValue> 67 <name>flush</name> 68 <description>Code Caches and CPU instruction buffer are flushed </description> 69 <value>1</value> 70 </enumeratedValue> 71 </enumeratedValues> 72 </field> 73 <field> 74 <name>SWD_DIS</name> 75 <description>Serial Wire Debug Disable </description> 76 <bitOffset>14</bitOffset> 77 <bitWidth>1</bitWidth> 78 <enumeratedValues> 79 <enumeratedValue> 80 <name>enable</name> 81 <description>Enable JTAG SWD</description> 82 <value>0</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>disable</name> 86 <description>Disable JTAG SWD </description> 87 <value>1</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 </fields> 92 </register> 93 <register> 94 <name>RST0</name> 95 <description>Reset.</description> 96 <addressOffset>0x04</addressOffset> 97 <fields> 98 <field> 99 <name>DMA</name> 100 <description>DMA Reset.</description> 101 <bitOffset>0</bitOffset> 102 <bitWidth>1</bitWidth> 103 </field> 104 <field> 105 <name>WDT0</name> 106 <description>Watchdog Timer Reset.</description> 107 <bitOffset>1</bitOffset> 108 <bitWidth>1</bitWidth> 109 </field> 110 <field> 111 <name>GPIO0</name> 112 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 113 <bitOffset>2</bitOffset> 114 <bitWidth>1</bitWidth> 115 </field> 116 <field> 117 <name>TIMER0</name> 118 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 119 <bitOffset>5</bitOffset> 120 <bitWidth>1</bitWidth> 121 </field> 122 <field> 123 <name>TIMER1</name> 124 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 125 <bitOffset>6</bitOffset> 126 <bitWidth>1</bitWidth> 127 </field> 128 <field> 129 <name>TIMER2</name> 130 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 131 <bitOffset>7</bitOffset> 132 <bitWidth>1</bitWidth> 133 </field> 134 <field> 135 <name>UART0</name> 136 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 137 <bitOffset>11</bitOffset> 138 <bitWidth>1</bitWidth> 139 </field> 140 <field> 141 <name>UART1</name> 142 <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 143 <bitOffset>12</bitOffset> 144 <bitWidth>1</bitWidth> 145 </field> 146 <field> 147 <name>SPI0</name> 148 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 149 <bitOffset>13</bitOffset> 150 <bitWidth>1</bitWidth> 151 </field> 152 <field> 153 <name>SPI1</name> 154 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 155 <bitOffset>14</bitOffset> 156 <bitWidth>1</bitWidth> 157 </field> 158 <field> 159 <name>I2C0</name> 160 <description>I2C0 Reset.</description> 161 <bitOffset>16</bitOffset> 162 <bitWidth>1</bitWidth> 163 </field> 164 <field> 165 <name>RTC</name> 166 <description>Real Time Clock Reset.</description> 167 <bitOffset>17</bitOffset> 168 <bitWidth>1</bitWidth> 169 </field> 170 <field> 171 <name>SOFT</name> 172 <description>Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.</description> 173 <bitOffset>29</bitOffset> 174 <bitWidth>1</bitWidth> 175 </field> 176 <field> 177 <name>PERIPH</name> 178 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 179 <bitOffset>30</bitOffset> 180 <bitWidth>1</bitWidth> 181 </field> 182 <field> 183 <name>SYSTEM</name> 184 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 185 <bitOffset>31</bitOffset> 186 <bitWidth>1</bitWidth> 187 </field> 188 </fields> 189 </register> 190 <register> 191 <name>CLK_CTRL</name> 192 <description>Clock Control.</description> 193 <addressOffset>0x08</addressOffset> 194 <resetValue>0x00000008</resetValue> 195 <fields> 196 <field> 197 <name>PSC</name> 198 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 199 <bitOffset>6</bitOffset> 200 <bitWidth>3</bitWidth> 201 <enumeratedValues> 202 <enumeratedValue> 203 <name>div1</name> 204 <description>Divide by 1.</description> 205 <value>0</value> 206 </enumeratedValue> 207 <enumeratedValue> 208 <name>div2</name> 209 <description>Divide by 2.</description> 210 <value>1</value> 211 </enumeratedValue> 212 <enumeratedValue> 213 <name>div4</name> 214 <description>Divide by 4.</description> 215 <value>2</value> 216 </enumeratedValue> 217 <enumeratedValue> 218 <name>div8</name> 219 <description>Divide by 8.</description> 220 <value>3</value> 221 </enumeratedValue> 222 <enumeratedValue> 223 <name>div16</name> 224 <description>Divide by 16.</description> 225 <value>4</value> 226 </enumeratedValue> 227 <enumeratedValue> 228 <name>div32</name> 229 <description>Divide by 32.</description> 230 <value>5</value> 231 </enumeratedValue> 232 <enumeratedValue> 233 <name>div64</name> 234 <description>Divide by 64.</description> 235 <value>6</value> 236 </enumeratedValue> 237 <enumeratedValue> 238 <name>div128</name> 239 <description>Divide by 128.</description> 240 <value>7</value> 241 </enumeratedValue> 242 </enumeratedValues> 243 </field> 244 <field> 245 <name>CLKSEL</name> 246 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 247 <bitOffset>9</bitOffset> 248 <bitWidth>3</bitWidth> 249 <enumeratedValues> 250 <enumeratedValue> 251 <name>HIRC</name> 252 <description>The internal 96 MHz oscillator is used for the system clock.</description> 253 <value>0</value> 254 </enumeratedValue> 255 <enumeratedValue> 256 <name>nanoRing</name> 257 <description>The nano-ring output is used for the system clock.</description> 258 <value>3</value> 259 </enumeratedValue> 260 <enumeratedValue> 261 <name>hfxIn</name> 262 <description>HFXIN is used for the system clock.</description> 263 <value>6</value> 264 </enumeratedValue> 265 </enumeratedValues> 266 </field> 267 <field> 268 <name>CLKRDY</name> 269 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 270 <bitOffset>13</bitOffset> 271 <bitWidth>1</bitWidth> 272 <access>read-only</access> 273 <enumeratedValues> 274 <enumeratedValue> 275 <name>busy</name> 276 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 277 <value>0</value> 278 </enumeratedValue> 279 <enumeratedValue> 280 <name>ready</name> 281 <description>System clock running from CLKSEL clock source.</description> 282 <value>1</value> 283 </enumeratedValue> 284 </enumeratedValues> 285 </field> 286 <field> 287 <name>X32K_EN</name> 288 <description>32kHz Crystal Oscillator Enable.</description> 289 <bitOffset>17</bitOffset> 290 <bitWidth>1</bitWidth> 291 <enumeratedValues> 292 <enumeratedValue> 293 <name>dis</name> 294 <description>Is Disabled.</description> 295 <value>0</value> 296 </enumeratedValue> 297 <enumeratedValue> 298 <name>en</name> 299 <description>Is Enabled.</description> 300 <value>1</value> 301 </enumeratedValue> 302 </enumeratedValues> 303 </field> 304 <field derivedFrom="X32K_EN"> 305 <name>HIRC_EN</name> 306 <description>60MHz High Frequency Internal Reference Clock Enable.</description> 307 <bitOffset>18</bitOffset> 308 <bitWidth>1</bitWidth> 309 </field> 310 <field> 311 <name>X32K_RDY</name> 312 <description>32kHz Crystal Oscillator Ready</description> 313 <bitOffset>25</bitOffset> 314 <bitWidth>1</bitWidth> 315 <access>read-only</access> 316 <enumeratedValues> 317 <enumeratedValue> 318 <name>not</name> 319 <description>Is not Ready.</description> 320 <value>0</value> 321 </enumeratedValue> 322 <enumeratedValue> 323 <name>ready</name> 324 <description>Is Ready.</description> 325 <value>1</value> 326 </enumeratedValue> 327 </enumeratedValues> 328 </field> 329 <field derivedFrom="X32K_RDY"> 330 <name>HIRC_RDY</name> 331 <description>60MHz HIRC Ready.</description> 332 <bitOffset>26</bitOffset> 333 <bitWidth>1</bitWidth> 334 </field> 335 <field derivedFrom="X32K_RDY"> 336 <name>LIRC8K_RDY</name> 337 <description>8kHz Low Frequency Reference Clock Ready.</description> 338 <bitOffset>29</bitOffset> 339 <bitWidth>1</bitWidth> 340 </field> 341 </fields> 342 </register> 343 <register> 344 <name>PM</name> 345 <description>Power Management.</description> 346 <addressOffset>0x0C</addressOffset> 347 <fields> 348 <field> 349 <name>MODE</name> 350 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 351 <bitOffset>0</bitOffset> 352 <bitWidth>3</bitWidth> 353 <enumeratedValues> 354 <enumeratedValue> 355 <name>active</name> 356 <description>Active Mode.</description> 357 <value>0</value> 358 </enumeratedValue> 359 <enumeratedValue> 360 <name>shutdown</name> 361 <description>Shutdown Mode.</description> 362 <value>3</value> 363 </enumeratedValue> 364 <enumeratedValue> 365 <name>backup</name> 366 <description>Backup Mode.</description> 367 <value>4</value> 368 </enumeratedValue> 369 </enumeratedValues> 370 </field> 371 <field> 372 <name>GPIOWK_EN</name> 373 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 374 <bitOffset>4</bitOffset> 375 <bitWidth>1</bitWidth> 376 <enumeratedValues> 377 <enumeratedValue> 378 <name>dis</name> 379 <description>Wake Up Disable.</description> 380 <value>0</value> 381 </enumeratedValue> 382 <enumeratedValue> 383 <name>en</name> 384 <description>Wake Up Enable.</description> 385 <value>1</value> 386 </enumeratedValue> 387 </enumeratedValues> 388 </field> 389 <field> 390 <name>RTCWK_EN</name> 391 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 392 <bitOffset>5</bitOffset> 393 <bitWidth>1</bitWidth> 394 <enumeratedValues> 395 <enumeratedValue> 396 <name>dis</name> 397 <description>Wake Up Disable.</description> 398 <value>0</value> 399 </enumeratedValue> 400 <enumeratedValue> 401 <name>en</name> 402 <description>Wake Up Enable.</description> 403 <value>1</value> 404 </enumeratedValue> 405 </enumeratedValues> 406 </field> 407 <field> 408 <name>HFIOPD</name> 409 <description>HFIO DEEPSLEEP Auto Off. When set, the High-Frequency Internal Oscillator is automatically powered off when in DEEPSLEEP mode. </description> 410 <bitOffset>15</bitOffset> 411 <bitWidth>1</bitWidth> 412 <enumeratedValues> 413 <enumeratedValue> 414 <name>active</name> 415 <description>Mode is Active.</description> 416 <value>0</value> 417 </enumeratedValue> 418 <enumeratedValue> 419 <name>deepsleep</name> 420 <description>Powered down in DEEPSLEEP.</description> 421 <value>1</value> 422 </enumeratedValue> 423 </enumeratedValues> 424 </field> 425 </fields> 426 </register> 427 <register> 428 <name>PCLK_DIS0</name> 429 <description>Peripheral Clock Disable.</description> 430 <addressOffset>0x24</addressOffset> 431 <fields> 432 <field> 433 <name>GPIO0D</name> 434 <description>GPIO0 Disable.</description> 435 <bitOffset>0</bitOffset> 436 <bitWidth>1</bitWidth> 437 <enumeratedValues> 438 <name>GPIODisable</name> 439 <enumeratedValue> 440 <name>en</name> 441 <description>enable it.</description> 442 <value>0</value> 443 </enumeratedValue> 444 <enumeratedValue> 445 <name>dis</name> 446 <description>disable it.</description> 447 <value>1</value> 448 </enumeratedValue> 449 </enumeratedValues> 450 </field> 451 <field> 452 <name>DMAD</name> 453 <description>DMA Disable.</description> 454 <bitOffset>5</bitOffset> 455 <bitWidth>1</bitWidth> 456 <enumeratedValues> 457 <name>GPIODisable</name> 458 <enumeratedValue> 459 <name>en</name> 460 <description>enable it.</description> 461 <value>0</value> 462 </enumeratedValue> 463 <enumeratedValue> 464 <name>dis</name> 465 <description>disable it.</description> 466 <value>1</value> 467 </enumeratedValue> 468 </enumeratedValues> 469 </field> 470 <field> 471 <name>SPI0D</name> 472 <description>SPI 0 Disable.</description> 473 <bitOffset>6</bitOffset> 474 <bitWidth>1</bitWidth> 475 <enumeratedValues> 476 <name>GPIODisable</name> 477 <enumeratedValue> 478 <name>en</name> 479 <description>enable it.</description> 480 <value>0</value> 481 </enumeratedValue> 482 <enumeratedValue> 483 <name>dis</name> 484 <description>disable it.</description> 485 <value>1</value> 486 </enumeratedValue> 487 </enumeratedValues> 488 </field> 489 <field> 490 <name>SPI1D</name> 491 <description>SPI 1 Disable.</description> 492 <bitOffset>7</bitOffset> 493 <bitWidth>1</bitWidth> 494 <enumeratedValues> 495 <name>GPIODisable</name> 496 <enumeratedValue> 497 <name>en</name> 498 <description>enable it.</description> 499 <value>0</value> 500 </enumeratedValue> 501 <enumeratedValue> 502 <name>dis</name> 503 <description>disable it.</description> 504 <value>1</value> 505 </enumeratedValue> 506 </enumeratedValues> 507 </field> 508 <field> 509 <name>UART0D</name> 510 <description>UART 0 Disable.</description> 511 <bitOffset>9</bitOffset> 512 <bitWidth>1</bitWidth> 513 <enumeratedValues> 514 <name>GPIODisable</name> 515 <enumeratedValue> 516 <name>en</name> 517 <description>enable it.</description> 518 <value>0</value> 519 </enumeratedValue> 520 <enumeratedValue> 521 <name>dis</name> 522 <description>disable it.</description> 523 <value>1</value> 524 </enumeratedValue> 525 </enumeratedValues> 526 </field> 527 <field> 528 <name>UART1D</name> 529 <description>UART 1 Disable.</description> 530 <bitOffset>10</bitOffset> 531 <bitWidth>1</bitWidth> 532 <enumeratedValues> 533 <name>GPIODisable</name> 534 <enumeratedValue> 535 <name>en</name> 536 <description>enable it.</description> 537 <value>0</value> 538 </enumeratedValue> 539 <enumeratedValue> 540 <name>dis</name> 541 <description>disable it.</description> 542 <value>1</value> 543 </enumeratedValue> 544 </enumeratedValues> 545 </field> 546 <field> 547 <name>I2C0D</name> 548 <description>I2C 0 Disable.</description> 549 <bitOffset>13</bitOffset> 550 <bitWidth>1</bitWidth> 551 <enumeratedValues> 552 <name>GPIODisable</name> 553 <enumeratedValue> 554 <name>en</name> 555 <description>enable it.</description> 556 <value>0</value> 557 </enumeratedValue> 558 <enumeratedValue> 559 <name>dis</name> 560 <description>disable it.</description> 561 <value>1</value> 562 </enumeratedValue> 563 </enumeratedValues> 564 </field> 565 <field> 566 <name>TIMER0D</name> 567 <description>Timer 0 Disable.</description> 568 <bitOffset>15</bitOffset> 569 <bitWidth>1</bitWidth> 570 <enumeratedValues> 571 <name>GPIODisable</name> 572 <enumeratedValue> 573 <name>en</name> 574 <description>enable it.</description> 575 <value>0</value> 576 </enumeratedValue> 577 <enumeratedValue> 578 <name>dis</name> 579 <description>disable it.</description> 580 <value>1</value> 581 </enumeratedValue> 582 </enumeratedValues> 583 </field> 584 <field> 585 <name>TIMER1D</name> 586 <description>Timer 1 Disable.</description> 587 <bitOffset>16</bitOffset> 588 <bitWidth>1</bitWidth> 589 <enumeratedValues> 590 <name>GPIODisable</name> 591 <enumeratedValue> 592 <name>en</name> 593 <description>enable it.</description> 594 <value>0</value> 595 </enumeratedValue> 596 <enumeratedValue> 597 <name>dis</name> 598 <description>disable it.</description> 599 <value>1</value> 600 </enumeratedValue> 601 </enumeratedValues> 602 </field> 603 <field> 604 <name>TIMER2D</name> 605 <description>Timer 2 Disable.</description> 606 <bitOffset>17</bitOffset> 607 <bitWidth>1</bitWidth> 608 <enumeratedValues> 609 <name>GPIODisable</name> 610 <enumeratedValue> 611 <name>en</name> 612 <description>enable it.</description> 613 <value>0</value> 614 </enumeratedValue> 615 <enumeratedValue> 616 <name>dis</name> 617 <description>disable it.</description> 618 <value>1</value> 619 </enumeratedValue> 620 </enumeratedValues> 621 </field> 622 <field> 623 <name>I2C1D</name> 624 <description>I2C 1 Disable.</description> 625 <bitOffset>28</bitOffset> 626 <bitWidth>1</bitWidth> 627 <enumeratedValues> 628 <name>GPIODisable</name> 629 <enumeratedValue> 630 <name>en</name> 631 <description>enable it.</description> 632 <value>0</value> 633 </enumeratedValue> 634 <enumeratedValue> 635 <name>dis</name> 636 <description>disable it.</description> 637 <value>1</value> 638 </enumeratedValue> 639 </enumeratedValues> 640 </field> 641 </fields> 642 </register> 643 <register> 644 <name>MEM_CTRL</name> 645 <description>Memory Clock Control Register.</description> 646 <addressOffset>0x28</addressOffset> 647 <fields> 648 <field> 649 <name>FWS</name> 650 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 651 <bitOffset>0</bitOffset> 652 <bitWidth>3</bitWidth> 653 </field> 654 <field> 655 <name>RAM0_LS</name> 656 <description>System RAM 0 Light Sleep Mode.</description> 657 <bitOffset>8</bitOffset> 658 <bitWidth>1</bitWidth> 659 <enumeratedValues> 660 <enumeratedValue> 661 <name>active</name> 662 <description>Memory is active.</description> 663 <value>0</value> 664 </enumeratedValue> 665 <enumeratedValue> 666 <name>light_sleep</name> 667 <description>Memory is in Light Sleep mode.</description> 668 <value>1</value> 669 </enumeratedValue> 670 </enumeratedValues> 671 </field> 672 <field> 673 <name>RAM1_LS</name> 674 <description>System RAM 1 Light Sleep Mode.</description> 675 <bitOffset>9</bitOffset> 676 <bitWidth>1</bitWidth> 677 <enumeratedValues> 678 <enumeratedValue> 679 <name>active</name> 680 <description>Memory is active.</description> 681 <value>0</value> 682 </enumeratedValue> 683 <enumeratedValue> 684 <name>light_sleep</name> 685 <description>Memory is in Light Sleep mode.</description> 686 <value>1</value> 687 </enumeratedValue> 688 </enumeratedValues> 689 </field> 690 <field> 691 <name>RAM2_LS</name> 692 <description>System RAM 2 Light Sleep Mode.</description> 693 <bitOffset>10</bitOffset> 694 <bitWidth>1</bitWidth> 695 <enumeratedValues> 696 <enumeratedValue> 697 <name>active</name> 698 <description>Memory is active.</description> 699 <value>0</value> 700 </enumeratedValue> 701 <enumeratedValue> 702 <name>light_sleep</name> 703 <description>Memory is in Light Sleep mode.</description> 704 <value>1</value> 705 </enumeratedValue> 706 </enumeratedValues> 707 </field> 708 <field> 709 <name>RAM3_LS</name> 710 <description>System RAM 3 Light Sleep Mode.</description> 711 <bitOffset>11</bitOffset> 712 <bitWidth>1</bitWidth> 713 <enumeratedValues> 714 <enumeratedValue> 715 <name>active</name> 716 <description>Memory is active.</description> 717 <value>0</value> 718 </enumeratedValue> 719 <enumeratedValue> 720 <name>light_sleep</name> 721 <description>Memory is in Light Sleep mode.</description> 722 <value>1</value> 723 </enumeratedValue> 724 </enumeratedValues> 725 </field> 726 <field> 727 <name>ICACHE_RET</name> 728 <description>ICache RAM Light Sleep Mode.</description> 729 <bitOffset>12</bitOffset> 730 <bitWidth>1</bitWidth> 731 <enumeratedValues> 732 <enumeratedValue> 733 <name>active</name> 734 <description>Memory is active.</description> 735 <value>0</value> 736 </enumeratedValue> 737 <enumeratedValue> 738 <name>light_sleep</name> 739 <description>Memory is in Light Sleep mode.</description> 740 <value>1</value> 741 </enumeratedValue> 742 </enumeratedValues> 743 </field> 744 </fields> 745 </register> 746 <register> 747 <name>MEM_ZCTRL</name> 748 <description>Memory Zeroize Control.</description> 749 <addressOffset>0x2C</addressOffset> 750 <fields> 751 <field> 752 <name>SRAM_ZERO</name> 753 <description>System RAM Block 0.</description> 754 <bitOffset>0</bitOffset> 755 <bitWidth>1</bitWidth> 756 <enumeratedValues> 757 <enumeratedValue> 758 <name>nop</name> 759 <description>No operation/complete.</description> 760 <value>0</value> 761 </enumeratedValue> 762 <enumeratedValue> 763 <name>start</name> 764 <description>Start operation.</description> 765 <value>1</value> 766 </enumeratedValue> 767 </enumeratedValues> 768 </field> 769 <field> 770 <name>ICACHE_ZERO</name> 771 <description>Instruction Cache.</description> 772 <bitOffset>1</bitOffset> 773 <bitWidth>1</bitWidth> 774 <enumeratedValues> 775 <enumeratedValue> 776 <name>nop</name> 777 <description>No operation/complete.</description> 778 <value>0</value> 779 </enumeratedValue> 780 <enumeratedValue> 781 <name>start</name> 782 <description>Start operation.</description> 783 <value>1</value> 784 </enumeratedValue> 785 </enumeratedValues> 786 </field> 787 </fields> 788 </register> 789 <register> 790 <name>SYS_STAT</name> 791 <description>System Status Register.</description> 792 <addressOffset>0x40</addressOffset> 793 <fields> 794 <field> 795 <name>ICECLOCK</name> 796 <description>ARM ICE Lock Status.</description> 797 <bitOffset>0</bitOffset> 798 <bitWidth>1</bitWidth> 799 <enumeratedValues> 800 <enumeratedValue> 801 <name>unlocked</name> 802 <description>ICE is unlocked.</description> 803 <value>0</value> 804 </enumeratedValue> 805 <enumeratedValue> 806 <name>locked</name> 807 <description>ICE is locked.</description> 808 <value>1</value> 809 </enumeratedValue> 810 </enumeratedValues> 811 </field> 812 </fields> 813 </register> 814 <register> 815 <name>RST1</name> 816 <description>Reset 1.</description> 817 <addressOffset>0x44</addressOffset> 818 <fields> 819 <field> 820 <name>I2C1</name> 821 <description>I2C1 Reset.</description> 822 <bitOffset>0</bitOffset> 823 <bitWidth>1</bitWidth> 824 <enumeratedValues> 825 <name>reset_write</name> 826 <usage>write</usage> 827 <enumeratedValue> 828 <name>RFU</name> 829 <description>Reserved. Do not use.</description> 830 <value>0</value> 831 </enumeratedValue> 832 <enumeratedValue> 833 <name>reset</name> 834 <description>Starts reset operation.</description> 835 <value>1</value> 836 </enumeratedValue> 837 </enumeratedValues> 838 <enumeratedValues> 839 <name>reset_read</name> 840 <usage>read</usage> 841 <enumeratedValue> 842 <name>reset_done</name> 843 <description>Reset complete.</description> 844 <value>0</value> 845 </enumeratedValue> 846 <enumeratedValue> 847 <name>busy</name> 848 <description>Reset in progress.</description> 849 <value>1</value> 850 </enumeratedValue> 851 </enumeratedValues> 852 </field> 853 </fields> 854 </register> 855 <register> 856 <name>PCLK_DIS1</name> 857 <description>Peripheral Clock Disable.</description> 858 <addressOffset>0x48</addressOffset> 859 <fields> 860 <field> 861 <name>FLCD</name> 862 <description>Secure Flash Controller Disable.</description> 863 <bitOffset>3</bitOffset> 864 <bitWidth>1</bitWidth> 865 <enumeratedValues> 866 <enumeratedValue> 867 <name>en</name> 868 <description>Enable.</description> 869 <value>0</value> 870 </enumeratedValue> 871 <enumeratedValue> 872 <name>dis</name> 873 <description>Disable.</description> 874 <value>1</value> 875 </enumeratedValue> 876 </enumeratedValues> 877 </field> 878 <field> 879 <name>ICCD</name> 880 <description>ICache Clock Disable. </description> 881 <bitOffset>11</bitOffset> 882 <bitWidth>1</bitWidth> 883 <enumeratedValues> 884 <enumeratedValue> 885 <name>en</name> 886 <description>Enable.</description> 887 <value>0</value> 888 </enumeratedValue> 889 <enumeratedValue> 890 <name>dis</name> 891 <description>Disable.</description> 892 <value>1</value> 893 </enumeratedValue> 894 </enumeratedValues> 895 </field> 896 </fields> 897 </register> 898 <register> 899 <name>EVTEN</name> 900 <description>Event Enable Register.</description> 901 <addressOffset>0x4C</addressOffset> 902 <fields> 903 <field> 904 <name>DMAEVENT</name> 905 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 906 <bitOffset>0</bitOffset> 907 <bitWidth>1</bitWidth> 908 </field> 909 <field> 910 <name>RX_EVT</name> 911 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 912 <bitOffset>1</bitOffset> 913 <bitWidth>1</bitWidth> 914 </field> 915 </fields> 916 </register> 917 <register> 918 <name>REV</name> 919 <description>Revision Register.</description> 920 <addressOffset>0x50</addressOffset> 921 <access>read-only</access> 922 <fields> 923 <field> 924 <name>REVISION</name> 925 <description>Manufacturer Chip Revision. </description> 926 <bitOffset>0</bitOffset> 927 <bitWidth>16</bitWidth> 928 </field> 929 </fields> 930 </register> 931 <register> 932 <name>SYS_IE</name> 933 <description>System Status Interrupt Enable</description> 934 <addressOffset>0x54</addressOffset> 935 <fields> 936 <field> 937 <name>ICEULIE</name> 938 <description>Arm ICE Unlocked Interrupt Enable. Set this bit to enable a PWRSEQ IRQ if the Arm ICE is unlocked.</description> 939 <bitOffset>0</bitOffset> 940 <bitWidth>1</bitWidth> 941 </field> 942 </fields> 943 </register> 944 </registers> 945 </peripheral> 946 <!-- GCR: Global Control Registers --> 947</device>
