1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SCON</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>BSTAPEN</name> 21 <description>Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.</description> 22 <bitOffset>0</bitOffset> 23 <bitWidth>1</bitWidth> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>dis</name> 27 <description>Boundary Scan TAP port disabled.</description> 28 <value>0</value> 29 </enumeratedValue> 30 <enumeratedValue> 31 <name>en</name> 32 <description>Boundary Scan TAP port enabled.</description> 33 <value>1</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>FLASH_PAGE_FLIP</name> 39 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 40 <bitOffset>4</bitOffset> 41 <bitWidth>1</bitWidth> 42 <enumeratedValues> 43 <enumeratedValue> 44 <name>normal</name> 45 <description>Physical layout matches logical layout.</description> 46 <value>0</value> 47 </enumeratedValue> 48 <enumeratedValue> 49 <name>flipped</name> 50 <description>Bottom half mapped to logical top half and vice versa.</description> 51 <value>1</value> 52 </enumeratedValue> 53 </enumeratedValues> 54 </field> 55 <field> 56 <name>CCACHE_FLUSH</name> 57 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 58 <bitOffset>6</bitOffset> 59 <bitWidth>1</bitWidth> 60 <enumeratedValues> 61 <enumeratedValue> 62 <name>normal</name> 63 <description>Normal Code Cache Operation</description> 64 <value>0</value> 65 </enumeratedValue> 66 <enumeratedValue> 67 <name>flush</name> 68 <description>Code Caches and CPU instruction buffer are flushed </description> 69 <value>1</value> 70 </enumeratedValue> 71 </enumeratedValues> 72 </field> 73 <field> 74 <name>DCACHE_FLUSH</name> 75 <description>Write 1 to flush the external memory controller's 16KB cache. This bit is automatically cleared to 0 when the flush is complete.</description> 76 <bitOffset>7</bitOffset> 77 <bitWidth>1</bitWidth> 78 <enumeratedValues> 79 <enumeratedValue> 80 <name>normal</name> 81 <description>Normal External Cache Operation</description> 82 <value>0</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>flush</name> 86 <description>External cache being flushed.</description> 87 <value>1</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 <field> 92 <name>DCACHE_DIS</name> 93 <description>Disable EMCC used for SPIXR or HyperBus/Xccela Bus code and data cache. </description> 94 <bitOffset>9</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>enabled</name> 99 <description>EMCC enabled.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>disabled</name> 104 <description>EMCC disabled and line buffer bypassed. </description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>CCHK</name> 111 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 112 <bitOffset>13</bitOffset> 113 <bitWidth>1</bitWidth> 114 <enumeratedValues> 115 <enumeratedValue> 116 <name>complete</name> 117 <description>No operation/complete.</description> 118 <value>0</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>start</name> 122 <description>Start operation.</description> 123 <value>1</value> 124 </enumeratedValue> 125 </enumeratedValues> 126 </field> 127 <field> 128 <name>CHKRES</name> 129 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 130 <bitOffset>15</bitOffset> 131 <bitWidth>1</bitWidth> 132 <enumeratedValues> 133 <enumeratedValue> 134 <name>pass</name> 135 <description>ROM Checksum Correct.</description> 136 <value>0</value> 137 </enumeratedValue> 138 <enumeratedValue> 139 <name>fail</name> 140 <description>ROM Checksum Fail.</description> 141 <value>1</value> 142 </enumeratedValue> 143 </enumeratedValues> 144 </field> 145 <field> 146 <name>OVR</name> 147 <description>These bits select the operating voltage range.</description> 148 <bitOffset>16</bitOffset> 149 <bitWidth>2</bitWidth> 150 <enumeratedValues> 151 <enumeratedValue> 152 <name>0v9</name> 153 <description>0.9V +/- 10%.</description> 154 <value>0</value> 155 </enumeratedValue> 156 <enumeratedValue> 157 <name>1V</name> 158 <description>1.0V +/- 10%.</description> 159 <value>1</value> 160 </enumeratedValue> 161 <enumeratedValue> 162 <name>1V1</name> 163 <description>1.1V +/- 10%.</description> 164 <value>2</value> 165 </enumeratedValue> 166 </enumeratedValues> 167 </field> 168 </fields> 169 </register> 170 <register> 171 <name>RST0</name> 172 <description>Reset.</description> 173 <addressOffset>0x04</addressOffset> 174 <fields> 175 <field> 176 <name>DMA</name> 177 <description>DMA Reset.</description> 178 <bitOffset>0</bitOffset> 179 <bitWidth>1</bitWidth> 180 </field> 181 <field derivedFrom="DMA"> 182 <name>WDT0</name> 183 <description>Watchdog Timer Reset.</description> 184 <bitOffset>1</bitOffset> 185 <bitWidth>1</bitWidth> 186 </field> 187 <field derivedFrom="DMA"> 188 <name>GPIO0</name> 189 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 190 <bitOffset>2</bitOffset> 191 <bitWidth>1</bitWidth> 192 </field> 193 <field derivedFrom="DMA"> 194 <name>GPIO1</name> 195 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 196 <bitOffset>3</bitOffset> 197 <bitWidth>1</bitWidth> 198 </field> 199 <field derivedFrom="DMA"> 200 <name>GPIO2</name> 201 <description>GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states.</description> 202 <bitOffset>4</bitOffset> 203 <bitWidth>1</bitWidth> 204 </field> 205 <field derivedFrom="DMA"> 206 <name>TIMER0</name> 207 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 208 <bitOffset>5</bitOffset> 209 <bitWidth>1</bitWidth> 210 </field> 211 <field derivedFrom="DMA"> 212 <name>TIMER1</name> 213 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 214 <bitOffset>6</bitOffset> 215 <bitWidth>1</bitWidth> 216 </field> 217 <field derivedFrom="DMA"> 218 <name>TIMER2</name> 219 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 220 <bitOffset>7</bitOffset> 221 <bitWidth>1</bitWidth> 222 </field> 223 <field derivedFrom="DMA"> 224 <name>TIMER3</name> 225 <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 226 <bitOffset>8</bitOffset> 227 <bitWidth>1</bitWidth> 228 </field> 229 <field derivedFrom="DMA"> 230 <name>TIMER4</name> 231 <description>Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks.</description> 232 <bitOffset>9</bitOffset> 233 <bitWidth>1</bitWidth> 234 </field> 235 <field derivedFrom="DMA"> 236 <name>TIMER5</name> 237 <description>Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks.</description> 238 <bitOffset>10</bitOffset> 239 <bitWidth>1</bitWidth> 240 </field> 241 <field derivedFrom="DMA"> 242 <name>UART0</name> 243 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 244 <bitOffset>11</bitOffset> 245 <bitWidth>1</bitWidth> 246 </field> 247 <field derivedFrom="DMA"> 248 <name>UART1</name> 249 <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 250 <bitOffset>12</bitOffset> 251 <bitWidth>1</bitWidth> 252 </field> 253 <field derivedFrom="DMA"> 254 <name>SPI0</name> 255 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 256 <bitOffset>13</bitOffset> 257 <bitWidth>1</bitWidth> 258 </field> 259 <field derivedFrom="DMA"> 260 <name>SPI1</name> 261 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 262 <bitOffset>14</bitOffset> 263 <bitWidth>1</bitWidth> 264 </field> 265 <field derivedFrom="DMA"> 266 <name>SPI2</name> 267 <description>SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description> 268 <bitOffset>15</bitOffset> 269 <bitWidth>1</bitWidth> 270 </field> 271 <field derivedFrom="DMA"> 272 <name>I2C0</name> 273 <description>I2C0 Reset.</description> 274 <bitOffset>16</bitOffset> 275 <bitWidth>1</bitWidth> 276 </field> 277 <field derivedFrom="DMA"> 278 <name>RTC</name> 279 <description>RTC Reset.</description> 280 <bitOffset>17</bitOffset> 281 <bitWidth>1</bitWidth> 282 </field> 283 <field derivedFrom="DMA"> 284 <name>TPU</name> 285 <description>Trust Protection Unit Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.</description> 286 <bitOffset>18</bitOffset> 287 <bitWidth>1</bitWidth> 288 </field> 289 <field derivedFrom="DMA"> 290 <name>HBC</name> 291 <description>HyperBus/Xccela controller reset.</description> 292 <bitOffset>21</bitOffset> 293 <bitWidth>1</bitWidth> 294 </field> 295 <field derivedFrom="DMA"> 296 <name>TFT</name> 297 <description>TFT controller reset.</description> 298 <bitOffset>22</bitOffset> 299 <bitWidth>1</bitWidth> 300 </field> 301 <field derivedFrom="DMA"> 302 <name>USB</name> 303 <description>USB Reset.</description> 304 <bitOffset>23</bitOffset> 305 <bitWidth>1</bitWidth> 306 </field> 307 <field derivedFrom="DMA"> 308 <name>ADC</name> 309 <description>Analog to Digital converter reset.</description> 310 <bitOffset>26</bitOffset> 311 <bitWidth>1</bitWidth> 312 </field> 313 <field derivedFrom="DMA"> 314 <name>UART2</name> 315 <description>UART 2 reset.</description> 316 <bitOffset>28</bitOffset> 317 <bitWidth>1</bitWidth> 318 </field> 319 <field derivedFrom="DMA"> 320 <name>SOFT</name> 321 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 322 <bitOffset>29</bitOffset> 323 <bitWidth>1</bitWidth> 324 </field> 325 <field derivedFrom="DMA"> 326 <name>PERIPH</name> 327 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 328 <bitOffset>30</bitOffset> 329 <bitWidth>1</bitWidth> 330 </field> 331 <field derivedFrom="DMA"> 332 <name>SYS</name> 333 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 334 <bitOffset>31</bitOffset> 335 <bitWidth>1</bitWidth> 336 </field> 337 </fields> 338 </register> 339 <register> 340 <name>CLK_CTRL</name> 341 <description>Clock Control.</description> 342 <addressOffset>0x08</addressOffset> 343 <resetValue>0x00000008</resetValue> 344 <fields> 345 <field> 346 <name>SYSCLK_PRESCALE</name> 347 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 348 <bitOffset>6</bitOffset> 349 <bitWidth>3</bitWidth> 350 <enumeratedValues> 351 <enumeratedValue> 352 <name>div1</name> 353 <description>Divide by 1.</description> 354 <value>0</value> 355 </enumeratedValue> 356 <enumeratedValue> 357 <name>div2</name> 358 <description>Divide by 2.</description> 359 <value>1</value> 360 </enumeratedValue> 361 <enumeratedValue> 362 <name>div4</name> 363 <description>Divide by 4.</description> 364 <value>2</value> 365 </enumeratedValue> 366 <enumeratedValue> 367 <name>div8</name> 368 <description>Divide by 8.</description> 369 <value>3</value> 370 </enumeratedValue> 371 <enumeratedValue> 372 <name>div16</name> 373 <description>Divide by 16.</description> 374 <value>4</value> 375 </enumeratedValue> 376 <enumeratedValue> 377 <name>div32</name> 378 <description>Divide by 32.</description> 379 <value>5</value> 380 </enumeratedValue> 381 <enumeratedValue> 382 <name>div64</name> 383 <description>Divide by 64.</description> 384 <value>6</value> 385 </enumeratedValue> 386 <enumeratedValue> 387 <name>div128</name> 388 <description>Divide by 128.</description> 389 <value>7</value> 390 </enumeratedValue> 391 </enumeratedValues> 392 </field> 393 <field> 394 <name>SYSOSC_SEL</name> 395 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 396 <bitOffset>9</bitOffset> 397 <bitWidth>3</bitWidth> 398 <enumeratedValues> 399 <enumeratedValue> 400 <name>CRYPTO</name> 401 <description>Internal Primary Oscilatior Clock</description> 402 <value>0</value> 403 </enumeratedValue> 404 <enumeratedValue> 405 <name>HFXIN</name> 406 <description>24MHz Internal Oscillator is used for the system clock.</description> 407 <value>2</value> 408 </enumeratedValue> 409 <enumeratedValue> 410 <name>NANORING</name> 411 <description>8kHz Internal Nano Ring Oscillator is used for the system clock.</description> 412 <value>3</value> 413 </enumeratedValue> 414 <enumeratedValue> 415 <name>HIRC96</name> 416 <description>120 MHz Internal Oscillator.</description> 417 <value>4</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>HIRC8</name> 421 <description>Internal 7.3728MHz oscillator.</description> 422 <value>5</value> 423 </enumeratedValue> 424 <enumeratedValue> 425 <name>X32K</name> 426 <description>External 32KHz oscillator.</description> 427 <value>6</value> 428 </enumeratedValue> 429 </enumeratedValues> 430 </field> 431 <field> 432 <name>SYSOSC_RDY</name> 433 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 434 <bitOffset>13</bitOffset> 435 <bitWidth>1</bitWidth> 436 <access>read-only</access> 437 <enumeratedValues> 438 <enumeratedValue> 439 <name>busy</name> 440 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 441 <value>0</value> 442 </enumeratedValue> 443 <enumeratedValue> 444 <name>ready</name> 445 <description>System clock running from CLKSEL clock source.</description> 446 <value>1</value> 447 </enumeratedValue> 448 </enumeratedValues> 449 </field> 450 <field> 451 <name>CCD</name> 452 <description>Cryptographic clock divider</description> 453 <bitOffset>15</bitOffset> 454 <bitWidth>1</bitWidth> 455 <access>read-only</access> 456 <enumeratedValues> 457 <enumeratedValue> 458 <name>non_div</name> 459 <description>The cryptographic accelerator clock is running in non-divided mode.</description> 460 <value>0</value> 461 </enumeratedValue> 462 <enumeratedValue> 463 <name>div</name> 464 <description>The cryptographic accelerator clock is running in divided mode.</description> 465 <value>1</value> 466 </enumeratedValue> 467 </enumeratedValues> 468 </field> 469 <field> 470 <name>X32K_EN</name> 471 <description>32KHz External Clock Enable.</description> 472 <bitOffset>17</bitOffset> 473 <bitWidth>1</bitWidth> 474 </field> 475 <field derivedFrom="X32K_EN"> 476 <name>CRYPTO_EN</name> 477 <description>50MHz High Frequency Internal Reference Clock Enable.</description> 478 <bitOffset>18</bitOffset> 479 <bitWidth>1</bitWidth> 480 </field> 481 <field derivedFrom="X32K_EN"> 482 <name>HIRC96_EN</name> 483 <description>120MHz High Frequency Internal Reference Clock Enable.</description> 484 <bitOffset>19</bitOffset> 485 <bitWidth>1</bitWidth> 486 </field> 487 <field derivedFrom="X32K_EN"> 488 <name>HIRC8_EN</name> 489 <description>7.3728MHz High Frequency Internal Reference Clock Enable.</description> 490 <bitOffset>20</bitOffset> 491 <bitWidth>1</bitWidth> 492 </field> 493 <field> 494 <name>HIRC8_VS</name> 495 <description>7.3728MHz Internal Oscillator Voltage Source Select</description> 496 <bitOffset>21</bitOffset> 497 <bitWidth>1</bitWidth> 498 </field> 499 <field> 500 <name>X32K_RDY</name> 501 <description>32KHz External Oscillator Ready.</description> 502 <bitOffset>25</bitOffset> 503 <bitWidth>1</bitWidth> 504 </field> 505 <field derivedFrom="X32K_RDY"> 506 <name>CRYPTO_RDY</name> 507 <description>50MHz Internal Oscillator Ready.</description> 508 <bitOffset>26</bitOffset> 509 <bitWidth>1</bitWidth> 510 </field> 511 <field derivedFrom="X32K_RDY"> 512 <name>HIRC96_RDY</name> 513 <description>120MHz Internal Oscillator Ready.</description> 514 <bitOffset>27</bitOffset> 515 <bitWidth>1</bitWidth> 516 </field> 517 <field derivedFrom="X32K_RDY"> 518 <name>HIRC8_RDY</name> 519 <description>7.3728MHz Internal Oscillator Ready.</description> 520 <bitOffset>28</bitOffset> 521 <bitWidth>1</bitWidth> 522 </field> 523 <field derivedFrom="X32K_RDY"> 524 <name>NANORING_RDY</name> 525 <description>Internal Nano Ring Oscillator Low Frequency Reference Clock Ready.</description> 526 <bitOffset>29</bitOffset> 527 <bitWidth>1</bitWidth> 528 </field> 529 </fields> 530 </register> 531 <register> 532 <name>PMR</name> 533 <description>Power Management.</description> 534 <addressOffset>0x0C</addressOffset> 535 <fields> 536 <field> 537 <name>MODE</name> 538 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 539 <bitOffset>0</bitOffset> 540 <bitWidth>3</bitWidth> 541 <enumeratedValues> 542 <enumeratedValue> 543 <name>active</name> 544 <description>Active Mode.</description> 545 <value>0</value> 546 </enumeratedValue> 547 <enumeratedValue> 548 <name>shutdown</name> 549 <description>Shutdown Mode.</description> 550 <value>3</value> 551 </enumeratedValue> 552 <enumeratedValue> 553 <name>backup</name> 554 <description>Backup Mode.</description> 555 <value>4</value> 556 </enumeratedValue> 557 </enumeratedValues> 558 </field> 559 <field> 560 <name>GPIOWKEN</name> 561 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 562 <bitOffset>4</bitOffset> 563 <bitWidth>1</bitWidth> 564 </field> 565 <field> 566 <name>RTCWKEN</name> 567 <description>RTC Wake Up Enable. This bit enables an RTC alarm to wake the device from any low-power mode to ACTIVE mode.</description> 568 <bitOffset>5</bitOffset> 569 <bitWidth>1</bitWidth> 570 </field> 571 <field> 572 <name>USBWKEN</name> 573 <description>USB Wake Up Enable. This enables a USB wakeup event to cause the device to exit from all low power modes into ACTIVE mode.</description> 574 <bitOffset>6</bitOffset> 575 <bitWidth>1</bitWidth> 576 </field> 577 <field> 578 <name>CRYPTOPD</name> 579 <description>Crypto Oscilator Power Down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. </description> 580 <bitOffset>15</bitOffset> 581 <bitWidth>1</bitWidth> 582 <enumeratedValues> 583 <enumeratedValue> 584 <name>active</name> 585 <description>Mode is Active.</description> 586 <value>0</value> 587 </enumeratedValue> 588 <enumeratedValue> 589 <name>deepsleep</name> 590 <description>Powered down in DEEPSLEEP.</description> 591 <value>1</value> 592 </enumeratedValue> 593 </enumeratedValues> 594 </field> 595 <field> 596 <name>HIRC96PD</name> 597 <description>120MHz Internal Oscillator power down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. </description> 598 <bitOffset>16</bitOffset> 599 <bitWidth>1</bitWidth> 600 <enumeratedValues> 601 <enumeratedValue> 602 <name>active</name> 603 <description>Mode is Active.</description> 604 <value>0</value> 605 </enumeratedValue> 606 <enumeratedValue> 607 <name>deepsleep</name> 608 <description>Powered down in DEEPSLEEP.</description> 609 <value>1</value> 610 </enumeratedValue> 611 </enumeratedValues> 612 </field> 613 <field> 614 <name>HIRC8PD</name> 615 <description>7.3728MHz Internal Oscillator power down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. </description> 616 <bitOffset>17</bitOffset> 617 <bitWidth>1</bitWidth> 618 <enumeratedValues> 619 <enumeratedValue> 620 <name>active</name> 621 <description>Mode is Active.</description> 622 <value>0</value> 623 </enumeratedValue> 624 <enumeratedValue> 625 <name>deepsleep</name> 626 <description>Powered down in DEEPSLEEP.</description> 627 <value>1</value> 628 </enumeratedValue> 629 </enumeratedValues> 630 </field> 631 </fields> 632 </register> 633 <register> 634 <name>PCLK_DIV</name> 635 <description>Peripheral Clock Divider.</description> 636 <addressOffset>0x18</addressOffset> 637 <resetValue>0x00000001</resetValue> 638 <fields> 639 <field> 640 <name>SDHCFRQ</name> 641 <description>This bit selects the frequency of the SDHC clock. If set, the clock oscillates at 50Mhz, otherwise it will oscillate at 60MHz.</description> 642 <bitOffset>7</bitOffset> 643 <bitWidth>1</bitWidth> 644 <enumeratedValues> 645 <enumeratedValue> 646 <name>60M</name> 647 <description>SDHC Freq = 120MHz/2.</description> 648 <value>0</value> 649 </enumeratedValue> 650 <enumeratedValue> 651 <name>50M</name> 652 <description>SDHC Freq = 50Mhz.</description> 653 <value>1</value> 654 </enumeratedValue> 655 </enumeratedValues> 656 </field> 657 <field> 658 <name>ADCFRQ</name> 659 <description>ADC Clock divider. ADC Clock Frequency = Periph_Clock/adcfrq. Values 0 and 1 invalid.</description> 660 <bitOffset>10</bitOffset> 661 <bitWidth>4</bitWidth> 662 <enumeratedValues> 663 <enumeratedValue> 664 <name>div2</name> 665 <description>ADC Freq = Periph_Clock/2.</description> 666 <value>2</value> 667 </enumeratedValue> 668 <enumeratedValue> 669 <name>div3</name> 670 <description>ADC Freq = Periph_Clock/3.</description> 671 <value>3</value> 672 </enumeratedValue> 673 <enumeratedValue> 674 <name>div4</name> 675 <description>ADC Freq = Periph_Clock/4.</description> 676 <value>4</value> 677 </enumeratedValue> 678 <enumeratedValue> 679 <name>div5</name> 680 <description>ADC Freq = Periph_Clock/5.</description> 681 <value>5</value> 682 </enumeratedValue> 683 <enumeratedValue> 684 <name>div6</name> 685 <description>ADC Freq = Periph_Clock/6.</description> 686 <value>6</value> 687 </enumeratedValue> 688 <enumeratedValue> 689 <name>div7</name> 690 <description>ADC Freq = Periph_Clock/7.</description> 691 <value>7</value> 692 </enumeratedValue> 693 <enumeratedValue> 694 <name>div8</name> 695 <description>ADC Freq = Periph_Clock/8.</description> 696 <value>8</value> 697 </enumeratedValue> 698 <enumeratedValue> 699 <name>div9</name> 700 <description>ADC Freq = Periph_Clock/9.</description> 701 <value>9</value> 702 </enumeratedValue> 703 <enumeratedValue> 704 <name>div10</name> 705 <description>ADC Freq = Periph_Clock/10.</description> 706 <value>10</value> 707 </enumeratedValue> 708 <enumeratedValue> 709 <name>div11</name> 710 <description>ADC Freq = Periph_Clock/11.</description> 711 <value>11</value> 712 </enumeratedValue> 713 <enumeratedValue> 714 <name>div12</name> 715 <description>ADC Freq = Periph_Clock/12.</description> 716 <value>12</value> 717 </enumeratedValue> 718 <enumeratedValue> 719 <name>div13</name> 720 <description>ADC Freq = Periph_Clock/13.</description> 721 <value>13</value> 722 </enumeratedValue> 723 <enumeratedValue> 724 <name>div14</name> 725 <description>ADC Freq = Periph_Clock/14.</description> 726 <value>14</value> 727 </enumeratedValue> 728 <enumeratedValue> 729 <name>div15</name> 730 <description>ADC Freq = Periph_Clock/15.</description> 731 <value>15</value> 732 </enumeratedValue> 733 </enumeratedValues> 734 </field> 735 <field> 736 <name>AONDIV</name> 737 <description>Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider.</description> 738 <bitOffset>14</bitOffset> 739 <bitWidth>2</bitWidth> 740 <enumeratedValues> 741 <enumeratedValue> 742 <name>div4</name> 743 <description>PCLK divide by 4.</description> 744 <value>0</value> 745 </enumeratedValue> 746 <enumeratedValue> 747 <name>div8</name> 748 <description>PCLK divide by 8.</description> 749 <value>1</value> 750 </enumeratedValue> 751 <enumeratedValue> 752 <name>div16</name> 753 <description>PCLK divide by 16.</description> 754 <value>2</value> 755 </enumeratedValue> 756 <enumeratedValue> 757 <name>div32</name> 758 <description>PCLK divide by 32.</description> 759 <value>3</value> 760 </enumeratedValue> 761 </enumeratedValues> 762 </field> 763 </fields> 764 </register> 765 <register> 766 <name>PCLK_DIS0</name> 767 <description>Peripheral Clock Disable.</description> 768 <addressOffset>0x24</addressOffset> 769 <fields> 770 <field> 771 <name>GPIO0</name> 772 <description>GPIO0 Clock Disable.</description> 773 <bitOffset>0</bitOffset> 774 <bitWidth>1</bitWidth> 775 <enumeratedValues> 776 <enumeratedValue> 777 <name>en</name> 778 <description>enable it.</description> 779 <value>0</value> 780 </enumeratedValue> 781 <enumeratedValue> 782 <name>dis</name> 783 <description>disable it.</description> 784 <value>1</value> 785 </enumeratedValue> 786 </enumeratedValues> 787 </field> 788 <field> 789 <name>GPIO1</name> 790 <description>GPIO1 Disable.</description> 791 <bitOffset>1</bitOffset> 792 <bitWidth>1</bitWidth> 793 <enumeratedValues> 794 <enumeratedValue> 795 <name>en</name> 796 <description>enable it.</description> 797 <value>0</value> 798 </enumeratedValue> 799 <enumeratedValue> 800 <name>dis</name> 801 <description>disable it.</description> 802 <value>1</value> 803 </enumeratedValue> 804 </enumeratedValues> 805 </field> 806 <field> 807 <name>GPIO2</name> 808 <description>GPIO2 Disable.</description> 809 <bitOffset>2</bitOffset> 810 <bitWidth>1</bitWidth> 811 <enumeratedValues> 812 <enumeratedValue> 813 <name>en</name> 814 <description>enable it.</description> 815 <value>0</value> 816 </enumeratedValue> 817 <enumeratedValue> 818 <name>dis</name> 819 <description>disable it.</description> 820 <value>1</value> 821 </enumeratedValue> 822 </enumeratedValues> 823 </field> 824 <field> 825 <name>USB</name> 826 <description>USB Disable.</description> 827 <bitOffset>3</bitOffset> 828 <bitWidth>1</bitWidth> 829 <enumeratedValues> 830 <enumeratedValue> 831 <name>en</name> 832 <description>enable it.</description> 833 <value>0</value> 834 </enumeratedValue> 835 <enumeratedValue> 836 <name>dis</name> 837 <description>disable it.</description> 838 <value>1</value> 839 </enumeratedValue> 840 </enumeratedValues> 841 </field> 842 <field> 843 <name>TFT</name> 844 <description>TFT Disable.</description> 845 <bitOffset>4</bitOffset> 846 <bitWidth>1</bitWidth> 847 <enumeratedValues> 848 <enumeratedValue> 849 <name>en</name> 850 <description>enable it.</description> 851 <value>0</value> 852 </enumeratedValue> 853 <enumeratedValue> 854 <name>dis</name> 855 <description>disable it.</description> 856 <value>1</value> 857 </enumeratedValue> 858 </enumeratedValues> 859 </field> 860 <field> 861 <name>DMA</name> 862 <description>DMA Disable.</description> 863 <bitOffset>5</bitOffset> 864 <bitWidth>1</bitWidth> 865 <enumeratedValues> 866 <enumeratedValue> 867 <name>en</name> 868 <description>enable it.</description> 869 <value>0</value> 870 </enumeratedValue> 871 <enumeratedValue> 872 <name>dis</name> 873 <description>disable it.</description> 874 <value>1</value> 875 </enumeratedValue> 876 </enumeratedValues> 877 </field> 878 <field> 879 <name>SPI0</name> 880 <description>SPI 0 Disable.</description> 881 <bitOffset>6</bitOffset> 882 <bitWidth>1</bitWidth> 883 <enumeratedValues> 884 <enumeratedValue> 885 <name>en</name> 886 <description>enable it.</description> 887 <value>0</value> 888 </enumeratedValue> 889 <enumeratedValue> 890 <name>dis</name> 891 <description>disable it.</description> 892 <value>1</value> 893 </enumeratedValue> 894 </enumeratedValues> 895 </field> 896 <field> 897 <name>SPI1</name> 898 <description>SPI 1 Disable.</description> 899 <bitOffset>7</bitOffset> 900 <bitWidth>1</bitWidth> 901 <enumeratedValues> 902 <enumeratedValue> 903 <name>en</name> 904 <description>enable it.</description> 905 <value>0</value> 906 </enumeratedValue> 907 <enumeratedValue> 908 <name>dis</name> 909 <description>disable it.</description> 910 <value>1</value> 911 </enumeratedValue> 912 </enumeratedValues> 913 </field> 914 <field> 915 <name>SPI2</name> 916 <description>SPI 2 Disable.</description> 917 <bitOffset>8</bitOffset> 918 <bitWidth>1</bitWidth> 919 <enumeratedValues> 920 <enumeratedValue> 921 <name>en</name> 922 <description>enable it.</description> 923 <value>0</value> 924 </enumeratedValue> 925 <enumeratedValue> 926 <name>dis</name> 927 <description>disable it.</description> 928 <value>1</value> 929 </enumeratedValue> 930 </enumeratedValues> 931 </field> 932 <field> 933 <name>UART0</name> 934 <description>UART 0 Disable.</description> 935 <bitOffset>9</bitOffset> 936 <bitWidth>1</bitWidth> 937 <enumeratedValues> 938 <enumeratedValue> 939 <name>en</name> 940 <description>enable it.</description> 941 <value>0</value> 942 </enumeratedValue> 943 <enumeratedValue> 944 <name>dis</name> 945 <description>disable it.</description> 946 <value>1</value> 947 </enumeratedValue> 948 </enumeratedValues> 949 </field> 950 <field> 951 <name>UART1</name> 952 <description>UART 1 Disable.</description> 953 <bitOffset>10</bitOffset> 954 <bitWidth>1</bitWidth> 955 <enumeratedValues> 956 <enumeratedValue> 957 <name>en</name> 958 <description>enable it.</description> 959 <value>0</value> 960 </enumeratedValue> 961 <enumeratedValue> 962 <name>dis</name> 963 <description>disable it.</description> 964 <value>1</value> 965 </enumeratedValue> 966 </enumeratedValues> 967 </field> 968 <field> 969 <name>I2C0</name> 970 <description>I2C 0 Disable.</description> 971 <bitOffset>13</bitOffset> 972 <bitWidth>1</bitWidth> 973 <enumeratedValues> 974 <enumeratedValue> 975 <name>en</name> 976 <description>enable it.</description> 977 <value>0</value> 978 </enumeratedValue> 979 <enumeratedValue> 980 <name>dis</name> 981 <description>disable it.</description> 982 <value>1</value> 983 </enumeratedValue> 984 </enumeratedValues> 985 </field> 986 <field> 987 <name>TPU</name> 988 <description>Trust Protection Unit Disable.</description> 989 <bitOffset>14</bitOffset> 990 <bitWidth>1</bitWidth> 991 <enumeratedValues> 992 <enumeratedValue> 993 <name>en</name> 994 <description>enable it.</description> 995 <value>0</value> 996 </enumeratedValue> 997 <enumeratedValue> 998 <name>dis</name> 999 <description>disable it.</description> 1000 <value>1</value> 1001 </enumeratedValue> 1002 </enumeratedValues> 1003 </field> 1004 <field> 1005 <name>TIMER0</name> 1006 <description>Timer 0 Disable.</description> 1007 <bitOffset>15</bitOffset> 1008 <bitWidth>1</bitWidth> 1009 <enumeratedValues> 1010 <enumeratedValue> 1011 <name>en</name> 1012 <description>enable it.</description> 1013 <value>0</value> 1014 </enumeratedValue> 1015 <enumeratedValue> 1016 <name>dis</name> 1017 <description>disable it.</description> 1018 <value>1</value> 1019 </enumeratedValue> 1020 </enumeratedValues> 1021 </field> 1022 <field> 1023 <name>TIMER1</name> 1024 <description>Timer 1 Disable.</description> 1025 <bitOffset>16</bitOffset> 1026 <bitWidth>1</bitWidth> 1027 <enumeratedValues> 1028 <enumeratedValue> 1029 <name>en</name> 1030 <description>enable it.</description> 1031 <value>0</value> 1032 </enumeratedValue> 1033 <enumeratedValue> 1034 <name>dis</name> 1035 <description>disable it.</description> 1036 <value>1</value> 1037 </enumeratedValue> 1038 </enumeratedValues> 1039 </field> 1040 <field> 1041 <name>TIMER2</name> 1042 <description>Timer 2 Disable.</description> 1043 <bitOffset>17</bitOffset> 1044 <bitWidth>1</bitWidth> 1045 <enumeratedValues> 1046 <enumeratedValue> 1047 <name>en</name> 1048 <description>enable it.</description> 1049 <value>0</value> 1050 </enumeratedValue> 1051 <enumeratedValue> 1052 <name>dis</name> 1053 <description>disable it.</description> 1054 <value>1</value> 1055 </enumeratedValue> 1056 </enumeratedValues> 1057 </field> 1058 <field> 1059 <name>TIMER3</name> 1060 <description>Timer 3 Disable.</description> 1061 <bitOffset>18</bitOffset> 1062 <bitWidth>1</bitWidth> 1063 <enumeratedValues> 1064 <enumeratedValue> 1065 <name>en</name> 1066 <description>enable it.</description> 1067 <value>0</value> 1068 </enumeratedValue> 1069 <enumeratedValue> 1070 <name>dis</name> 1071 <description>disable it.</description> 1072 <value>1</value> 1073 </enumeratedValue> 1074 </enumeratedValues> 1075 </field> 1076 <field> 1077 <name>TIMER4</name> 1078 <description>Timer 4 Disable.</description> 1079 <bitOffset>19</bitOffset> 1080 <bitWidth>1</bitWidth> 1081 <enumeratedValues> 1082 <enumeratedValue> 1083 <name>en</name> 1084 <description>enable it.</description> 1085 <value>0</value> 1086 </enumeratedValue> 1087 <enumeratedValue> 1088 <name>dis</name> 1089 <description>disable it.</description> 1090 <value>1</value> 1091 </enumeratedValue> 1092 </enumeratedValues> 1093 </field> 1094 <field> 1095 <name>TIMER5</name> 1096 <description>Timer 5 Disable.</description> 1097 <bitOffset>20</bitOffset> 1098 <bitWidth>1</bitWidth> 1099 <enumeratedValues> 1100 <enumeratedValue> 1101 <name>en</name> 1102 <description>enable it.</description> 1103 <value>0</value> 1104 </enumeratedValue> 1105 <enumeratedValue> 1106 <name>dis</name> 1107 <description>disable it.</description> 1108 <value>1</value> 1109 </enumeratedValue> 1110 </enumeratedValues> 1111 </field> 1112 <field> 1113 <name>ADC</name> 1114 <description>ADC Disable.</description> 1115 <bitOffset>23</bitOffset> 1116 <bitWidth>1</bitWidth> 1117 <enumeratedValues> 1118 <enumeratedValue> 1119 <name>en</name> 1120 <description>enable it.</description> 1121 <value>0</value> 1122 </enumeratedValue> 1123 <enumeratedValue> 1124 <name>dis</name> 1125 <description>disable it.</description> 1126 <value>1</value> 1127 </enumeratedValue> 1128 </enumeratedValues> 1129 </field> 1130 <field> 1131 <name>I2C1</name> 1132 <description>I2C 1 Disable.</description> 1133 <bitOffset>28</bitOffset> 1134 <bitWidth>1</bitWidth> 1135 <enumeratedValues> 1136 <enumeratedValue> 1137 <name>en</name> 1138 <description>enable it.</description> 1139 <value>0</value> 1140 </enumeratedValue> 1141 <enumeratedValue> 1142 <name>dis</name> 1143 <description>disable it.</description> 1144 <value>1</value> 1145 </enumeratedValue> 1146 </enumeratedValues> 1147 </field> 1148 <field> 1149 <name>PT</name> 1150 <description>Pulse Train Engine Disable.</description> 1151 <bitOffset>29</bitOffset> 1152 <bitWidth>1</bitWidth> 1153 <enumeratedValues> 1154 <enumeratedValue> 1155 <name>en</name> 1156 <description>enable it.</description> 1157 <value>0</value> 1158 </enumeratedValue> 1159 <enumeratedValue> 1160 <name>dis</name> 1161 <description>disable it.</description> 1162 <value>1</value> 1163 </enumeratedValue> 1164 </enumeratedValues> 1165 </field> 1166 <field> 1167 <name>SPIXIPF</name> 1168 <description>SPI-XIPF Disable.</description> 1169 <bitOffset>30</bitOffset> 1170 <bitWidth>1</bitWidth> 1171 <enumeratedValues> 1172 <enumeratedValue> 1173 <name>en</name> 1174 <description>enable it.</description> 1175 <value>0</value> 1176 </enumeratedValue> 1177 <enumeratedValue> 1178 <name>dis</name> 1179 <description>disable it.</description> 1180 <value>1</value> 1181 </enumeratedValue> 1182 </enumeratedValues> 1183 </field> 1184 <field> 1185 <name>SPIXIPM</name> 1186 <description>XSPI Master Clock Disable.</description> 1187 <bitOffset>31</bitOffset> 1188 <bitWidth>1</bitWidth> 1189 <enumeratedValues> 1190 <enumeratedValue> 1191 <name>en</name> 1192 <description>enable it.</description> 1193 <value>0</value> 1194 </enumeratedValue> 1195 <enumeratedValue> 1196 <name>dis</name> 1197 <description>disable it.</description> 1198 <value>1</value> 1199 </enumeratedValue> 1200 </enumeratedValues> 1201 </field> 1202 </fields> 1203 </register> 1204 <register> 1205 <name>MEM_CLK</name> 1206 <description>Memory Clock Control Register.</description> 1207 <addressOffset>0x28</addressOffset> 1208 <fields> 1209 <field> 1210 <name>FWS</name> 1211 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 1.</description> 1212 <bitOffset>0</bitOffset> 1213 <bitWidth>3</bitWidth> 1214 </field> 1215 <field> 1216 <name>SYSRAM0LS</name> 1217 <description>System RAM 0 Light Sleep Mode. Write 1 to put RAM0 in light sleep power mode.</description> 1218 <bitOffset>16</bitOffset> 1219 <bitWidth>1</bitWidth> 1220 <enumeratedValues> 1221 <enumeratedValue> 1222 <name>active</name> 1223 <description>RAM is active.</description> 1224 <value>0</value> 1225 </enumeratedValue> 1226 <enumeratedValue> 1227 <name>light_sleep</name> 1228 <description>RAM is in Light Sleep mode.</description> 1229 <value>1</value> 1230 </enumeratedValue> 1231 </enumeratedValues> 1232 </field> 1233 <field> 1234 <name>SYSRAM1LS</name> 1235 <description>System RAM 1 Light Sleep Mode. Write 1 to put RAM1 in light sleep power mode.</description> 1236 <bitOffset>17</bitOffset> 1237 <bitWidth>1</bitWidth> 1238 <enumeratedValues> 1239 <enumeratedValue> 1240 <name>active</name> 1241 <description>RAM is active.</description> 1242 <value>0</value> 1243 </enumeratedValue> 1244 <enumeratedValue> 1245 <name>light_sleep</name> 1246 <description>RAM is in Light Sleep mode.</description> 1247 <value>1</value> 1248 </enumeratedValue> 1249 </enumeratedValues> 1250 </field> 1251 <field> 1252 <name>SYSRAM2LS</name> 1253 <description>System RAM 2 Light Sleep Mode. Write 1 to put RAM2 in light sleep power mode.</description> 1254 <bitOffset>18</bitOffset> 1255 <bitWidth>1</bitWidth> 1256 <enumeratedValues> 1257 <enumeratedValue> 1258 <name>active</name> 1259 <description>RAM is active.</description> 1260 <value>0</value> 1261 </enumeratedValue> 1262 <enumeratedValue> 1263 <name>light_sleep</name> 1264 <description>RAM is in Light Sleep mode.</description> 1265 <value>1</value> 1266 </enumeratedValue> 1267 </enumeratedValues> 1268 </field> 1269 <field> 1270 <name>SYSRAM3LS</name> 1271 <description>System RAM 3 Light Sleep Mode. Write 1 to put RAM3 in light sleep power mode.</description> 1272 <bitOffset>19</bitOffset> 1273 <bitWidth>1</bitWidth> 1274 <enumeratedValues> 1275 <enumeratedValue> 1276 <name>active</name> 1277 <description>RAM is active.</description> 1278 <value>0</value> 1279 </enumeratedValue> 1280 <enumeratedValue> 1281 <name>light_sleep</name> 1282 <description>RAM is in Light Sleep mode.</description> 1283 <value>1</value> 1284 </enumeratedValue> 1285 </enumeratedValues> 1286 </field> 1287 <field> 1288 <name>SYSRAM4LS</name> 1289 <description>System RAM 4 Light Sleep Mode. Write 1 to put RAM4 in light sleep power mode.</description> 1290 <bitOffset>20</bitOffset> 1291 <bitWidth>1</bitWidth> 1292 <enumeratedValues> 1293 <enumeratedValue> 1294 <name>active</name> 1295 <description>RAM is active.</description> 1296 <value>0</value> 1297 </enumeratedValue> 1298 <enumeratedValue> 1299 <name>light_sleep</name> 1300 <description>RAM is in Light Sleep mode.</description> 1301 <value>1</value> 1302 </enumeratedValue> 1303 </enumeratedValues> 1304 </field> 1305 <field> 1306 <name>SYSRAM5LS</name> 1307 <description>System RAM 4 Light Sleep Mode. Write 1 to put RAM5 in light sleep power mode.</description> 1308 <bitOffset>21</bitOffset> 1309 <bitWidth>1</bitWidth> 1310 <enumeratedValues> 1311 <enumeratedValue> 1312 <name>active</name> 1313 <description>RAM is active.</description> 1314 <value>0</value> 1315 </enumeratedValue> 1316 <enumeratedValue> 1317 <name>light_sleep</name> 1318 <description>RAM is in Light Sleep mode.</description> 1319 <value>1</value> 1320 </enumeratedValue> 1321 </enumeratedValues> 1322 </field> 1323 <field> 1324 <name>SYSRAM6LS</name> 1325 <description>System RAM 4 Light Sleep Mode. Write 1 to put RAM6 in light sleep power mode.</description> 1326 <bitOffset>22</bitOffset> 1327 <bitWidth>1</bitWidth> 1328 <enumeratedValues> 1329 <enumeratedValue> 1330 <name>active</name> 1331 <description>RAM is active.</description> 1332 <value>0</value> 1333 </enumeratedValue> 1334 <enumeratedValue> 1335 <name>light_sleep</name> 1336 <description>RAM is in Light Sleep mode.</description> 1337 <value>1</value> 1338 </enumeratedValue> 1339 </enumeratedValues> 1340 </field> 1341 <field> 1342 <name>ICACHELS</name> 1343 <description>ICache RAM Light Sleep Mode.</description> 1344 <bitOffset>24</bitOffset> 1345 <bitWidth>1</bitWidth> 1346 <enumeratedValues> 1347 <enumeratedValue> 1348 <name>active</name> 1349 <description>RAM is active.</description> 1350 <value>0</value> 1351 </enumeratedValue> 1352 <enumeratedValue> 1353 <name>light_sleep</name> 1354 <description>RAM is in Light Sleep mode.</description> 1355 <value>1</value> 1356 </enumeratedValue> 1357 </enumeratedValues> 1358 </field> 1359 <field> 1360 <name>ICACHEXIPLS</name> 1361 <description>SPI-XIPF Instruction Cache RAM Light Sleep Mode.</description> 1362 <bitOffset>25</bitOffset> 1363 <bitWidth>1</bitWidth> 1364 <enumeratedValues> 1365 <enumeratedValue> 1366 <name>active</name> 1367 <description>RAM is active.</description> 1368 <value>0</value> 1369 </enumeratedValue> 1370 <enumeratedValue> 1371 <name>light_sleep</name> 1372 <description>RAM is in Light Sleep mode.</description> 1373 <value>1</value> 1374 </enumeratedValue> 1375 </enumeratedValues> 1376 </field> 1377 <field> 1378 <name>SCACHELS</name> 1379 <description>Internal RAM Cache Light Sleep Mode.</description> 1380 <bitOffset>26</bitOffset> 1381 <bitWidth>1</bitWidth> 1382 <enumeratedValues> 1383 <enumeratedValue> 1384 <name>active</name> 1385 <description>RAM is active.</description> 1386 <value>0</value> 1387 </enumeratedValue> 1388 <enumeratedValue> 1389 <name>light_sleep</name> 1390 <description>RAM is in Light Sleep mode.</description> 1391 <value>1</value> 1392 </enumeratedValue> 1393 </enumeratedValues> 1394 </field> 1395 <field> 1396 <name>CRYPTOLS</name> 1397 <description>Crypto RAM Light Sleep Mode.</description> 1398 <bitOffset>27</bitOffset> 1399 <bitWidth>1</bitWidth> 1400 <enumeratedValues> 1401 <enumeratedValue> 1402 <name>active</name> 1403 <description>RAM is active.</description> 1404 <value>0</value> 1405 </enumeratedValue> 1406 <enumeratedValue> 1407 <name>light_sleep</name> 1408 <description>RAM is in Light Sleep mode.</description> 1409 <value>1</value> 1410 </enumeratedValue> 1411 </enumeratedValues> 1412 </field> 1413 <field> 1414 <name>USBLS</name> 1415 <description>USB FIFO Light Sleep Mode.</description> 1416 <bitOffset>28</bitOffset> 1417 <bitWidth>1</bitWidth> 1418 <enumeratedValues> 1419 <enumeratedValue> 1420 <name>active</name> 1421 <description>RAM is active.</description> 1422 <value>0</value> 1423 </enumeratedValue> 1424 <enumeratedValue> 1425 <name>light_sleep</name> 1426 <description>RAM is in Light Sleep mode.</description> 1427 <value>1</value> 1428 </enumeratedValue> 1429 </enumeratedValues> 1430 </field> 1431 <field> 1432 <name>ROMLS</name> 1433 <description>ROM Light Sleep Mode.</description> 1434 <bitOffset>29</bitOffset> 1435 <bitWidth>1</bitWidth> 1436 <enumeratedValues> 1437 <enumeratedValue> 1438 <name>active</name> 1439 <description>RAM is active.</description> 1440 <value>0</value> 1441 </enumeratedValue> 1442 <enumeratedValue> 1443 <name>light_sleep</name> 1444 <description>RAM is in Light Sleep mode.</description> 1445 <value>1</value> 1446 </enumeratedValue> 1447 </enumeratedValues> 1448 </field> 1449 </fields> 1450 </register> 1451 <register> 1452 <name>MEM_ZERO</name> 1453 <description>Memory Zeroize Control.</description> 1454 <addressOffset>0x2C</addressOffset> 1455 <fields> 1456 <field> 1457 <name>SRAM0Z</name> 1458 <description>System RAM Block 0.</description> 1459 <bitOffset>0</bitOffset> 1460 <bitWidth>1</bitWidth> 1461 <enumeratedValues> 1462 <enumeratedValue> 1463 <name>nop</name> 1464 <description>No operation/complete.</description> 1465 <value>0</value> 1466 </enumeratedValue> 1467 <enumeratedValue> 1468 <name>start</name> 1469 <description>Start operation.</description> 1470 <value>1</value> 1471 </enumeratedValue> 1472 </enumeratedValues> 1473 </field> 1474 <field> 1475 <name>SRAM1Z</name> 1476 <description>System RAM Block 1.</description> 1477 <bitOffset>1</bitOffset> 1478 <bitWidth>1</bitWidth> 1479 <enumeratedValues> 1480 <enumeratedValue> 1481 <name>nop</name> 1482 <description>No operation/complete.</description> 1483 <value>0</value> 1484 </enumeratedValue> 1485 <enumeratedValue> 1486 <name>start</name> 1487 <description>Start operation.</description> 1488 <value>1</value> 1489 </enumeratedValue> 1490 </enumeratedValues> 1491 </field> 1492 <field> 1493 <name>SRAM2Z</name> 1494 <description>System RAM Block 2.</description> 1495 <bitOffset>2</bitOffset> 1496 <bitWidth>1</bitWidth> 1497 <enumeratedValues> 1498 <enumeratedValue> 1499 <name>nop</name> 1500 <description>No operation/complete.</description> 1501 <value>0</value> 1502 </enumeratedValue> 1503 <enumeratedValue> 1504 <name>start</name> 1505 <description>Start operation.</description> 1506 <value>1</value> 1507 </enumeratedValue> 1508 </enumeratedValues> 1509 </field> 1510 <field> 1511 <name>SRAM3Z</name> 1512 <description>System RAM Block 3.</description> 1513 <bitOffset>3</bitOffset> 1514 <bitWidth>1</bitWidth> 1515 <enumeratedValues> 1516 <enumeratedValue> 1517 <name>nop</name> 1518 <description>No operation/complete.</description> 1519 <value>0</value> 1520 </enumeratedValue> 1521 <enumeratedValue> 1522 <name>start</name> 1523 <description>Start operation.</description> 1524 <value>1</value> 1525 </enumeratedValue> 1526 </enumeratedValues> 1527 </field> 1528 <field> 1529 <name>SRAM4Z</name> 1530 <description>System RAM Block 4.</description> 1531 <bitOffset>4</bitOffset> 1532 <bitWidth>1</bitWidth> 1533 <enumeratedValues> 1534 <enumeratedValue> 1535 <name>nop</name> 1536 <description>No operation/complete.</description> 1537 <value>0</value> 1538 </enumeratedValue> 1539 <enumeratedValue> 1540 <name>start</name> 1541 <description>Start operation.</description> 1542 <value>1</value> 1543 </enumeratedValue> 1544 </enumeratedValues> 1545 </field> 1546 <field> 1547 <name>SRAM5Z</name> 1548 <description>System RAM Block 5.</description> 1549 <bitOffset>5</bitOffset> 1550 <bitWidth>1</bitWidth> 1551 <enumeratedValues> 1552 <enumeratedValue> 1553 <name>nop</name> 1554 <description>No operation/complete.</description> 1555 <value>0</value> 1556 </enumeratedValue> 1557 <enumeratedValue> 1558 <name>start</name> 1559 <description>Start operation.</description> 1560 <value>1</value> 1561 </enumeratedValue> 1562 </enumeratedValues> 1563 </field> 1564 <field> 1565 <name>SRAM6Z</name> 1566 <description>System RAM Block 6.</description> 1567 <bitOffset>6</bitOffset> 1568 <bitWidth>1</bitWidth> 1569 <enumeratedValues> 1570 <enumeratedValue> 1571 <name>nop</name> 1572 <description>No operation/complete.</description> 1573 <value>0</value> 1574 </enumeratedValue> 1575 <enumeratedValue> 1576 <name>start</name> 1577 <description>Start operation.</description> 1578 <value>1</value> 1579 </enumeratedValue> 1580 </enumeratedValues> 1581 </field> 1582 <field> 1583 <name>ICACHEZ</name> 1584 <description>Instruction Cache (ICC0) zeroization.</description> 1585 <bitOffset>8</bitOffset> 1586 <bitWidth>1</bitWidth> 1587 <enumeratedValues> 1588 <enumeratedValue> 1589 <name>nop</name> 1590 <description>No operation/complete.</description> 1591 <value>0</value> 1592 </enumeratedValue> 1593 <enumeratedValue> 1594 <name>start</name> 1595 <description>Start operation.</description> 1596 <value>1</value> 1597 </enumeratedValue> 1598 </enumeratedValues> 1599 </field> 1600 <field> 1601 <name>ICACHEXIPZ</name> 1602 <description>SPI-XIPF Instruction Cache (ICC1) zeroization.</description> 1603 <bitOffset>9</bitOffset> 1604 <bitWidth>1</bitWidth> 1605 <enumeratedValues> 1606 <enumeratedValue> 1607 <name>nop</name> 1608 <description>No operation/complete.</description> 1609 <value>0</value> 1610 </enumeratedValue> 1611 <enumeratedValue> 1612 <name>start</name> 1613 <description>Start operation.</description> 1614 <value>1</value> 1615 </enumeratedValue> 1616 </enumeratedValues> 1617 </field> 1618 <field> 1619 <name>SCACHEDATAZ</name> 1620 <description>EMCC data zeroization.</description> 1621 <bitOffset>10</bitOffset> 1622 <bitWidth>1</bitWidth> 1623 <enumeratedValues> 1624 <enumeratedValue> 1625 <name>nop</name> 1626 <description>No operation/complete.</description> 1627 <value>0</value> 1628 </enumeratedValue> 1629 <enumeratedValue> 1630 <name>start</name> 1631 <description>Start operation.</description> 1632 <value>1</value> 1633 </enumeratedValue> 1634 </enumeratedValues> 1635 </field> 1636 <field> 1637 <name>SCACHETAGZ</name> 1638 <description>EMCC tag zeroization.</description> 1639 <bitOffset>11</bitOffset> 1640 <bitWidth>1</bitWidth> 1641 <enumeratedValues> 1642 <enumeratedValue> 1643 <name>nop</name> 1644 <description>No operation/complete.</description> 1645 <value>0</value> 1646 </enumeratedValue> 1647 <enumeratedValue> 1648 <name>start</name> 1649 <description>Start operation.</description> 1650 <value>1</value> 1651 </enumeratedValue> 1652 </enumeratedValues> 1653 </field> 1654 <field> 1655 <name>CRYPTOZ</name> 1656 <description>Crypto MAA Memory zeroization.</description> 1657 <bitOffset>12</bitOffset> 1658 <bitWidth>1</bitWidth> 1659 <enumeratedValues> 1660 <enumeratedValue> 1661 <name>nop</name> 1662 <description>No operation/complete.</description> 1663 <value>0</value> 1664 </enumeratedValue> 1665 <enumeratedValue> 1666 <name>start</name> 1667 <description>Start operation.</description> 1668 <value>1</value> 1669 </enumeratedValue> 1670 </enumeratedValues> 1671 </field> 1672 <field> 1673 <name>USBFIFOZ</name> 1674 <description>USB FIFO zeroization.</description> 1675 <bitOffset>13</bitOffset> 1676 <bitWidth>1</bitWidth> 1677 <enumeratedValues> 1678 <enumeratedValue> 1679 <name>nop</name> 1680 <description>No operation/complete.</description> 1681 <value>0</value> 1682 </enumeratedValue> 1683 <enumeratedValue> 1684 <name>start</name> 1685 <description>Start operation.</description> 1686 <value>1</value> 1687 </enumeratedValue> 1688 </enumeratedValues> 1689 </field> 1690 </fields> 1691 </register> 1692 <register> 1693 <name>SYS_STAT</name> 1694 <description>System Status Register.</description> 1695 <addressOffset>0x40</addressOffset> 1696 <fields> 1697 <field> 1698 <name>ICELOCK</name> 1699 <description>ARM ICE Lock Status.</description> 1700 <bitOffset>0</bitOffset> 1701 <bitWidth>1</bitWidth> 1702 <enumeratedValues> 1703 <enumeratedValue> 1704 <name>unlocked</name> 1705 <description>ICE is unlocked.</description> 1706 <value>0</value> 1707 </enumeratedValue> 1708 <enumeratedValue> 1709 <name>locked</name> 1710 <description>ICE is locked.</description> 1711 <value>1</value> 1712 </enumeratedValue> 1713 </enumeratedValues> 1714 </field> 1715 <field> 1716 <name>CODEINTERR</name> 1717 <description>Flash SPI-XIPF Code Integrity Error Status Flag.</description> 1718 <bitOffset>1</bitOffset> 1719 <bitWidth>1</bitWidth> 1720 <enumeratedValues> 1721 <enumeratedValue> 1722 <name>noerr</name> 1723 <description> .</description> 1724 <value>0</value> 1725 </enumeratedValue> 1726 <enumeratedValue> 1727 <name>err</name> 1728 <description>SPI-XIPF code integrity error.</description> 1729 <value>1</value> 1730 </enumeratedValue> 1731 </enumeratedValues> 1732 </field> 1733 <field> 1734 <name>SCMEMF</name> 1735 <description>HyperBus/Xccela Cache Memory Error Status Flag.</description> 1736 <bitOffset>5</bitOffset> 1737 <bitWidth>1</bitWidth> 1738 <enumeratedValues> 1739 <enumeratedValue> 1740 <name>noerr</name> 1741 <description>Normal operation.</description> 1742 <value>0</value> 1743 </enumeratedValue> 1744 <enumeratedValue> 1745 <name>memfault</name> 1746 <description>HyperBus/Xccela cahce memory fault.</description> 1747 <value>1</value> 1748 </enumeratedValue> 1749 </enumeratedValues> 1750 </field> 1751 </fields> 1752 </register> 1753 <register> 1754 <name>RST1</name> 1755 <description>Reset 1.</description> 1756 <addressOffset>0x44</addressOffset> 1757 <fields> 1758 <field> 1759 <name>I2C1</name> 1760 <description>I2C1 Reset.</description> 1761 <bitOffset>0</bitOffset> 1762 <bitWidth>1</bitWidth> 1763 </field> 1764 <field derivedFrom="I2C1"> 1765 <name>PT</name> 1766 <description>Pulse Train Reset.</description> 1767 <bitOffset>1</bitOffset> 1768 <bitWidth>1</bitWidth> 1769 </field> 1770 <field derivedFrom="I2C1"> 1771 <name>SPIXIP</name> 1772 <description>SPI-XIPF Reset.</description> 1773 <bitOffset>3</bitOffset> 1774 <bitWidth>1</bitWidth> 1775 </field> 1776 <field derivedFrom="I2C1"> 1777 <name>XSPIM</name> 1778 <description>XSPI Master Reset.</description> 1779 <bitOffset>4</bitOffset> 1780 <bitWidth>1</bitWidth> 1781 </field> 1782 <field derivedFrom="I2C1"> 1783 <name>GPIO3</name> 1784 <description>GPIO3 Reset.</description> 1785 <bitOffset>5</bitOffset> 1786 <bitWidth>1</bitWidth> 1787 </field> 1788 <field derivedFrom="I2C1"> 1789 <name>SDHC</name> 1790 <description>SDHC Reset.</description> 1791 <bitOffset>6</bitOffset> 1792 <bitWidth>1</bitWidth> 1793 </field> 1794 <field derivedFrom="I2C1"> 1795 <name>OWIRE</name> 1796 <description>One-Wire Reset.</description> 1797 <bitOffset>7</bitOffset> 1798 <bitWidth>1</bitWidth> 1799 </field> 1800 <field derivedFrom="I2C1"> 1801 <name>WDT1</name> 1802 <description>WDT1 Reset.</description> 1803 <bitOffset>8</bitOffset> 1804 <bitWidth>1</bitWidth> 1805 </field> 1806 <field derivedFrom="I2C1"> 1807 <name>SPI3</name> 1808 <description>SPI3 Reset.</description> 1809 <bitOffset>9</bitOffset> 1810 <bitWidth>1</bitWidth> 1811 </field> 1812 <field derivedFrom="I2C1"> 1813 <name>I2S</name> 1814 <description>I2S (SPIMSS) Reset.</description> 1815 <bitOffset>10</bitOffset> 1816 <bitWidth>1</bitWidth> 1817 </field> 1818 <field derivedFrom="I2C1"> 1819 <name>XIPR</name> 1820 <description>SPIXR Reset.</description> 1821 <bitOffset>15</bitOffset> 1822 <bitWidth>1</bitWidth> 1823 </field> 1824 <field derivedFrom="I2C1"> 1825 <name>SEMA</name> 1826 <description>Semaphore Block Reset.</description> 1827 <bitOffset>16</bitOffset> 1828 <bitWidth>1</bitWidth> 1829 </field> 1830 </fields> 1831 </register> 1832 <register> 1833 <name>PCLK_DIS1</name> 1834 <description>Peripheral Clock Disable.</description> 1835 <addressOffset>0x48</addressOffset> 1836 <fields> 1837 <field> 1838 <name>UART2</name> 1839 <description>UART2 Disable.</description> 1840 <bitOffset>1</bitOffset> 1841 <bitWidth>1</bitWidth> 1842 <enumeratedValues> 1843 <enumeratedValue> 1844 <name>en</name> 1845 <description>Clock enabled to the peripheral.</description> 1846 <value>0</value> 1847 </enumeratedValue> 1848 <enumeratedValue> 1849 <name>dis</name> 1850 <description>Clock disabled to the peripheral.</description> 1851 <value>1</value> 1852 </enumeratedValue> 1853 </enumeratedValues> 1854 </field> 1855 <field> 1856 <name>TRNG</name> 1857 <description>TRNG Disable.</description> 1858 <bitOffset>2</bitOffset> 1859 <bitWidth>1</bitWidth> 1860 <enumeratedValues> 1861 <enumeratedValue> 1862 <name>en</name> 1863 <description>Clock enabled to the peripheral.</description> 1864 <value>0</value> 1865 </enumeratedValue> 1866 <enumeratedValue> 1867 <name>dis</name> 1868 <description>Clock disabled to the peripheral.</description> 1869 <value>1</value> 1870 </enumeratedValue> 1871 </enumeratedValues> 1872 </field> 1873 <field> 1874 <name>SFLC</name> 1875 <description>Secore Flash Controller Clock Disable.</description> 1876 <bitOffset>3</bitOffset> 1877 <bitWidth>1</bitWidth> 1878 <enumeratedValues> 1879 <enumeratedValue> 1880 <name>en</name> 1881 <description>Clock enabled to the peripheral.</description> 1882 <value>0</value> 1883 </enumeratedValue> 1884 <enumeratedValue> 1885 <name>dis</name> 1886 <description>Clock disabled to the peripheral.</description> 1887 <value>1</value> 1888 </enumeratedValue> 1889 </enumeratedValues> 1890 </field> 1891 <field> 1892 <name>HBC</name> 1893 <description>HyperBus/Xccela Clock Disable.</description> 1894 <bitOffset>4</bitOffset> 1895 <bitWidth>1</bitWidth> 1896 <enumeratedValues> 1897 <enumeratedValue> 1898 <name>en</name> 1899 <description>Clock enabled to the peripheral.</description> 1900 <value>0</value> 1901 </enumeratedValue> 1902 <enumeratedValue> 1903 <name>dis</name> 1904 <description>Clock disabled to the peripheral.</description> 1905 <value>1</value> 1906 </enumeratedValue> 1907 </enumeratedValues> 1908 </field> 1909 <field> 1910 <name>GPIO3</name> 1911 <description>GPIO3 Disable.</description> 1912 <bitOffset>6</bitOffset> 1913 <bitWidth>1</bitWidth> 1914 <enumeratedValues> 1915 <enumeratedValue> 1916 <name>en</name> 1917 <description>Clock enabled to the peripheral.</description> 1918 <value>0</value> 1919 </enumeratedValue> 1920 <enumeratedValue> 1921 <name>dis</name> 1922 <description>Clock disabled to the peripheral.</description> 1923 <value>1</value> 1924 </enumeratedValue> 1925 </enumeratedValues> 1926 </field> 1927 <field> 1928 <name>SCACHE</name> 1929 <description>System Cache Clock Disable.</description> 1930 <bitOffset>7</bitOffset> 1931 <bitWidth>1</bitWidth> 1932 <enumeratedValues> 1933 <enumeratedValue> 1934 <name>en</name> 1935 <description>Clock enabled to the peripheral.</description> 1936 <value>0</value> 1937 </enumeratedValue> 1938 <enumeratedValue> 1939 <name>dis</name> 1940 <description>Clock disabled to the peripheral.</description> 1941 <value>1</value> 1942 </enumeratedValue> 1943 </enumeratedValues> 1944 </field> 1945 <field> 1946 <name>SDMA</name> 1947 <description>Smart DMA Clock Disable.</description> 1948 <bitOffset>8</bitOffset> 1949 <bitWidth>1</bitWidth> 1950 <enumeratedValues> 1951 <enumeratedValue> 1952 <name>en</name> 1953 <description>Clock enabled to the peripheral.</description> 1954 <value>0</value> 1955 </enumeratedValue> 1956 <enumeratedValue> 1957 <name>dis</name> 1958 <description>Clock disabled to the peripheral.</description> 1959 <value>1</value> 1960 </enumeratedValue> 1961 </enumeratedValues> 1962 </field> 1963 <field> 1964 <name>SEMA</name> 1965 <description>Semaphore Block Clock Disable.</description> 1966 <bitOffset>9</bitOffset> 1967 <bitWidth>1</bitWidth> 1968 <enumeratedValues> 1969 <enumeratedValue> 1970 <name>en</name> 1971 <description>Clock enabled to the peripheral.</description> 1972 <value>0</value> 1973 </enumeratedValue> 1974 <enumeratedValue> 1975 <name>dis</name> 1976 <description>Clock disabled to the peripheral.</description> 1977 <value>1</value> 1978 </enumeratedValue> 1979 </enumeratedValues> 1980 </field> 1981 <field> 1982 <name>SDHC</name> 1983 <description>SDHC Controller Clock Disable.</description> 1984 <bitOffset>10</bitOffset> 1985 <bitWidth>1</bitWidth> 1986 <enumeratedValues> 1987 <enumeratedValue> 1988 <name>en</name> 1989 <description>Clock enabled to the peripheral.</description> 1990 <value>0</value> 1991 </enumeratedValue> 1992 <enumeratedValue> 1993 <name>dis</name> 1994 <description>Clock disabled to the peripheral.</description> 1995 <value>1</value> 1996 </enumeratedValue> 1997 </enumeratedValues> 1998 </field> 1999 <field> 2000 <name>ICACHE</name> 2001 <description>Flash Instruction Cache Clock Disable.</description> 2002 <bitOffset>11</bitOffset> 2003 <bitWidth>1</bitWidth> 2004 <enumeratedValues> 2005 <enumeratedValue> 2006 <name>en</name> 2007 <description>Clock enabled to the peripheral.</description> 2008 <value>0</value> 2009 </enumeratedValue> 2010 <enumeratedValue> 2011 <name>dis</name> 2012 <description>Clock disabled to the peripheral.</description> 2013 <value>1</value> 2014 </enumeratedValue> 2015 </enumeratedValues> 2016 </field> 2017 <field> 2018 <name>ICACHEXIPF</name> 2019 <description>SPI-XIPF Flash Clock Disable.</description> 2020 <bitOffset>12</bitOffset> 2021 <bitWidth>1</bitWidth> 2022 <enumeratedValues> 2023 <enumeratedValue> 2024 <name>en</name> 2025 <description>Clock enabled to the peripheral.</description> 2026 <value>0</value> 2027 </enumeratedValue> 2028 <enumeratedValue> 2029 <name>dis</name> 2030 <description>Clock disabled to the peripheral.</description> 2031 <value>1</value> 2032 </enumeratedValue> 2033 </enumeratedValues> 2034 </field> 2035 <field> 2036 <name>OW</name> 2037 <description>One-Wire Clock Disable.</description> 2038 <bitOffset>13</bitOffset> 2039 <bitWidth>1</bitWidth> 2040 <enumeratedValues> 2041 <enumeratedValue> 2042 <name>en</name> 2043 <description>Clock enabled to the peripheral.</description> 2044 <value>0</value> 2045 </enumeratedValue> 2046 <enumeratedValue> 2047 <name>dis</name> 2048 <description>Clock disabled to the peripheral.</description> 2049 <value>1</value> 2050 </enumeratedValue> 2051 </enumeratedValues> 2052 </field> 2053 <field> 2054 <name>SPI3</name> 2055 <description>SPI3 Clock Disable.</description> 2056 <bitOffset>14</bitOffset> 2057 <bitWidth>1</bitWidth> 2058 <enumeratedValues> 2059 <enumeratedValue> 2060 <name>en</name> 2061 <description>Clock enabled to the peripheral.</description> 2062 <value>0</value> 2063 </enumeratedValue> 2064 <enumeratedValue> 2065 <name>dis</name> 2066 <description>Clock disabled to the peripheral.</description> 2067 <value>1</value> 2068 </enumeratedValue> 2069 </enumeratedValues> 2070 </field> 2071 <field> 2072 <name>I2S</name> 2073 <description>I2S (SPIMSS) Clock Disable.</description> 2074 <bitOffset>15</bitOffset> 2075 <bitWidth>1</bitWidth> 2076 <enumeratedValues> 2077 <enumeratedValue> 2078 <name>en</name> 2079 <description>Clock enabled to the peripheral.</description> 2080 <value>0</value> 2081 </enumeratedValue> 2082 <enumeratedValue> 2083 <name>dis</name> 2084 <description>Clock disabled to the peripheral.</description> 2085 <value>1</value> 2086 </enumeratedValue> 2087 </enumeratedValues> 2088 </field> 2089 <field> 2090 <name>SPIXIPR</name> 2091 <description>SPIXR RAM Clock Disable.</description> 2092 <bitOffset>20</bitOffset> 2093 <bitWidth>1</bitWidth> 2094 <enumeratedValues> 2095 <enumeratedValue> 2096 <name>en</name> 2097 <description>Clock enabled to the peripheral.</description> 2098 <value>0</value> 2099 </enumeratedValue> 2100 <enumeratedValue> 2101 <name>dis</name> 2102 <description>Clock disabled to the peripheral.</description> 2103 <value>1</value> 2104 </enumeratedValue> 2105 </enumeratedValues> 2106 </field> 2107 </fields> 2108 </register> 2109 <register> 2110 <name>EVENT_EN</name> 2111 <description>Event Enable Register.</description> 2112 <addressOffset>0x4C</addressOffset> 2113 <fields> 2114 <field> 2115 <name>DMAEVENT</name> 2116 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 2117 <bitOffset>0</bitOffset> 2118 <bitWidth>1</bitWidth> 2119 <enumeratedValues> 2120 <enumeratedValue> 2121 <name>dis</name> 2122 <description>DMA CTZ Event will not wake up the device.</description> 2123 <value>0</value> 2124 </enumeratedValue> 2125 <enumeratedValue> 2126 <name>en</name> 2127 <description>DMA CTZ Event Wake-up Enabled.</description> 2128 <value>1</value> 2129 </enumeratedValue> 2130 </enumeratedValues> 2131 </field> 2132 <field> 2133 <name>RXEVENT</name> 2134 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 2135 <bitOffset>1</bitOffset> 2136 <bitWidth>1</bitWidth> 2137 <enumeratedValues> 2138 <enumeratedValue> 2139 <name>dis</name> 2140 <description>A receive event is not generated when an external input transitions from low to high.</description> 2141 <value>0</value> 2142 </enumeratedValue> 2143 <enumeratedValue> 2144 <name>en</name> 2145 <description>A receive event is generated when external event is triggered.</description> 2146 <value>1</value> 2147 </enumeratedValue> 2148 </enumeratedValues> 2149 </field> 2150 <field> 2151 <name>TXEVENT</name> 2152 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].</description> 2153 <bitOffset>2</bitOffset> 2154 <bitWidth>1</bitWidth> 2155 <enumeratedValues> 2156 <enumeratedValue> 2157 <name>dis</name> 2158 <description>Transmit event disabled.</description> 2159 <value>0</value> 2160 </enumeratedValue> 2161 <enumeratedValue> 2162 <name>en</name> 2163 <description>A transmit event is enabled on Send Event instruction.</description> 2164 <value>1</value> 2165 </enumeratedValue> 2166 </enumeratedValues> 2167 </field> 2168 </fields> 2169 </register> 2170 <register> 2171 <name>REV</name> 2172 <description>Revision Register.</description> 2173 <addressOffset>0x50</addressOffset> 2174 <access>read-only</access> 2175 <fields> 2176 <field> 2177 <name>REVISION</name> 2178 <description>Manufacturer Chip Revision. </description> 2179 <bitOffset>0</bitOffset> 2180 <bitWidth>16</bitWidth> 2181 </field> 2182 </fields> 2183 </register> 2184 <register> 2185 <name>SYS_STAT_IE</name> 2186 <description>System Status Interrupt Enable Register.</description> 2187 <addressOffset>0x54</addressOffset> 2188 <fields> 2189 <field> 2190 <name>ICEULIE</name> 2191 <description>ARM ICE Unlock Interrupt Enable.</description> 2192 <bitOffset>0</bitOffset> 2193 <bitWidth>1</bitWidth> 2194 <enumeratedValues> 2195 <enumeratedValue> 2196 <name>dis</name> 2197 <description>disabled.</description> 2198 <value>0</value> 2199 </enumeratedValue> 2200 <enumeratedValue> 2201 <name>en</name> 2202 <description>enabled.</description> 2203 <value>1</value> 2204 </enumeratedValue> 2205 </enumeratedValues> 2206 </field> 2207 <field> 2208 <name>CIEIE</name> 2209 <description>SPI-XIPF Code Intergrity Error Interrupt Enable.</description> 2210 <bitOffset>1</bitOffset> 2211 <bitWidth>1</bitWidth> 2212 <enumeratedValues> 2213 <enumeratedValue> 2214 <name>dis</name> 2215 <description>disabled.</description> 2216 <value>0</value> 2217 </enumeratedValue> 2218 <enumeratedValue> 2219 <name>en</name> 2220 <description>enabled.</description> 2221 <value>1</value> 2222 </enumeratedValue> 2223 </enumeratedValues> 2224 </field> 2225 <field> 2226 <name>SCMFIE</name> 2227 <description>HyperBus/Xccela Cache Memory Fault Interrupt Enable.</description> 2228 <bitOffset>5</bitOffset> 2229 <bitWidth>1</bitWidth> 2230 <enumeratedValues> 2231 <enumeratedValue> 2232 <name>dis</name> 2233 <description>disabled.</description> 2234 <value>0</value> 2235 </enumeratedValue> 2236 <enumeratedValue> 2237 <name>en</name> 2238 <description>enabled.</description> 2239 <value>1</value> 2240 </enumeratedValue> 2241 </enumeratedValues> 2242 </field> 2243 </fields> 2244 </register> 2245 </registers> 2246 </peripheral> 2247</device>
