1<?xml version="1.0" encoding="utf-8" standalone="no"?> 2<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <peripheral> 4 <name>GCR</name> 5 <description>Global Control Registers.</description> 6 <baseAddress>0x40000000</baseAddress> 7 <addressBlock> 8 <offset>0</offset> 9 <size>0x400</size> 10 <usage>registers</usage> 11 </addressBlock> 12 <registers> 13 <register> 14 <name>SYSCTRL</name> 15 <description>System Control.</description> 16 <addressOffset>0x00</addressOffset> 17 <resetMask>0xFFFFFFFE</resetMask> 18 <fields> 19 <field> 20 <name>BSTAPEN</name> 21 <description>Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.</description> 22 <bitOffset>0</bitOffset> 23 <bitWidth>1</bitWidth> 24 <enumeratedValues> 25 <enumeratedValue> 26 <name>dis</name> 27 <description>Boundary Scan TAP port disabled.</description> 28 <value>0</value> 29 </enumeratedValue> 30 <enumeratedValue> 31 <name>en</name> 32 <description>Boundary Scan TAP port enabled.</description> 33 <value>1</value> 34 </enumeratedValue> 35 </enumeratedValues> 36 </field> 37 <field> 38 <name>FLASH0_PAGE_FLIP</name> 39 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 40 <bitOffset>4</bitOffset> 41 <bitWidth>1</bitWidth> 42 <enumeratedValues> 43 <enumeratedValue> 44 <name>normal</name> 45 <description>Physical layout matches logical layout.</description> 46 <value>0</value> 47 </enumeratedValue> 48 <enumeratedValue> 49 <name>swapped</name> 50 <description>Bottom half mapped to logical top half and vice versa.</description> 51 <value>1</value> 52 </enumeratedValue> 53 </enumeratedValues> 54 </field> 55 <field> 56 <name>ICC0_FLUSH</name> 57 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 58 <bitOffset>6</bitOffset> 59 <bitWidth>1</bitWidth> 60 <enumeratedValues> 61 <enumeratedValue> 62 <name>normal</name> 63 <description>Normal Code Cache Operation</description> 64 <value>0</value> 65 </enumeratedValue> 66 <enumeratedValue> 67 <name>flush</name> 68 <description>Code Caches and CPU instruction buffer are flushed </description> 69 <value>1</value> 70 </enumeratedValue> 71 </enumeratedValues> 72 </field> 73 <field> 74 <name>CCHK</name> 75 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 76 <bitOffset>13</bitOffset> 77 <bitWidth>1</bitWidth> 78 <enumeratedValues> 79 <enumeratedValue> 80 <name>complete</name> 81 <description>No operation/complete.</description> 82 <value>0</value> 83 </enumeratedValue> 84 <enumeratedValue> 85 <name>start</name> 86 <description>Start operation.</description> 87 <value>1</value> 88 </enumeratedValue> 89 </enumeratedValues> 90 </field> 91 <field> 92 <name>CHKRES</name> 93 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 94 <bitOffset>15</bitOffset> 95 <bitWidth>1</bitWidth> 96 <enumeratedValues> 97 <enumeratedValue> 98 <name>pass</name> 99 <description>ROM Checksum Correct.</description> 100 <value>0</value> 101 </enumeratedValue> 102 <enumeratedValue> 103 <name>fail</name> 104 <description>ROM Checksum Fail.</description> 105 <value>1</value> 106 </enumeratedValue> 107 </enumeratedValues> 108 </field> 109 <field> 110 <name>MDU_KEYSZ</name> 111 <description>MDU Key Size. This register defines the size of AES key that is used in the memory protection logic.</description> 112 <bitOffset>21</bitOffset> 113 <bitWidth>1</bitWidth> 114 <enumeratedValues> 115 <enumeratedValue> 116 <name>128b</name> 117 <description>128 bit key</description> 118 <value>0</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>256b</name> 122 <description>256 bit key</description> 123 <value>1</value> 124 </enumeratedValue> 125 </enumeratedValues> 126 </field> 127 </fields> 128 </register> 129 <register> 130 <name>RST0</name> 131 <description>Reset.</description> 132 <addressOffset>0x04</addressOffset> 133 <fields> 134 <field> 135 <name>DMA</name> 136 <description>DMA Reset.</description> 137 <bitOffset>0</bitOffset> 138 <bitWidth>1</bitWidth> 139 </field> 140 <field derivedFrom="DMA"> 141 <name>WDT0</name> 142 <description>Watchdog Timer Reset.</description> 143 <bitOffset>1</bitOffset> 144 <bitWidth>1</bitWidth> 145 </field> 146 <field derivedFrom="DMA"> 147 <name>GPIO0</name> 148 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 149 <bitOffset>2</bitOffset> 150 <bitWidth>1</bitWidth> 151 </field> 152 <field derivedFrom="DMA"> 153 <name>GPIO1</name> 154 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 155 <bitOffset>3</bitOffset> 156 <bitWidth>1</bitWidth> 157 </field> 158 <field derivedFrom="DMA"> 159 <name>TMR0</name> 160 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 161 <bitOffset>5</bitOffset> 162 <bitWidth>1</bitWidth> 163 </field> 164 <field derivedFrom="DMA"> 165 <name>TMR1</name> 166 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 167 <bitOffset>6</bitOffset> 168 <bitWidth>1</bitWidth> 169 </field> 170 <field derivedFrom="DMA"> 171 <name>TMR2</name> 172 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 173 <bitOffset>7</bitOffset> 174 <bitWidth>1</bitWidth> 175 </field> 176 <field derivedFrom="DMA"> 177 <name>TMR3</name> 178 <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 179 <bitOffset>8</bitOffset> 180 <bitWidth>1</bitWidth> 181 </field> 182 <field derivedFrom="DMA"> 183 <name>UART0</name> 184 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 185 <bitOffset>11</bitOffset> 186 <bitWidth>1</bitWidth> 187 </field> 188 <field derivedFrom="DMA"> 189 <name>SPI0</name> 190 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 191 <bitOffset>13</bitOffset> 192 <bitWidth>1</bitWidth> 193 </field> 194 <field derivedFrom="DMA"> 195 <name>SPI1</name> 196 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 197 <bitOffset>14</bitOffset> 198 <bitWidth>1</bitWidth> 199 </field> 200 <field derivedFrom="DMA"> 201 <name>I2C0</name> 202 <description>I2C0 Reset.</description> 203 <bitOffset>16</bitOffset> 204 <bitWidth>1</bitWidth> 205 </field> 206 <field derivedFrom="DMA"> 207 <name>CRYPTO</name> 208 <description>Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.</description> 209 <bitOffset>18</bitOffset> 210 <bitWidth>1</bitWidth> 211 </field> 212 <field derivedFrom="DMA"> 213 <name>SOFT</name> 214 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 215 <bitOffset>29</bitOffset> 216 <bitWidth>1</bitWidth> 217 </field> 218 <field derivedFrom="DMA"> 219 <name>PERIPH</name> 220 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 221 <bitOffset>30</bitOffset> 222 <bitWidth>1</bitWidth> 223 </field> 224 <field derivedFrom="DMA"> 225 <name>SYS</name> 226 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 227 <bitOffset>31</bitOffset> 228 <bitWidth>1</bitWidth> 229 </field> 230 </fields> 231 </register> 232 <register> 233 <name>CLKCTRL</name> 234 <description>Clock Control.</description> 235 <addressOffset>0x08</addressOffset> 236 <resetValue>0x00000008</resetValue> 237 <fields> 238 <field> 239 <name>SYSCLK_DIV</name> 240 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 241 <bitOffset>6</bitOffset> 242 <bitWidth>3</bitWidth> 243 <enumeratedValues> 244 <enumeratedValue> 245 <name>div1</name> 246 <description>Divide by 1.</description> 247 <value>0</value> 248 </enumeratedValue> 249 <enumeratedValue> 250 <name>div2</name> 251 <description>Divide by 2.</description> 252 <value>1</value> 253 </enumeratedValue> 254 <enumeratedValue> 255 <name>div4</name> 256 <description>Divide by 4.</description> 257 <value>2</value> 258 </enumeratedValue> 259 <enumeratedValue> 260 <name>div8</name> 261 <description>Divide by 8.</description> 262 <value>3</value> 263 </enumeratedValue> 264 <enumeratedValue> 265 <name>div16</name> 266 <description>Divide by 16.</description> 267 <value>4</value> 268 </enumeratedValue> 269 <enumeratedValue> 270 <name>div32</name> 271 <description>Divide by 32.</description> 272 <value>5</value> 273 </enumeratedValue> 274 <enumeratedValue> 275 <name>div64</name> 276 <description>Divide by 64.</description> 277 <value>6</value> 278 </enumeratedValue> 279 <enumeratedValue> 280 <name>div128</name> 281 <description>Divide by 128.</description> 282 <value>7</value> 283 </enumeratedValue> 284 </enumeratedValues> 285 </field> 286 <field> 287 <name>SYSCLK_SEL</name> 288 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 289 <bitOffset>9</bitOffset> 290 <bitWidth>3</bitWidth> 291 <enumeratedValues> 292 <enumeratedValue> 293 <name>IPO</name> 294 <description>Internal Primary Oscilatior Clock</description> 295 <value>0</value> 296 </enumeratedValue> 297 <enumeratedValue> 298 <name>INRO</name> 299 <description>8kHz Internal Nano Ring Oscillator is used for the system clock.</description> 300 <value>3</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>IBRO</name> 304 <description>The internal Baud Rate oscillator is used for the system clock.</description> 305 <value>5</value> 306 </enumeratedValue> 307 </enumeratedValues> 308 </field> 309 <field> 310 <name>SYSCLK_RDY</name> 311 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 312 <bitOffset>13</bitOffset> 313 <bitWidth>1</bitWidth> 314 <access>read-only</access> 315 <enumeratedValues> 316 <enumeratedValue> 317 <name>busy</name> 318 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 319 <value>0</value> 320 </enumeratedValue> 321 <enumeratedValue> 322 <name>ready</name> 323 <description>System clock running from CLKSEL clock source.</description> 324 <value>1</value> 325 </enumeratedValue> 326 </enumeratedValues> 327 </field> 328 <field> 329 <name>CCD</name> 330 <description>Cryptographic clock divider</description> 331 <bitOffset>15</bitOffset> 332 <bitWidth>1</bitWidth> 333 <access>read-only</access> 334 <enumeratedValues> 335 <enumeratedValue> 336 <name>non_div</name> 337 <description>The cryptographic accelerator clock is running in non-divided mode.</description> 338 <value>0</value> 339 </enumeratedValue> 340 <enumeratedValue> 341 <name>div</name> 342 <description>The cryptographic accelerator clock is running in divided mode.</description> 343 <value>1</value> 344 </enumeratedValue> 345 </enumeratedValues> 346 </field> 347 <field> 348 <name>IPO_EN</name> 349 <description>96MHz High Frequency Internal Reference Clock Enable.</description> 350 <bitOffset>18</bitOffset> 351 <bitWidth>1</bitWidth> 352 </field> 353 <field derivedFrom="IPO_EN"> 354 <name>IBRO_EN</name> 355 <description>8MHz High Frequency Internal Reference Clock Enable.</description> 356 <bitOffset>20</bitOffset> 357 <bitWidth>1</bitWidth> 358 </field> 359 <field> 360 <name>IBRO_VS</name> 361 <description>7.3728MHz Internal Oscillator Voltage Source Select</description> 362 <bitOffset>21</bitOffset> 363 <bitWidth>1</bitWidth> 364 </field> 365 <field > 366 <name>IPO_RDY</name> 367 <description>Internal Primary Oscillator Ready.</description> 368 <bitOffset>26</bitOffset> 369 <bitWidth>1</bitWidth> 370 </field> 371 <field derivedFrom="IPO_RDY"> 372 <name>IBRO_RDY</name> 373 <description>Internal Baud Rate Oscillator Ready.</description> 374 <bitOffset>28</bitOffset> 375 <bitWidth>1</bitWidth> 376 </field> 377 <field derivedFrom="IPO_RDY"> 378 <name>INRO_RDY</name> 379 <description>Internal Nano Ring Oscillator Low Frequency Reference Clock Ready.</description> 380 <bitOffset>29</bitOffset> 381 <bitWidth>1</bitWidth> 382 </field> 383 </fields> 384 </register> 385 <register> 386 <name>PM</name> 387 <description>Power Management.</description> 388 <addressOffset>0x0C</addressOffset> 389 <fields> 390 <field> 391 <name>MODE</name> 392 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 393 <bitOffset>0</bitOffset> 394 <bitWidth>3</bitWidth> 395 <enumeratedValues> 396 <enumeratedValue> 397 <name>active</name> 398 <description>Active Mode.</description> 399 <value>0</value> 400 </enumeratedValue> 401 <enumeratedValue> 402 <name>deepsleep</name> 403 <description>DeepSleep Mode.</description> 404 <value>2</value> 405 </enumeratedValue> 406 <enumeratedValue> 407 <name>shutdown</name> 408 <description>Shutdown Mode.</description> 409 <value>3</value> 410 </enumeratedValue> 411 <enumeratedValue> 412 <name>backup</name> 413 <description>Backup Mode.</description> 414 <value>4</value> 415 </enumeratedValue> 416 </enumeratedValues> 417 </field> 418 <field> 419 <name>GPIO_WE</name> 420 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 421 <bitOffset>4</bitOffset> 422 <bitWidth>1</bitWidth> 423 </field> 424 <field> 425 <name>IPO_PD</name> 426 <description>Internal Primary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. </description> 427 <bitOffset>15</bitOffset> 428 <bitWidth>1</bitWidth> 429 <enumeratedValues> 430 <enumeratedValue> 431 <name>active</name> 432 <description>Mode is Active.</description> 433 <value>0</value> 434 </enumeratedValue> 435 <enumeratedValue> 436 <name>deepsleep</name> 437 <description>Powered down in DEEPSLEEP.</description> 438 <value>1</value> 439 </enumeratedValue> 440 </enumeratedValues> 441 </field> 442 <field> 443 <name>IBRO_PD</name> 444 <description>Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. </description> 445 <bitOffset>17</bitOffset> 446 <bitWidth>1</bitWidth> 447 <enumeratedValues> 448 <enumeratedValue> 449 <name>active</name> 450 <description>Mode is Active.</description> 451 <value>0</value> 452 </enumeratedValue> 453 <enumeratedValue> 454 <name>deepsleep</name> 455 <description>Powered down in DEEPSLEEP.</description> 456 <value>1</value> 457 </enumeratedValue> 458 </enumeratedValues> 459 </field> 460 </fields> 461 </register> 462 <register> 463 <name>PCLKDIV</name> 464 <description>Peripheral Clock Divider.</description> 465 <addressOffset>0x18</addressOffset> 466 <resetValue>0x00000001</resetValue> 467 <fields> 468 <field> 469 <name>PCF</name> 470 <description>These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware.</description> 471 <bitOffset>0</bitOffset> 472 <bitWidth>3</bitWidth> 473 <enumeratedValues> 474 <enumeratedValue> 475 <name>96MHz</name> 476 <value>2</value> 477 </enumeratedValue> 478 <enumeratedValue> 479 <name>48MHz</name> 480 <value>3</value> 481 </enumeratedValue> 482 <enumeratedValue> 483 <name>24MHz</name> 484 <value>4</value> 485 </enumeratedValue> 486 <enumeratedValue> 487 <name>12MHz</name> 488 <value>5</value> 489 </enumeratedValue> 490 <enumeratedValue> 491 <name>6MHz</name> 492 <value>6</value> 493 </enumeratedValue> 494 <enumeratedValue> 495 <name>3MHz</name> 496 <value>7</value> 497 </enumeratedValue> 498 </enumeratedValues> 499 </field> 500 <field> 501 <name>PCFWEN</name> 502 <description>PCF Write Enable. This bit allows the PCF Register bits to be updated by Software.</description> 503 <bitOffset>3</bitOffset> 504 <bitWidth>1</bitWidth> 505 <enumeratedValues> 506 <enumeratedValue> 507 <name>blocked</name> 508 <description>Writes to PCF are blocked.</description> 509 <value>0</value> 510 </enumeratedValue> 511 <enumeratedValue> 512 <name>allowed</name> 513 <description>Writes to PCF are allowed</description> 514 <value>1</value> 515 </enumeratedValue> 516 </enumeratedValues> 517 </field> 518 <field> 519 <name>AON_CLKDIV</name> 520 <description>Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider.</description> 521 <bitOffset>14</bitOffset> 522 <bitWidth>2</bitWidth> 523 <enumeratedValues> 524 <enumeratedValue> 525 <name>div_4</name> 526 <description>PCLK divide by 4.</description> 527 <value>0</value> 528 </enumeratedValue> 529 <enumeratedValue> 530 <name>div_8</name> 531 <description>PCLK divide by 8.</description> 532 <value>1</value> 533 </enumeratedValue> 534 <enumeratedValue> 535 <name>div_16</name> 536 <description>PCLK divide by 16.</description> 537 <value>2</value> 538 </enumeratedValue> 539 <enumeratedValue> 540 <name>div_32</name> 541 <description>PCLK divide by 32.</description> 542 <value>3</value> 543 </enumeratedValue> 544 </enumeratedValues> 545 </field> 546 </fields> 547 </register> 548 <register> 549 <name>PCLKDIS0</name> 550 <description>Peripheral Clock Disable.</description> 551 <addressOffset>0x24</addressOffset> 552 <fields> 553 <field> 554 <name>GPIO0</name> 555 <description>GPIO0 Clock Disable.</description> 556 <bitOffset>0</bitOffset> 557 <bitWidth>1</bitWidth> 558 <enumeratedValues> 559 <enumeratedValue> 560 <name>en</name> 561 <description>enable it.</description> 562 <value>0</value> 563 </enumeratedValue> 564 <enumeratedValue> 565 <name>dis</name> 566 <description>disable it.</description> 567 <value>1</value> 568 </enumeratedValue> 569 </enumeratedValues> 570 </field> 571 <field derivedFrom="GPIO0"> 572 <name>GPIO1</name> 573 <description>GPIO1 Disable.</description> 574 <bitOffset>1</bitOffset> 575 <bitWidth>1</bitWidth> 576 </field> 577 <field derivedFrom="GPIO0"> 578 <name>DMA</name> 579 <description>DMA Disable.</description> 580 <bitOffset>5</bitOffset> 581 <bitWidth>1</bitWidth> 582 </field> 583 <field derivedFrom="GPIO0"> 584 <name>SPI0</name> 585 <description>SPI 0 Disable.</description> 586 <bitOffset>6</bitOffset> 587 <bitWidth>1</bitWidth> 588 </field> 589 <field derivedFrom="GPIO0"> 590 <name>SPI1</name> 591 <description>SPI 1 Disable.</description> 592 <bitOffset>7</bitOffset> 593 <bitWidth>1</bitWidth> 594 </field> 595 <field derivedFrom="GPIO0"> 596 <name>UART0</name> 597 <description>UART 0 Disable.</description> 598 <bitOffset>9</bitOffset> 599 <bitWidth>1</bitWidth> 600 </field> 601 <field derivedFrom="GPIO0"> 602 <name>I2C0</name> 603 <description>I2C 0 Disable.</description> 604 <bitOffset>13</bitOffset> 605 <bitWidth>1</bitWidth> 606 </field> 607 <field derivedFrom="GPIO0"> 608 <name>CRYPTO</name> 609 <description>Crypto Disable.</description> 610 <bitOffset>14</bitOffset> 611 <bitWidth>1</bitWidth> 612 </field> 613 <field derivedFrom="GPIO0"> 614 <name>TMR0</name> 615 <description>Timer 0 Disable.</description> 616 <bitOffset>15</bitOffset> 617 <bitWidth>1</bitWidth> 618 </field> 619 <field derivedFrom="GPIO0"> 620 <name>TMR1</name> 621 <description>Timer 1 Disable.</description> 622 <bitOffset>16</bitOffset> 623 <bitWidth>1</bitWidth> 624 </field> 625 <field derivedFrom="GPIO0"> 626 <name>TMR2</name> 627 <description>Timer 2 Disable.</description> 628 <bitOffset>17</bitOffset> 629 <bitWidth>1</bitWidth> 630 </field> 631 <field derivedFrom="GPIO0"> 632 <name>TMR3</name> 633 <description>Timer 3 Disable.</description> 634 <bitOffset>18</bitOffset> 635 <bitWidth>1</bitWidth> 636 </field> 637 </fields> 638 </register> 639 <register> 640 <name>MEMCTRL</name> 641 <description>Memory Clock Control Register.</description> 642 <addressOffset>0x28</addressOffset> 643 <fields> 644 <field> 645 <name>FWS</name> 646 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 647 <bitOffset>0</bitOffset> 648 <bitWidth>3</bitWidth> 649 </field> 650 <field> 651 <name>RAMWS_EN</name> 652 <description>SRAM Wait State Enable</description> 653 <bitOffset>4</bitOffset> 654 <bitWidth>1</bitWidth> 655 </field> 656 <field> 657 <name>RAM0LS_EN</name> 658 <description>System RAM 0 Light Sleep Mode.</description> 659 <bitOffset>16</bitOffset> 660 <bitWidth>1</bitWidth> 661 <enumeratedValues> 662 <enumeratedValue> 663 <name>active</name> 664 <description>RAM is active.</description> 665 <value>0</value> 666 </enumeratedValue> 667 <enumeratedValue> 668 <name>light_sleep</name> 669 <description>RAM is in Light Sleep mode.</description> 670 <value>1</value> 671 </enumeratedValue> 672 </enumeratedValues> 673 </field> 674 <field derivedFrom="RAM0LS_EN"> 675 <name>RAM1LS_EN</name> 676 <description>System RAM 1 Light Sleep Mode.</description> 677 <bitOffset>17</bitOffset> 678 <bitWidth>1</bitWidth> 679 </field> 680 <field derivedFrom="RAM0LS_EN"> 681 <name>RAM2LS_EN</name> 682 <description>System RAM 2 Light Sleep Mode.</description> 683 <bitOffset>18</bitOffset> 684 <bitWidth>1</bitWidth> 685 </field> 686 <field derivedFrom="RAM0LS_EN"> 687 <name>RAM3LS_EN</name> 688 <description>System RAM 3 Light Sleep Mode.</description> 689 <bitOffset>19</bitOffset> 690 <bitWidth>1</bitWidth> 691 </field> 692 <field derivedFrom="RAM0LS_EN"> 693 <name>RAM4LS_EN</name> 694 <description>System RAM 4 Light Sleep Mode.</description> 695 <bitOffset>20</bitOffset> 696 <bitWidth>1</bitWidth> 697 </field> 698 <field derivedFrom="RAM0LS_EN"> 699 <name>ICC0LS_EN</name> 700 <description>ICache RAM Light Sleep Mode.</description> 701 <bitOffset>24</bitOffset> 702 <bitWidth>1</bitWidth> 703 </field> 704 <field derivedFrom="RAM0LS_EN"> 705 <name>ROMLS_EN</name> 706 <description>ROM Light Sleep Mode.</description> 707 <bitOffset>29</bitOffset> 708 <bitWidth>1</bitWidth> 709 </field> 710 </fields> 711 </register> 712 <register> 713 <name>MEMZ</name> 714 <description>Memory Zeroize Control.</description> 715 <addressOffset>0x2C</addressOffset> 716 <fields> 717 <field> 718 <name>RAM0</name> 719 <description>System RAM Block 0.</description> 720 <bitOffset>0</bitOffset> 721 <bitWidth>1</bitWidth> 722 <enumeratedValues> 723 <enumeratedValue> 724 <name>nop</name> 725 <description>No operation/complete.</description> 726 <value>0</value> 727 </enumeratedValue> 728 <enumeratedValue> 729 <name>start</name> 730 <description>Start operation.</description> 731 <value>1</value> 732 </enumeratedValue> 733 </enumeratedValues> 734 </field> 735 <field derivedFrom="RAM0"> 736 <name>RAM1</name> 737 <description>System RAM Block 1.</description> 738 <bitOffset>1</bitOffset> 739 <bitWidth>1</bitWidth> 740 </field> 741 <field derivedFrom="RAM0"> 742 <name>RAM2</name> 743 <description>System RAM Block 2.</description> 744 <bitOffset>2</bitOffset> 745 <bitWidth>1</bitWidth> 746 </field> 747 <field derivedFrom="RAM0"> 748 <name>RAM3</name> 749 <description>System RAM Block 3.</description> 750 <bitOffset>3</bitOffset> 751 <bitWidth>1</bitWidth> 752 </field> 753 <field derivedFrom="RAM0"> 754 <name>RAM4</name> 755 <description>System RAM Block 4.</description> 756 <bitOffset>4</bitOffset> 757 <bitWidth>1</bitWidth> 758 </field> 759 <field derivedFrom="RAM0"> 760 <name>ICC0</name> 761 <description>Instruction Cache.</description> 762 <bitOffset>8</bitOffset> 763 <bitWidth>1</bitWidth> 764 </field> 765 </fields> 766 </register> 767 <register> 768 <name>SYSST</name> 769 <description>System Status Register.</description> 770 <addressOffset>0x40</addressOffset> 771 <fields> 772 <field> 773 <name>ICELOCK</name> 774 <description>ARM ICE Lock Status.</description> 775 <bitOffset>0</bitOffset> 776 <bitWidth>1</bitWidth> 777 <enumeratedValues> 778 <enumeratedValue> 779 <name>unlocked</name> 780 <description>ICE is unlocked.</description> 781 <value>0</value> 782 </enumeratedValue> 783 <enumeratedValue> 784 <name>locked</name> 785 <description>ICE is locked.</description> 786 <value>1</value> 787 </enumeratedValue> 788 </enumeratedValues> 789 </field> 790 </fields> 791 </register> 792 <register> 793 <name>RST1</name> 794 <description>Reset 1.</description> 795 <addressOffset>0x44</addressOffset> 796 <fields> 797 <field > 798 <name>WDT1</name> 799 <description>WDT1 Reset.</description> 800 <bitOffset>8</bitOffset> 801 <bitWidth>1</bitWidth> 802 </field> 803 <field derivedFrom="WDT1"> 804 <name>SFES</name> 805 <description>Serial Flash Emulation Slave Reset.</description> 806 <bitOffset>28</bitOffset> 807 <bitWidth>1</bitWidth> 808 </field> 809 </fields> 810 </register> 811 <register> 812 <name>PCLKDIS1</name> 813 <description>Peripheral Clock Disable.</description> 814 <addressOffset>0x48</addressOffset> 815 <fields> 816 <field > 817 <name>TRNG</name> 818 <description>TRNG Disable.</description> 819 <bitOffset>2</bitOffset> 820 <bitWidth>1</bitWidth> 821 </field> 822 <field derivedFrom="TRNG"> 823 <name>WDT0</name> 824 <description>WDT0 Clock Disable</description> 825 <bitOffset>27</bitOffset> 826 <bitWidth>1</bitWidth> 827 </field> 828 <field derivedFrom="TRNG"> 829 <name>WDT1</name> 830 <description>WDT1 Clock Disable</description> 831 <bitOffset>28</bitOffset> 832 <bitWidth>1</bitWidth> 833 </field> 834 <field derivedFrom="TRNG"> 835 <name>SFES</name> 836 <description>Serial Flash emulation slave Clock Disable</description> 837 <bitOffset>30</bitOffset> 838 <bitWidth>1</bitWidth> 839 </field> 840 </fields> 841 </register> 842 <register> 843 <name>EVENTEN</name> 844 <description>Event Enable Register.</description> 845 <addressOffset>0x4C</addressOffset> 846 <fields> 847 <field> 848 <name>DMA</name> 849 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 850 <bitOffset>0</bitOffset> 851 <bitWidth>1</bitWidth> 852 </field> 853 <field> 854 <name>RX</name> 855 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 856 <bitOffset>1</bitOffset> 857 <bitWidth>1</bitWidth> 858 </field> 859 <field> 860 <name>TX</name> 861 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].</description> 862 <bitOffset>2</bitOffset> 863 <bitWidth>1</bitWidth> 864 </field> 865 </fields> 866 </register> 867 <register> 868 <name>REVISION</name> 869 <description>Revision Register.</description> 870 <addressOffset>0x50</addressOffset> 871 <access>read-only</access> 872 <fields> 873 <field> 874 <name>REVISION</name> 875 <description>Manufacturer Chip Revision. </description> 876 <bitOffset>0</bitOffset> 877 <bitWidth>16</bitWidth> 878 </field> 879 </fields> 880 </register> 881 <register> 882 <name>SYSIE</name> 883 <description>System Status Interrupt Enable Register.</description> 884 <addressOffset>0x54</addressOffset> 885 <fields> 886 <field> 887 <name>ICEUNLOCK</name> 888 <description>ARM ICE Unlock Interrupt Enable.</description> 889 <bitOffset>0</bitOffset> 890 <bitWidth>1</bitWidth> 891 <enumeratedValues> 892 <enumeratedValue> 893 <name>dis</name> 894 <description>disabled.</description> 895 <value>0</value> 896 </enumeratedValue> 897 <enumeratedValue> 898 <name>en</name> 899 <description>enabled.</description> 900 <value>1</value> 901 </enumeratedValue> 902 </enumeratedValues> 903 </field> 904 </fields> 905 </register> 906 <register> 907 <name>ECCERR</name> 908 <description>ECC Error Register</description> 909 <addressOffset>0x64</addressOffset> 910 <fields> 911 <field> 912 <name>RAM0</name> 913 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 914 <bitOffset>0</bitOffset> 915 <bitWidth>1</bitWidth> 916 </field> 917 <field> 918 <name>RAM1</name> 919 <description>ECC System RAM1 Error Flag. Write 1 to clear.</description> 920 <bitOffset>1</bitOffset> 921 <bitWidth>1</bitWidth> 922 </field> 923 <field> 924 <name>RAM2</name> 925 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 926 <bitOffset>2</bitOffset> 927 <bitWidth>1</bitWidth> 928 </field> 929 <field> 930 <name>RAM3</name> 931 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 932 <bitOffset>3</bitOffset> 933 <bitWidth>1</bitWidth> 934 </field> 935 <field> 936 <name>RAM4</name> 937 <description>ECC System RAM4 Error Flag. Write 1 to clear.</description> 938 <bitOffset>4</bitOffset> 939 <bitWidth>1</bitWidth> 940 </field> 941 </fields> 942 </register> 943 <register> 944 <name>ECCCED</name> 945 <description>ECC Not Double Error Detect Register</description> 946 <addressOffset>0x68</addressOffset> 947 <fields> 948 <field> 949 <name>RAM0</name> 950 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 951 <bitOffset>0</bitOffset> 952 <bitWidth>1</bitWidth> 953 </field> 954 <field> 955 <name>RAM1</name> 956 <description>ECC System RAM1 Not Double Error Detect. Write 1 to clear.</description> 957 <bitOffset>1</bitOffset> 958 <bitWidth>1</bitWidth> 959 </field> 960 <field> 961 <name>RAM2</name> 962 <description>ECC System RAM2 Not Double Error Detect. Write 1 to clear.</description> 963 <bitOffset>2</bitOffset> 964 <bitWidth>1</bitWidth> 965 </field> 966 <field> 967 <name>RAM3</name> 968 <description>ECC System RAM3 Not Double Error Detect. Write 1 to clear.</description> 969 <bitOffset>3</bitOffset> 970 <bitWidth>1</bitWidth> 971 </field> 972 <field> 973 <name>RAM4</name> 974 <description>ECC System RAM4 Not Double Error Detect. Write 1 to clear.</description> 975 <bitOffset>4</bitOffset> 976 <bitWidth>1</bitWidth> 977 </field> 978 </fields> 979 </register> 980 <register> 981 <name>ECCIE</name> 982 <description>ECC IRQ Enable Register</description> 983 <addressOffset>0x6C</addressOffset> 984 <fields> 985 <field> 986 <name>RAM0</name> 987 <description>ECC System RAM0 Interrupt Enable.</description> 988 <bitOffset>0</bitOffset> 989 <bitWidth>1</bitWidth> 990 </field> 991 <field> 992 <name>RAM1</name> 993 <description>ECC System RAM1 Interrupt Enable.</description> 994 <bitOffset>1</bitOffset> 995 <bitWidth>1</bitWidth> 996 </field> 997 <field> 998 <name>RAM2</name> 999 <description>ECC System RAM2 Interrupt Enable.</description> 1000 <bitOffset>2</bitOffset> 1001 <bitWidth>1</bitWidth> 1002 </field> 1003 <field> 1004 <name>RAM3</name> 1005 <description>ECC System RAM3 Interrupt Enable.</description> 1006 <bitOffset>3</bitOffset> 1007 <bitWidth>1</bitWidth> 1008 </field> 1009 <field> 1010 <name>RAM4</name> 1011 <description>ECC System RAM4 Interrupt Enable.</description> 1012 <bitOffset>4</bitOffset> 1013 <bitWidth>1</bitWidth> 1014 </field> 1015 </fields> 1016 </register> 1017 <register> 1018 <name>ECCADDR</name> 1019 <description>ECC Error Address Register</description> 1020 <addressOffset>0x70</addressOffset> 1021 <fields> 1022 <field> 1023 <name>DATARAMADDR</name> 1024 <description>ECC Error Address/DATA RAM Error Address</description> 1025 <bitOffset>0</bitOffset> 1026 <bitWidth>14</bitWidth> 1027 </field> 1028 <field> 1029 <name>DATARAMBANK</name> 1030 <description>ECC Error Address/DATA RAM Error Bank</description> 1031 <bitOffset>14</bitOffset> 1032 <bitWidth>1</bitWidth> 1033 </field> 1034 <field> 1035 <name>DATARAMERR</name> 1036 <description>DATA RAM ERROR</description> 1037 <bitOffset>15</bitOffset> 1038 <bitWidth>1</bitWidth> 1039 </field> 1040 <field> 1041 <name>TAGRAMADDR</name> 1042 <description>ECC Error Address/TAG RAM Error Address</description> 1043 <bitOffset>16</bitOffset> 1044 <bitWidth>14</bitWidth> 1045 </field> 1046 <field> 1047 <name>TAGRAMBANK</name> 1048 <description>ECC Error Address/TAG RAM Error Bank</description> 1049 <bitOffset>30</bitOffset> 1050 <bitWidth>1</bitWidth> 1051 </field> 1052 <field> 1053 <name>TAGRAMERR</name> 1054 <description>TAG RAM ERROR</description> 1055 <bitOffset>31</bitOffset> 1056 <bitWidth>1</bitWidth> 1057 </field> 1058 </fields> 1059 </register> 1060 </registers> 1061 </peripheral> 1062</device> 1063
