1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 /* **** Includes **** */
22 #include <stddef.h>
23 #include "mxc_device.h"
24 #include "mxc_assert.h"
25 #include "gpio.h"
26 #include "gpio_reva.h"
27 #include "gpio_common.h"
28 #include "mxc_sys.h"
29 #include "lpgcr_regs.h"
30 #include "mcr_regs.h"
31
32 /* **** Definitions **** */
33
34 /* **** Globals **** */
35
36 /* **** Functions **** */
MXC_GPIO_Init(uint32_t portmask)37 int MXC_GPIO_Init(uint32_t portmask)
38 {
39 if (portmask & 0x1) {
40 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
41 }
42
43 if (portmask & 0x2) {
44 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1);
45 }
46
47 return MXC_GPIO_Common_Init(portmask);
48 }
49
MXC_GPIO_Shutdown(uint32_t portmask)50 int MXC_GPIO_Shutdown(uint32_t portmask)
51 {
52 if (portmask & 0x1) {
53 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0);
54 }
55
56 if (portmask & 0x2) {
57 MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1);
58 }
59
60 return E_NO_ERROR;
61 }
62
MXC_GPIO_Reset(uint32_t portmask)63 int MXC_GPIO_Reset(uint32_t portmask)
64 {
65 if (portmask & 0x1) {
66 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0);
67 }
68
69 if (portmask & 0x2) {
70 MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1);
71 }
72
73 return E_NO_ERROR;
74 }
75
MXC_GPIO_Config(const mxc_gpio_cfg_t * cfg)76 int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg)
77 {
78 int port, error;
79 mxc_gpio_regs_t *gpio = cfg->port;
80
81 port = MXC_GPIO_GET_IDX(cfg->port);
82
83 if (cfg->port == MXC_GPIO3) {
84 if (cfg->mask & MXC_GPIO_PIN_0) {
85 switch (cfg->func) {
86 case MXC_GPIO_FUNC_IN:
87 MXC_MCR->gpio3_ctrl &= ~(MXC_F_MCR_GPIO3_CTRL_P30_OE);
88 break;
89
90 case MXC_GPIO_FUNC_OUT:
91 MXC_MCR->gpio3_ctrl |= MXC_F_MCR_GPIO3_CTRL_P30_OE;
92 break;
93
94 default:
95 return E_NOT_SUPPORTED;
96 }
97
98 switch (cfg->pad) {
99 case MXC_GPIO_PAD_NONE:
100 MXC_MCR->gpio3_ctrl &= ~(MXC_F_MCR_GPIO3_CTRL_P30_PE);
101 break;
102
103 case MXC_GPIO_PAD_PULL_UP:
104 MXC_MCR->gpio3_ctrl |= MXC_F_MCR_GPIO3_CTRL_P30_PE;
105 break;
106
107 default:
108 return E_NOT_SUPPORTED;
109 }
110 }
111
112 if (cfg->mask & MXC_GPIO_PIN_1) {
113 switch (cfg->func) {
114 case MXC_GPIO_FUNC_IN:
115 MXC_MCR->gpio3_ctrl &= ~(MXC_F_MCR_GPIO3_CTRL_P31_OE);
116 break;
117
118 case MXC_GPIO_FUNC_OUT:
119 MXC_MCR->gpio3_ctrl |= MXC_F_MCR_GPIO3_CTRL_P31_OE;
120 break;
121
122 default:
123 return E_NOT_SUPPORTED;
124 }
125
126 switch (cfg->pad) {
127 case MXC_GPIO_PAD_NONE:
128 MXC_MCR->gpio3_ctrl &= ~(MXC_F_MCR_GPIO3_CTRL_P31_PE);
129 break;
130
131 case MXC_GPIO_PAD_PULL_UP:
132 MXC_MCR->gpio3_ctrl |= MXC_F_MCR_GPIO3_CTRL_P31_PE;
133 break;
134
135 default:
136 return E_NOT_SUPPORTED;
137 }
138 }
139
140 return E_NO_ERROR;
141 } else {
142 MXC_GPIO_Init(1 << port);
143 }
144
145 // Configure the vssel
146 error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask);
147 if (error != E_NO_ERROR) {
148 return error;
149 }
150
151 // Configure alternate function
152 error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask);
153
154 if (error != E_NO_ERROR) {
155 return error;
156 }
157
158 // Configure the pad
159 switch (cfg->pad) {
160 case MXC_GPIO_PAD_NONE:
161 gpio->padctrl0 &= ~cfg->mask;
162 gpio->padctrl1 &= ~cfg->mask;
163 break;
164
165 case MXC_GPIO_PAD_WEAK_PULL_UP:
166 gpio->padctrl0 |= cfg->mask;
167 gpio->padctrl1 &= ~cfg->mask;
168 gpio->ps &= ~cfg->mask;
169 break;
170
171 case MXC_GPIO_PAD_PULL_UP:
172 gpio->padctrl0 |= cfg->mask;
173 gpio->padctrl1 &= ~cfg->mask;
174 gpio->ps |= cfg->mask;
175 break;
176
177 case MXC_GPIO_PAD_WEAK_PULL_DOWN:
178 gpio->padctrl0 &= ~cfg->mask;
179 gpio->padctrl1 |= cfg->mask;
180 gpio->ps &= ~cfg->mask;
181 break;
182
183 case MXC_GPIO_PAD_PULL_DOWN:
184 gpio->padctrl0 &= ~cfg->mask;
185 gpio->padctrl1 |= cfg->mask;
186 gpio->ps |= cfg->mask;
187 break;
188
189 default:
190 return E_BAD_PARAM;
191 }
192
193 // Configure the drive strength
194 if (cfg->func == MXC_GPIO_FUNC_IN) {
195 return E_NO_ERROR;
196 } else {
197 return MXC_GPIO_SetDriveStrength(gpio, cfg->drvstr, cfg->mask);
198 }
199 }
200
201 /* ************************************************************************** */
MXC_GPIO_InGet(mxc_gpio_regs_t * port,uint32_t mask)202 uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask)
203 {
204 uint32_t results;
205
206 if (port == MXC_GPIO3) {
207 if ((mask & MXC_GPIO_PIN_0) && (mask & MXC_GPIO_PIN_1)) {
208 results = 0;
209 results |= (!!(MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P30_IN) << 0);
210 results |= (!!(MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P31_IN) << 1);
211
212 return results;
213 }
214
215 if (mask & MXC_GPIO_PIN_0) {
216 return MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P30_IN;
217 }
218
219 if (mask & MXC_GPIO_PIN_1) {
220 return MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P31_IN;
221 }
222 }
223
224 return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask);
225 }
226
227 /* ************************************************************************** */
MXC_GPIO_OutSet(mxc_gpio_regs_t * port,uint32_t mask)228 void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask)
229 {
230 if (port == MXC_GPIO3) {
231 if (mask & MXC_GPIO_PIN_0) {
232 MXC_MCR->gpio3_ctrl |= MXC_F_MCR_GPIO3_CTRL_P30_DO;
233 }
234
235 if (mask & MXC_GPIO_PIN_1) {
236 MXC_MCR->gpio3_ctrl |= MXC_F_MCR_GPIO3_CTRL_P31_DO;
237 }
238
239 return;
240 }
241
242 MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask);
243 }
244
245 /* ************************************************************************** */
MXC_GPIO_OutClr(mxc_gpio_regs_t * port,uint32_t mask)246 void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask)
247 {
248 if (port == MXC_GPIO3) {
249 if (mask & MXC_GPIO_PIN_0) {
250 MXC_MCR->gpio3_ctrl &= ~(MXC_F_MCR_GPIO3_CTRL_P30_DO);
251 }
252
253 if (mask & MXC_GPIO_PIN_1) {
254 MXC_MCR->gpio3_ctrl &= ~(MXC_F_MCR_GPIO3_CTRL_P31_DO);
255 }
256
257 return;
258 }
259
260 MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask);
261 }
262
263 /* ************************************************************************** */
MXC_GPIO_OutGet(mxc_gpio_regs_t * port,uint32_t mask)264 uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask)
265 {
266 uint32_t results;
267
268 if (port == MXC_GPIO3) {
269 if (mask & (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1)) {
270 results = 0;
271 results |= (!!(MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P30_DO) << 0);
272 results |= (!!(MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P31_DO) << 1);
273
274 return results;
275 }
276
277 if (mask & MXC_GPIO_PIN_0) {
278 return MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P30_DO;
279 }
280
281 if (mask & MXC_GPIO_PIN_1) {
282 return MXC_MCR->gpio3_ctrl & MXC_F_MCR_GPIO3_CTRL_P31_DO;
283 }
284 }
285
286 return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask);
287 }
288
289 /* ************************************************************************** */
MXC_GPIO_OutPut(mxc_gpio_regs_t * port,uint32_t mask,uint32_t val)290 void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val)
291 {
292 MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val);
293 }
294
295 /* ************************************************************************** */
MXC_GPIO_OutToggle(mxc_gpio_regs_t * port,uint32_t mask)296 void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask)
297 {
298 MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask);
299 }
300
301 /* ************************************************************************** */
MXC_GPIO_IntConfig(const mxc_gpio_cfg_t * cfg,mxc_gpio_int_pol_t pol)302 int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
303 {
304 return MXC_GPIO_RevA_IntConfig(cfg, pol);
305 }
306
307 /* ************************************************************************** */
MXC_GPIO_EnableInt(mxc_gpio_regs_t * port,uint32_t mask)308 void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask)
309 {
310 MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask);
311 }
312
313 /* ************************************************************************** */
MXC_GPIO_DisableInt(mxc_gpio_regs_t * port,uint32_t mask)314 void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask)
315 {
316 MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask);
317 }
318
319 /* ************************************************************************** */
MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t * cfg,mxc_gpio_callback_fn func,void * cbdata)320 void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata)
321 {
322 MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata);
323 }
324
325 /* ************************************************************************** */
MXC_GPIO_Handler(unsigned int port)326 void MXC_GPIO_Handler(unsigned int port)
327 {
328 MXC_GPIO_Common_Handler(port);
329 }
330
331 /* ************************************************************************** */
MXC_GPIO_ClearFlags(mxc_gpio_regs_t * port,uint32_t flags)332 void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags)
333 {
334 MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags);
335 }
336
337 /* ************************************************************************** */
MXC_GPIO_GetFlags(mxc_gpio_regs_t * port)338 uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port)
339 {
340 return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port);
341 }
342
MXC_GPIO_SetVSSEL(mxc_gpio_regs_t * port,mxc_gpio_vssel_t vssel,uint32_t mask)343 int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask)
344 {
345 return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask);
346 }
347
348 /* ************************************************************************** */
MXC_GPIO_SetWakeEn(mxc_gpio_regs_t * port,uint32_t mask)349 void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
350 {
351 MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask);
352 }
353
354 /* ************************************************************************** */
MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t * port,uint32_t mask)355 void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask)
356 {
357 MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask);
358 }
359
360 /* ************************************************************************** */
MXC_GPIO_GetWakeEn(mxc_gpio_regs_t * port)361 uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port)
362 {
363 return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port);
364 }
365
366 /* ************************************************************************** */
MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t * port,mxc_gpio_drvstr_t drvstr,uint32_t mask)367 int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask)
368 {
369 return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask);
370 }
371
