1 /** 2 * @file csi2_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CSI2_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _CSI2_REVA_REGS_H_ 27 #define _CSI2_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup csi2_reva 65 * @defgroup csi2_reva_registers CSI2_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the CSI2_REVA Peripheral Module. 67 * @details Camera Serial Interface Registers. 68 */ 69 70 /** 71 * @ingroup csi2_reva_registers 72 * Structure type to access the CSI2_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cfg_num_lanes; /**< <tt>\b 0x000:</tt> CSI2_REVA CFG_NUM_LANES Register */ 76 __IO uint32_t cfg_clk_lane_en; /**< <tt>\b 0x004:</tt> CSI2_REVA CFG_CLK_LANE_EN Register */ 77 __IO uint32_t cfg_data_lane_en; /**< <tt>\b 0x008:</tt> CSI2_REVA CFG_DATA_LANE_EN Register */ 78 __IO uint32_t cfg_flush_count; /**< <tt>\b 0x00C:</tt> CSI2_REVA CFG_FLUSH_COUNT Register */ 79 __IO uint32_t cfg_bit_err; /**< <tt>\b 0x010:</tt> CSI2_REVA CFG_BIT_ERR Register */ 80 __IO uint32_t irq_status; /**< <tt>\b 0x014:</tt> CSI2_REVA IRQ_STATUS Register */ 81 __IO uint32_t irq_enable; /**< <tt>\b 0x018:</tt> CSI2_REVA IRQ_ENABLE Register */ 82 __IO uint32_t irq_clr; /**< <tt>\b 0x01C:</tt> CSI2_REVA IRQ_CLR Register */ 83 __IO uint32_t ulps_clk_status; /**< <tt>\b 0x020:</tt> CSI2_REVA ULPS_CLK_STATUS Register */ 84 __IO uint32_t ulps_status; /**< <tt>\b 0x024:</tt> CSI2_REVA ULPS_STATUS Register */ 85 __IO uint32_t ulps_clk_mark_status; /**< <tt>\b 0x028:</tt> CSI2_REVA ULPS_CLK_MARK_STATUS Register */ 86 __IO uint32_t ulps_mark_status; /**< <tt>\b 0x02C:</tt> CSI2_REVA ULPS_MARK_STATUS Register */ 87 __IO uint32_t ppi_errsot_hs; /**< <tt>\b 0x030:</tt> CSI2_REVA PPI_ERRSOT_HS Register */ 88 __IO uint32_t ppi_errsotsync_hs; /**< <tt>\b 0x034:</tt> CSI2_REVA PPI_ERRSOTSYNC_HS Register */ 89 __IO uint32_t ppi_erresc; /**< <tt>\b 0x038:</tt> CSI2_REVA PPI_ERRESC Register */ 90 __IO uint32_t ppi_errsyncesc; /**< <tt>\b 0x03C:</tt> CSI2_REVA PPI_ERRSYNCESC Register */ 91 __IO uint32_t ppi_errcontrol; /**< <tt>\b 0x040:</tt> CSI2_REVA PPI_ERRCONTROL Register */ 92 __IO uint32_t cfg_cphy_en; /**< <tt>\b 0x044:</tt> CSI2_REVA CFG_CPHY_EN Register */ 93 __IO uint32_t cfg_ppi_16_en; /**< <tt>\b 0x048:</tt> CSI2_REVA CFG_PPI_16_EN Register */ 94 __IO uint32_t cfg_packet_interface_en; /**< <tt>\b 0x04C:</tt> CSI2_REVA CFG_PACKET_INTERFACE_EN Register */ 95 __IO uint32_t cfg_vcx_en; /**< <tt>\b 0x050:</tt> CSI2_REVA CFG_VCX_EN Register */ 96 __IO uint32_t cfg_byte_data_format; /**< <tt>\b 0x054:</tt> CSI2_REVA CFG_BYTE_DATA_FORMAT Register */ 97 __IO uint32_t cfg_disable_payload_0; /**< <tt>\b 0x058:</tt> CSI2_REVA CFG_DISABLE_PAYLOAD_0 Register */ 98 __IO uint32_t cfg_disable_payload_1; /**< <tt>\b 0x05C:</tt> CSI2_REVA CFG_DISABLE_PAYLOAD_1 Register */ 99 __R uint32_t rsv_0x60_0x7f[8]; 100 __IO uint32_t cfg_vid_ignore_vc; /**< <tt>\b 0x080:</tt> CSI2_REVA CFG_VID_IGNORE_VC Register */ 101 __IO uint32_t cfg_vid_vc; /**< <tt>\b 0x084:</tt> CSI2_REVA CFG_VID_VC Register */ 102 __IO uint32_t cfg_p_fifo_send_level; /**< <tt>\b 0x088:</tt> CSI2_REVA CFG_P_FIFO_SEND_LEVEL Register */ 103 __IO uint32_t cfg_vid_vsync; /**< <tt>\b 0x08C:</tt> CSI2_REVA CFG_VID_VSYNC Register */ 104 __IO uint32_t cfg_vid_hsync_fp; /**< <tt>\b 0x090:</tt> CSI2_REVA CFG_VID_HSYNC_FP Register */ 105 __IO uint32_t cfg_vid_hsync; /**< <tt>\b 0x094:</tt> CSI2_REVA CFG_VID_HSYNC Register */ 106 __IO uint32_t cfg_vid_hsync_bp; /**< <tt>\b 0x098:</tt> CSI2_REVA CFG_VID_HSYNC_BP Register */ 107 __R uint32_t rsv_0x9c_0x3ff[217]; 108 __IO uint32_t cfg_databus16_sel; /**< <tt>\b 0x400:</tt> CSI2_REVA CFG_DATABUS16_SEL Register */ 109 __IO uint32_t cfg_d0_swap_sel; /**< <tt>\b 0x404:</tt> CSI2_REVA CFG_D0_SWAP_SEL Register */ 110 __IO uint32_t cfg_d1_swap_sel; /**< <tt>\b 0x408:</tt> CSI2_REVA CFG_D1_SWAP_SEL Register */ 111 __IO uint32_t cfg_d2_swap_sel; /**< <tt>\b 0x40C:</tt> CSI2_REVA CFG_D2_SWAP_SEL Register */ 112 __IO uint32_t cfg_d3_swap_sel; /**< <tt>\b 0x410:</tt> CSI2_REVA CFG_D3_SWAP_SEL Register */ 113 __IO uint32_t cfg_c0_swap_sel; /**< <tt>\b 0x414:</tt> CSI2_REVA CFG_C0_SWAP_SEL Register */ 114 __IO uint32_t cfg_dpdn_swap; /**< <tt>\b 0x418:</tt> CSI2_REVA CFG_DPDN_SWAP Register */ 115 __IO uint32_t rg_cfgclk_1us_cnt; /**< <tt>\b 0x41C:</tt> CSI2_REVA RG_CFGCLK_1US_CNT Register */ 116 __IO uint32_t rg_hsrx_clk_pre_time_grp0; /**< <tt>\b 0x420:</tt> CSI2_REVA RG_HSRX_CLK_PRE_TIME_GRP0 Register */ 117 __IO uint32_t rg_hsrx_data_pre_time_grp0; /**< <tt>\b 0x424:</tt> CSI2_REVA RG_HSRX_DATA_PRE_TIME_GRP0 Register */ 118 __IO uint32_t reset_deskew; /**< <tt>\b 0x428:</tt> CSI2_REVA RESET_DESKEW Register */ 119 __IO uint32_t pma_rdy; /**< <tt>\b 0x42C:</tt> CSI2_REVA PMA_RDY Register */ 120 __IO uint32_t xcfgi_dw00; /**< <tt>\b 0x430:</tt> CSI2_REVA XCFGI_DW00 Register */ 121 __IO uint32_t xcfgi_dw01; /**< <tt>\b 0x434:</tt> CSI2_REVA XCFGI_DW01 Register */ 122 __IO uint32_t xcfgi_dw02; /**< <tt>\b 0x438:</tt> CSI2_REVA XCFGI_DW02 Register */ 123 __IO uint32_t xcfgi_dw03; /**< <tt>\b 0x43C:</tt> CSI2_REVA XCFGI_DW03 Register */ 124 __IO uint32_t xcfgi_dw04; /**< <tt>\b 0x440:</tt> CSI2_REVA XCFGI_DW04 Register */ 125 __IO uint32_t xcfgi_dw05; /**< <tt>\b 0x444:</tt> CSI2_REVA XCFGI_DW05 Register */ 126 __IO uint32_t xcfgi_dw06; /**< <tt>\b 0x448:</tt> CSI2_REVA XCFGI_DW06 Register */ 127 __IO uint32_t xcfgi_dw07; /**< <tt>\b 0x44C:</tt> CSI2_REVA XCFGI_DW07 Register */ 128 __IO uint32_t xcfgi_dw08; /**< <tt>\b 0x450:</tt> CSI2_REVA XCFGI_DW08 Register */ 129 __IO uint32_t xcfgi_dw09; /**< <tt>\b 0x454:</tt> CSI2_REVA XCFGI_DW09 Register */ 130 __IO uint32_t xcfgi_dw0a; /**< <tt>\b 0x458:</tt> CSI2_REVA XCFGI_DW0A Register */ 131 __IO uint32_t xcfgi_dw0b; /**< <tt>\b 0x45C:</tt> CSI2_REVA XCFGI_DW0B Register */ 132 __IO uint32_t xcfgi_dw0c; /**< <tt>\b 0x460:</tt> CSI2_REVA XCFGI_DW0C Register */ 133 __IO uint32_t xcfgi_dw0d; /**< <tt>\b 0x464:</tt> CSI2_REVA XCFGI_DW0D Register */ 134 __IO uint32_t gpio_mode; /**< <tt>\b 0x468:</tt> CSI2_REVA GPIO_MODE Register */ 135 __IO uint32_t gpio_dp_ie; /**< <tt>\b 0x46C:</tt> CSI2_REVA GPIO_DP_IE Register */ 136 __IO uint32_t gpio_dn_ie; /**< <tt>\b 0x470:</tt> CSI2_REVA GPIO_DN_IE Register */ 137 __IO uint32_t gpio_dp_c; /**< <tt>\b 0x474:</tt> CSI2_REVA GPIO_DP_C Register */ 138 __IO uint32_t gpio_dn_c; /**< <tt>\b 0x478:</tt> CSI2_REVA GPIO_DN_C Register */ 139 __IO uint32_t vcontrol; /**< <tt>\b 0x47C:</tt> CSI2_REVA VCONTROL Register */ 140 __IO uint32_t mpsov1; /**< <tt>\b 0x480:</tt> CSI2_REVA MPSOV1 Register */ 141 __IO uint32_t mpsov2; /**< <tt>\b 0x484:</tt> CSI2_REVA MPSOV2 Register */ 142 __IO uint32_t mpsov3; /**< <tt>\b 0x488:</tt> CSI2_REVA MPSOV3 Register */ 143 __R uint32_t rsv_0x48c; 144 __IO uint32_t rg_cdrx_dsirx_en; /**< <tt>\b 0x490:</tt> CSI2_REVA RG_CDRX_DSIRX_EN Register */ 145 __IO uint32_t rg_cdrx_l012_sublvds_en; /**< <tt>\b 0x494:</tt> CSI2_REVA RG_CDRX_L012_SUBLVDS_EN Register */ 146 __IO uint32_t rg_cdrx_l012_hsrt_ctrl; /**< <tt>\b 0x498:</tt> CSI2_REVA RG_CDRX_L012_HSRT_CTRL Register */ 147 __IO uint32_t rg_cdrx_bisths_pll_en; /**< <tt>\b 0x49C:</tt> CSI2_REVA RG_CDRX_BISTHS_PLL_EN Register */ 148 __IO uint32_t rg_cdrx_bisths_pll_pre_div2; /**< <tt>\b 0x4A0:</tt> CSI2_REVA RG_CDRX_BISTHS_PLL_PRE_DIV2 Register */ 149 __IO uint32_t rg_cdrx_bisths_pll_fbk_int; /**< <tt>\b 0x4A4:</tt> CSI2_REVA RG_CDRX_BISTHS_PLL_FBK_INT Register */ 150 __IO uint32_t dbg1_mux_sel; /**< <tt>\b 0x4A8:</tt> CSI2_REVA DBG1_MUX_SEL Register */ 151 __IO uint32_t dbg2_mux_sel; /**< <tt>\b 0x4AC:</tt> CSI2_REVA DBG2_MUX_SEL Register */ 152 __IO uint32_t dbg1_mux_dout; /**< <tt>\b 0x4B0:</tt> CSI2_REVA DBG1_MUX_DOUT Register */ 153 __IO uint32_t dbg2_mux_dout; /**< <tt>\b 0x4B4:</tt> CSI2_REVA DBG2_MUX_DOUT Register */ 154 __IO uint32_t aon_power_ready_n; /**< <tt>\b 0x4B8:</tt> CSI2_REVA AON_POWER_READY_N Register */ 155 __IO uint32_t dphy_rst_n; /**< <tt>\b 0x4BC:</tt> CSI2_REVA DPHY_RST_N Register */ 156 __IO uint32_t rxbyteclkhs_inv; /**< <tt>\b 0x4C0:</tt> CSI2_REVA RXBYTECLKHS_INV Register */ 157 __R uint32_t rsv_0x4c4_0x4ff[15]; 158 __IO uint32_t vfifo_cfg0; /**< <tt>\b 0x500:</tt> CSI2_REVA VFIFO_CFG0 Register */ 159 __IO uint32_t vfifo_cfg1; /**< <tt>\b 0x504:</tt> CSI2_REVA VFIFO_CFG1 Register */ 160 __IO uint32_t vfifo_ctrl; /**< <tt>\b 0x508:</tt> CSI2_REVA VFIFO_CTRL Register */ 161 __IO uint32_t vfifo_sts; /**< <tt>\b 0x50C:</tt> CSI2_REVA VFIFO_STS Register */ 162 __IO uint32_t vfifo_line_num; /**< <tt>\b 0x510:</tt> CSI2_REVA VFIFO_LINE_NUM Register */ 163 __IO uint32_t vfifo_pixel_num; /**< <tt>\b 0x514:</tt> CSI2_REVA VFIFO_PIXEL_NUM Register */ 164 __IO uint32_t vfifo_line_cnt; /**< <tt>\b 0x518:</tt> CSI2_REVA VFIFO_LINE_CNT Register */ 165 __IO uint32_t vfifo_pixel_cnt; /**< <tt>\b 0x51C:</tt> CSI2_REVA VFIFO_PIXEL_CNT Register */ 166 __IO uint32_t vfifo_frame_sts; /**< <tt>\b 0x520:</tt> CSI2_REVA VFIFO_FRAME_STS Register */ 167 __IO uint32_t vfifo_raw_ctrl; /**< <tt>\b 0x524:</tt> CSI2_REVA VFIFO_RAW_CTRL Register */ 168 __IO uint32_t vfifo_raw_buf0_addr; /**< <tt>\b 0x528:</tt> CSI2_REVA VFIFO_RAW_BUF0_ADDR Register */ 169 __IO uint32_t vfifo_raw_buf1_addr; /**< <tt>\b 0x52C:</tt> CSI2_REVA VFIFO_RAW_BUF1_ADDR Register */ 170 __IO uint32_t vfifo_ahbm_ctrl; /**< <tt>\b 0x530:</tt> CSI2_REVA VFIFO_AHBM_CTRL Register */ 171 __IO uint32_t vfifo_ahbm_sts; /**< <tt>\b 0x534:</tt> CSI2_REVA VFIFO_AHBM_STS Register */ 172 __IO uint32_t vfifo_ahbm_start_addr; /**< <tt>\b 0x538:</tt> CSI2_REVA VFIFO_AHBM_START_ADDR Register */ 173 __IO uint32_t vfifo_ahbm_addr_range; /**< <tt>\b 0x53C:</tt> CSI2_REVA VFIFO_AHBM_ADDR_RANGE Register */ 174 __IO uint32_t vfifo_ahbm_max_trans; /**< <tt>\b 0x540:</tt> CSI2_REVA VFIFO_AHBM_MAX_TRANS Register */ 175 __IO uint32_t vfifo_ahbm_trans_cnt; /**< <tt>\b 0x544:</tt> CSI2_REVA VFIFO_AHBM_TRANS_CNT Register */ 176 __R uint32_t rsv_0x548_0x5ff[46]; 177 __IO uint32_t rx_eint_vff_ie; /**< <tt>\b 0x600:</tt> CSI2_REVA RX_EINT_VFF_IE Register */ 178 __IO uint32_t rx_eint_vff_if; /**< <tt>\b 0x604:</tt> CSI2_REVA RX_EINT_VFF_IF Register */ 179 __IO uint32_t rx_eint_ppi_ie; /**< <tt>\b 0x608:</tt> CSI2_REVA RX_EINT_PPI_IE Register */ 180 __IO uint32_t rx_eint_ppi_if; /**< <tt>\b 0x60C:</tt> CSI2_REVA RX_EINT_PPI_IF Register */ 181 __IO uint32_t rx_eint_ctrl_ie; /**< <tt>\b 0x610:</tt> CSI2_REVA RX_EINT_CTRL_IE Register */ 182 __IO uint32_t rx_eint_ctrl_if; /**< <tt>\b 0x614:</tt> CSI2_REVA RX_EINT_CTRL_IF Register */ 183 __R uint32_t rsv_0x618_0x6ff[58]; 184 __IO uint32_t ppi_stopstate; /**< <tt>\b 0x700:</tt> CSI2_REVA PPI_STOPSTATE Register */ 185 __IO uint32_t ppi_turnaround_cfg; /**< <tt>\b 0x704:</tt> CSI2_REVA PPI_TURNAROUND_CFG Register */ 186 } mxc_csi2_reva_regs_t; 187 188 /* Register offsets for module CSI2_REVA */ 189 /** 190 * @ingroup csi2_reva_registers 191 * @defgroup CSI2_REVA_Register_Offsets Register Offsets 192 * @brief CSI2_REVA Peripheral Register Offsets from the CSI2_REVA Base Peripheral Address. 193 * @{ 194 */ 195 #define MXC_R_CSI2_REVA_CFG_NUM_LANES ((uint32_t)0x00000000UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0000</tt> */ 196 #define MXC_R_CSI2_REVA_CFG_CLK_LANE_EN ((uint32_t)0x00000004UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0004</tt> */ 197 #define MXC_R_CSI2_REVA_CFG_DATA_LANE_EN ((uint32_t)0x00000008UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0008</tt> */ 198 #define MXC_R_CSI2_REVA_CFG_FLUSH_COUNT ((uint32_t)0x0000000CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x000C</tt> */ 199 #define MXC_R_CSI2_REVA_CFG_BIT_ERR ((uint32_t)0x00000010UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0010</tt> */ 200 #define MXC_R_CSI2_REVA_IRQ_STATUS ((uint32_t)0x00000014UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0014</tt> */ 201 #define MXC_R_CSI2_REVA_IRQ_ENABLE ((uint32_t)0x00000018UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0018</tt> */ 202 #define MXC_R_CSI2_REVA_IRQ_CLR ((uint32_t)0x0000001CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x001C</tt> */ 203 #define MXC_R_CSI2_REVA_ULPS_CLK_STATUS ((uint32_t)0x00000020UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0020</tt> */ 204 #define MXC_R_CSI2_REVA_ULPS_STATUS ((uint32_t)0x00000024UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0024</tt> */ 205 #define MXC_R_CSI2_REVA_ULPS_CLK_MARK_STATUS ((uint32_t)0x00000028UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0028</tt> */ 206 #define MXC_R_CSI2_REVA_ULPS_MARK_STATUS ((uint32_t)0x0000002CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x002C</tt> */ 207 #define MXC_R_CSI2_REVA_PPI_ERRSOT_HS ((uint32_t)0x00000030UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0030</tt> */ 208 #define MXC_R_CSI2_REVA_PPI_ERRSOTSYNC_HS ((uint32_t)0x00000034UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0034</tt> */ 209 #define MXC_R_CSI2_REVA_PPI_ERRESC ((uint32_t)0x00000038UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0038</tt> */ 210 #define MXC_R_CSI2_REVA_PPI_ERRSYNCESC ((uint32_t)0x0000003CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x003C</tt> */ 211 #define MXC_R_CSI2_REVA_PPI_ERRCONTROL ((uint32_t)0x00000040UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0040</tt> */ 212 #define MXC_R_CSI2_REVA_CFG_CPHY_EN ((uint32_t)0x00000044UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0044</tt> */ 213 #define MXC_R_CSI2_REVA_CFG_PPI_16_EN ((uint32_t)0x00000048UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0048</tt> */ 214 #define MXC_R_CSI2_REVA_CFG_PACKET_INTERFACE_EN ((uint32_t)0x0000004CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x004C</tt> */ 215 #define MXC_R_CSI2_REVA_CFG_VCX_EN ((uint32_t)0x00000050UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0050</tt> */ 216 #define MXC_R_CSI2_REVA_CFG_BYTE_DATA_FORMAT ((uint32_t)0x00000054UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0054</tt> */ 217 #define MXC_R_CSI2_REVA_CFG_DISABLE_PAYLOAD_0 ((uint32_t)0x00000058UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0058</tt> */ 218 #define MXC_R_CSI2_REVA_CFG_DISABLE_PAYLOAD_1 ((uint32_t)0x0000005CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x005C</tt> */ 219 #define MXC_R_CSI2_REVA_CFG_VID_IGNORE_VC ((uint32_t)0x00000080UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0080</tt> */ 220 #define MXC_R_CSI2_REVA_CFG_VID_VC ((uint32_t)0x00000084UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0084</tt> */ 221 #define MXC_R_CSI2_REVA_CFG_P_FIFO_SEND_LEVEL ((uint32_t)0x00000088UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0088</tt> */ 222 #define MXC_R_CSI2_REVA_CFG_VID_VSYNC ((uint32_t)0x0000008CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x008C</tt> */ 223 #define MXC_R_CSI2_REVA_CFG_VID_HSYNC_FP ((uint32_t)0x00000090UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0090</tt> */ 224 #define MXC_R_CSI2_REVA_CFG_VID_HSYNC ((uint32_t)0x00000094UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0094</tt> */ 225 #define MXC_R_CSI2_REVA_CFG_VID_HSYNC_BP ((uint32_t)0x00000098UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0098</tt> */ 226 #define MXC_R_CSI2_REVA_CFG_DATABUS16_SEL ((uint32_t)0x00000400UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0400</tt> */ 227 #define MXC_R_CSI2_REVA_CFG_D0_SWAP_SEL ((uint32_t)0x00000404UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0404</tt> */ 228 #define MXC_R_CSI2_REVA_CFG_D1_SWAP_SEL ((uint32_t)0x00000408UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0408</tt> */ 229 #define MXC_R_CSI2_REVA_CFG_D2_SWAP_SEL ((uint32_t)0x0000040CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x040C</tt> */ 230 #define MXC_R_CSI2_REVA_CFG_D3_SWAP_SEL ((uint32_t)0x00000410UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0410</tt> */ 231 #define MXC_R_CSI2_REVA_CFG_C0_SWAP_SEL ((uint32_t)0x00000414UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0414</tt> */ 232 #define MXC_R_CSI2_REVA_CFG_DPDN_SWAP ((uint32_t)0x00000418UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0418</tt> */ 233 #define MXC_R_CSI2_REVA_RG_CFGCLK_1US_CNT ((uint32_t)0x0000041CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x041C</tt> */ 234 #define MXC_R_CSI2_REVA_RG_HSRX_CLK_PRE_TIME_GRP0 ((uint32_t)0x00000420UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0420</tt> */ 235 #define MXC_R_CSI2_REVA_RG_HSRX_DATA_PRE_TIME_GRP0 ((uint32_t)0x00000424UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0424</tt> */ 236 #define MXC_R_CSI2_REVA_RESET_DESKEW ((uint32_t)0x00000428UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0428</tt> */ 237 #define MXC_R_CSI2_REVA_PMA_RDY ((uint32_t)0x0000042CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x042C</tt> */ 238 #define MXC_R_CSI2_REVA_XCFGI_DW00 ((uint32_t)0x00000430UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0430</tt> */ 239 #define MXC_R_CSI2_REVA_XCFGI_DW01 ((uint32_t)0x00000434UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0434</tt> */ 240 #define MXC_R_CSI2_REVA_XCFGI_DW02 ((uint32_t)0x00000438UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0438</tt> */ 241 #define MXC_R_CSI2_REVA_XCFGI_DW03 ((uint32_t)0x0000043CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x043C</tt> */ 242 #define MXC_R_CSI2_REVA_XCFGI_DW04 ((uint32_t)0x00000440UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0440</tt> */ 243 #define MXC_R_CSI2_REVA_XCFGI_DW05 ((uint32_t)0x00000444UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0444</tt> */ 244 #define MXC_R_CSI2_REVA_XCFGI_DW06 ((uint32_t)0x00000448UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0448</tt> */ 245 #define MXC_R_CSI2_REVA_XCFGI_DW07 ((uint32_t)0x0000044CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x044C</tt> */ 246 #define MXC_R_CSI2_REVA_XCFGI_DW08 ((uint32_t)0x00000450UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0450</tt> */ 247 #define MXC_R_CSI2_REVA_XCFGI_DW09 ((uint32_t)0x00000454UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0454</tt> */ 248 #define MXC_R_CSI2_REVA_XCFGI_DW0A ((uint32_t)0x00000458UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0458</tt> */ 249 #define MXC_R_CSI2_REVA_XCFGI_DW0B ((uint32_t)0x0000045CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x045C</tt> */ 250 #define MXC_R_CSI2_REVA_XCFGI_DW0C ((uint32_t)0x00000460UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0460</tt> */ 251 #define MXC_R_CSI2_REVA_XCFGI_DW0D ((uint32_t)0x00000464UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0464</tt> */ 252 #define MXC_R_CSI2_REVA_GPIO_MODE ((uint32_t)0x00000468UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0468</tt> */ 253 #define MXC_R_CSI2_REVA_GPIO_DP_IE ((uint32_t)0x0000046CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x046C</tt> */ 254 #define MXC_R_CSI2_REVA_GPIO_DN_IE ((uint32_t)0x00000470UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0470</tt> */ 255 #define MXC_R_CSI2_REVA_GPIO_DP_C ((uint32_t)0x00000474UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0474</tt> */ 256 #define MXC_R_CSI2_REVA_GPIO_DN_C ((uint32_t)0x00000478UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0478</tt> */ 257 #define MXC_R_CSI2_REVA_VCONTROL ((uint32_t)0x0000047CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x047C</tt> */ 258 #define MXC_R_CSI2_REVA_MPSOV1 ((uint32_t)0x00000480UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0480</tt> */ 259 #define MXC_R_CSI2_REVA_MPSOV2 ((uint32_t)0x00000484UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0484</tt> */ 260 #define MXC_R_CSI2_REVA_MPSOV3 ((uint32_t)0x00000488UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0488</tt> */ 261 #define MXC_R_CSI2_REVA_RG_CDRX_DSIRX_EN ((uint32_t)0x00000490UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0490</tt> */ 262 #define MXC_R_CSI2_REVA_RG_CDRX_L012_SUBLVDS_EN ((uint32_t)0x00000494UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0494</tt> */ 263 #define MXC_R_CSI2_REVA_RG_CDRX_L012_HSRT_CTRL ((uint32_t)0x00000498UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0498</tt> */ 264 #define MXC_R_CSI2_REVA_RG_CDRX_BISTHS_PLL_EN ((uint32_t)0x0000049CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x049C</tt> */ 265 #define MXC_R_CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2 ((uint32_t)0x000004A0UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04A0</tt> */ 266 #define MXC_R_CSI2_REVA_RG_CDRX_BISTHS_PLL_FBK_INT ((uint32_t)0x000004A4UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04A4</tt> */ 267 #define MXC_R_CSI2_REVA_DBG1_MUX_SEL ((uint32_t)0x000004A8UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04A8</tt> */ 268 #define MXC_R_CSI2_REVA_DBG2_MUX_SEL ((uint32_t)0x000004ACUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04AC</tt> */ 269 #define MXC_R_CSI2_REVA_DBG1_MUX_DOUT ((uint32_t)0x000004B0UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04B0</tt> */ 270 #define MXC_R_CSI2_REVA_DBG2_MUX_DOUT ((uint32_t)0x000004B4UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04B4</tt> */ 271 #define MXC_R_CSI2_REVA_AON_POWER_READY_N ((uint32_t)0x000004B8UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04B8</tt> */ 272 #define MXC_R_CSI2_REVA_DPHY_RST_N ((uint32_t)0x000004BCUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04BC</tt> */ 273 #define MXC_R_CSI2_REVA_RXBYTECLKHS_INV ((uint32_t)0x000004C0UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x04C0</tt> */ 274 #define MXC_R_CSI2_REVA_VFIFO_CFG0 ((uint32_t)0x00000500UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0500</tt> */ 275 #define MXC_R_CSI2_REVA_VFIFO_CFG1 ((uint32_t)0x00000504UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0504</tt> */ 276 #define MXC_R_CSI2_REVA_VFIFO_CTRL ((uint32_t)0x00000508UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0508</tt> */ 277 #define MXC_R_CSI2_REVA_VFIFO_STS ((uint32_t)0x0000050CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x050C</tt> */ 278 #define MXC_R_CSI2_REVA_VFIFO_LINE_NUM ((uint32_t)0x00000510UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0510</tt> */ 279 #define MXC_R_CSI2_REVA_VFIFO_PIXEL_NUM ((uint32_t)0x00000514UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0514</tt> */ 280 #define MXC_R_CSI2_REVA_VFIFO_LINE_CNT ((uint32_t)0x00000518UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0518</tt> */ 281 #define MXC_R_CSI2_REVA_VFIFO_PIXEL_CNT ((uint32_t)0x0000051CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x051C</tt> */ 282 #define MXC_R_CSI2_REVA_VFIFO_FRAME_STS ((uint32_t)0x00000520UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0520</tt> */ 283 #define MXC_R_CSI2_REVA_VFIFO_RAW_CTRL ((uint32_t)0x00000524UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0524</tt> */ 284 #define MXC_R_CSI2_REVA_VFIFO_RAW_BUF0_ADDR ((uint32_t)0x00000528UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0528</tt> */ 285 #define MXC_R_CSI2_REVA_VFIFO_RAW_BUF1_ADDR ((uint32_t)0x0000052CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x052C</tt> */ 286 #define MXC_R_CSI2_REVA_VFIFO_AHBM_CTRL ((uint32_t)0x00000530UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0530</tt> */ 287 #define MXC_R_CSI2_REVA_VFIFO_AHBM_STS ((uint32_t)0x00000534UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0534</tt> */ 288 #define MXC_R_CSI2_REVA_VFIFO_AHBM_START_ADDR ((uint32_t)0x00000538UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0538</tt> */ 289 #define MXC_R_CSI2_REVA_VFIFO_AHBM_ADDR_RANGE ((uint32_t)0x0000053CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x053C</tt> */ 290 #define MXC_R_CSI2_REVA_VFIFO_AHBM_MAX_TRANS ((uint32_t)0x00000540UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0540</tt> */ 291 #define MXC_R_CSI2_REVA_VFIFO_AHBM_TRANS_CNT ((uint32_t)0x00000544UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0544</tt> */ 292 #define MXC_R_CSI2_REVA_RX_EINT_VFF_IE ((uint32_t)0x00000600UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0600</tt> */ 293 #define MXC_R_CSI2_REVA_RX_EINT_VFF_IF ((uint32_t)0x00000604UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0604</tt> */ 294 #define MXC_R_CSI2_REVA_RX_EINT_PPI_IE ((uint32_t)0x00000608UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0608</tt> */ 295 #define MXC_R_CSI2_REVA_RX_EINT_PPI_IF ((uint32_t)0x0000060CUL) /**< Offset from CSI2_REVA Base Address: <tt> 0x060C</tt> */ 296 #define MXC_R_CSI2_REVA_RX_EINT_CTRL_IE ((uint32_t)0x00000610UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0610</tt> */ 297 #define MXC_R_CSI2_REVA_RX_EINT_CTRL_IF ((uint32_t)0x00000614UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0614</tt> */ 298 #define MXC_R_CSI2_REVA_PPI_STOPSTATE ((uint32_t)0x00000700UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0700</tt> */ 299 #define MXC_R_CSI2_REVA_PPI_TURNAROUND_CFG ((uint32_t)0x00000704UL) /**< Offset from CSI2_REVA Base Address: <tt> 0x0704</tt> */ 300 /**@} end of group csi2_reva_registers */ 301 302 /** 303 * @ingroup csi2_reva_registers 304 * @defgroup CSI2_REVA_CFG_NUM_LANES CSI2_REVA_CFG_NUM_LANES 305 * @brief CFG_NUM_LANES. 306 * @{ 307 */ 308 #define MXC_F_CSI2_REVA_CFG_NUM_LANES_LANES_POS 0 /**< CFG_NUM_LANES_LANES Position */ 309 #define MXC_F_CSI2_REVA_CFG_NUM_LANES_LANES ((uint32_t)(0xFUL << MXC_F_CSI2_REVA_CFG_NUM_LANES_LANES_POS)) /**< CFG_NUM_LANES_LANES Mask */ 310 311 /**@} end of group CSI2_REVA_CFG_NUM_LANES_Register */ 312 313 /** 314 * @ingroup csi2_reva_registers 315 * @defgroup CSI2_REVA_CFG_CLK_LANE_EN CSI2_REVA_CFG_CLK_LANE_EN 316 * @brief CFG_CLK_LANE_EN. 317 * @{ 318 */ 319 #define MXC_F_CSI2_REVA_CFG_CLK_LANE_EN_EN_POS 0 /**< CFG_CLK_LANE_EN_EN Position */ 320 #define MXC_F_CSI2_REVA_CFG_CLK_LANE_EN_EN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_CLK_LANE_EN_EN_POS)) /**< CFG_CLK_LANE_EN_EN Mask */ 321 322 /**@} end of group CSI2_REVA_CFG_CLK_LANE_EN_Register */ 323 324 /** 325 * @ingroup csi2_reva_registers 326 * @defgroup CSI2_REVA_CFG_DATA_LANE_EN CSI2_REVA_CFG_DATA_LANE_EN 327 * @brief CFG_DATA_LANE_EN. 328 * @{ 329 */ 330 #define MXC_F_CSI2_REVA_CFG_DATA_LANE_EN_EN_POS 0 /**< CFG_DATA_LANE_EN_EN Position */ 331 #define MXC_F_CSI2_REVA_CFG_DATA_LANE_EN_EN ((uint32_t)(0xFFUL << MXC_F_CSI2_REVA_CFG_DATA_LANE_EN_EN_POS)) /**< CFG_DATA_LANE_EN_EN Mask */ 332 333 /**@} end of group CSI2_REVA_CFG_DATA_LANE_EN_Register */ 334 335 /** 336 * @ingroup csi2_reva_registers 337 * @defgroup CSI2_REVA_CFG_FLUSH_COUNT CSI2_REVA_CFG_FLUSH_COUNT 338 * @brief CFG_FLUSH_COUNT. 339 * @{ 340 */ 341 #define MXC_F_CSI2_REVA_CFG_FLUSH_COUNT_COUNT_POS 0 /**< CFG_FLUSH_COUNT_COUNT Position */ 342 #define MXC_F_CSI2_REVA_CFG_FLUSH_COUNT_COUNT ((uint32_t)(0xFUL << MXC_F_CSI2_REVA_CFG_FLUSH_COUNT_COUNT_POS)) /**< CFG_FLUSH_COUNT_COUNT Mask */ 343 344 /**@} end of group CSI2_REVA_CFG_FLUSH_COUNT_Register */ 345 346 /** 347 * @ingroup csi2_reva_registers 348 * @defgroup CSI2_REVA_CFG_BIT_ERR CSI2_REVA_CFG_BIT_ERR 349 * @brief CFG_BIT_ERR. 350 * @{ 351 */ 352 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_MBE_POS 0 /**< CFG_BIT_ERR_MBE Position */ 353 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_BIT_ERR_MBE_POS)) /**< CFG_BIT_ERR_MBE Mask */ 354 355 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_SBE_POS 1 /**< CFG_BIT_ERR_SBE Position */ 356 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_BIT_ERR_SBE_POS)) /**< CFG_BIT_ERR_SBE Mask */ 357 358 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_HEADER_POS 2 /**< CFG_BIT_ERR_HEADER Position */ 359 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_HEADER ((uint32_t)(0x1FUL << MXC_F_CSI2_REVA_CFG_BIT_ERR_HEADER_POS)) /**< CFG_BIT_ERR_HEADER Mask */ 360 361 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_CRC_POS 7 /**< CFG_BIT_ERR_CRC Position */ 362 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_BIT_ERR_CRC_POS)) /**< CFG_BIT_ERR_CRC Mask */ 363 364 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_VID_ERR_SEND_LVL_POS 8 /**< CFG_BIT_ERR_VID_ERR_SEND_LVL Position */ 365 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_BIT_ERR_VID_ERR_SEND_LVL_POS)) /**< CFG_BIT_ERR_VID_ERR_SEND_LVL Mask */ 366 367 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV_POS 9 /**< CFG_BIT_ERR_VID_ERR_FIFO_WR_OV Position */ 368 #define MXC_F_CSI2_REVA_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV_POS)) /**< CFG_BIT_ERR_VID_ERR_FIFO_WR_OV Mask */ 369 370 /**@} end of group CSI2_REVA_CFG_BIT_ERR_Register */ 371 372 /** 373 * @ingroup csi2_reva_registers 374 * @defgroup CSI2_REVA_IRQ_STATUS CSI2_REVA_IRQ_STATUS 375 * @brief IRQ_STATUS. 376 * @{ 377 */ 378 #define MXC_F_CSI2_REVA_IRQ_STATUS_CRC_POS 0 /**< IRQ_STATUS_CRC Position */ 379 #define MXC_F_CSI2_REVA_IRQ_STATUS_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_CRC_POS)) /**< IRQ_STATUS_CRC Mask */ 380 381 #define MXC_F_CSI2_REVA_IRQ_STATUS_SBE_POS 1 /**< IRQ_STATUS_SBE Position */ 382 #define MXC_F_CSI2_REVA_IRQ_STATUS_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_SBE_POS)) /**< IRQ_STATUS_SBE Mask */ 383 384 #define MXC_F_CSI2_REVA_IRQ_STATUS_MBE_POS 2 /**< IRQ_STATUS_MBE Position */ 385 #define MXC_F_CSI2_REVA_IRQ_STATUS_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_MBE_POS)) /**< IRQ_STATUS_MBE Mask */ 386 387 #define MXC_F_CSI2_REVA_IRQ_STATUS_ULPS_ACTIVE_POS 3 /**< IRQ_STATUS_ULPS_ACTIVE Position */ 388 #define MXC_F_CSI2_REVA_IRQ_STATUS_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_ULPS_ACTIVE_POS)) /**< IRQ_STATUS_ULPS_ACTIVE Mask */ 389 390 #define MXC_F_CSI2_REVA_IRQ_STATUS_ULPS_MARK_ACTIVE_POS 4 /**< IRQ_STATUS_ULPS_MARK_ACTIVE Position */ 391 #define MXC_F_CSI2_REVA_IRQ_STATUS_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_ULPS_MARK_ACTIVE_POS)) /**< IRQ_STATUS_ULPS_MARK_ACTIVE Mask */ 392 393 #define MXC_F_CSI2_REVA_IRQ_STATUS_VID_ERR_SEND_LVL_POS 5 /**< IRQ_STATUS_VID_ERR_SEND_LVL Position */ 394 #define MXC_F_CSI2_REVA_IRQ_STATUS_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_VID_ERR_SEND_LVL_POS)) /**< IRQ_STATUS_VID_ERR_SEND_LVL Mask */ 395 396 #define MXC_F_CSI2_REVA_IRQ_STATUS_VID_ERR_FIFO_WR_OV_POS 6 /**< IRQ_STATUS_VID_ERR_FIFO_WR_OV Position */ 397 #define MXC_F_CSI2_REVA_IRQ_STATUS_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_STATUS_VID_ERR_FIFO_WR_OV_POS)) /**< IRQ_STATUS_VID_ERR_FIFO_WR_OV Mask */ 398 399 /**@} end of group CSI2_REVA_IRQ_STATUS_Register */ 400 401 /** 402 * @ingroup csi2_reva_registers 403 * @defgroup CSI2_REVA_IRQ_ENABLE CSI2_REVA_IRQ_ENABLE 404 * @brief IRQ_ENABLE. 405 * @{ 406 */ 407 #define MXC_F_CSI2_REVA_IRQ_ENABLE_CRC_POS 0 /**< IRQ_ENABLE_CRC Position */ 408 #define MXC_F_CSI2_REVA_IRQ_ENABLE_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_CRC_POS)) /**< IRQ_ENABLE_CRC Mask */ 409 410 #define MXC_F_CSI2_REVA_IRQ_ENABLE_SBE_POS 1 /**< IRQ_ENABLE_SBE Position */ 411 #define MXC_F_CSI2_REVA_IRQ_ENABLE_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_SBE_POS)) /**< IRQ_ENABLE_SBE Mask */ 412 413 #define MXC_F_CSI2_REVA_IRQ_ENABLE_MBE_POS 2 /**< IRQ_ENABLE_MBE Position */ 414 #define MXC_F_CSI2_REVA_IRQ_ENABLE_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_MBE_POS)) /**< IRQ_ENABLE_MBE Mask */ 415 416 #define MXC_F_CSI2_REVA_IRQ_ENABLE_ULPS_ACTIVE_POS 3 /**< IRQ_ENABLE_ULPS_ACTIVE Position */ 417 #define MXC_F_CSI2_REVA_IRQ_ENABLE_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_ULPS_ACTIVE_POS)) /**< IRQ_ENABLE_ULPS_ACTIVE Mask */ 418 419 #define MXC_F_CSI2_REVA_IRQ_ENABLE_ULPS_MARK_ACTIVE_POS 4 /**< IRQ_ENABLE_ULPS_MARK_ACTIVE Position */ 420 #define MXC_F_CSI2_REVA_IRQ_ENABLE_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_ULPS_MARK_ACTIVE_POS)) /**< IRQ_ENABLE_ULPS_MARK_ACTIVE Mask */ 421 422 #define MXC_F_CSI2_REVA_IRQ_ENABLE_VID_ERR_SEND_LVL_POS 5 /**< IRQ_ENABLE_VID_ERR_SEND_LVL Position */ 423 #define MXC_F_CSI2_REVA_IRQ_ENABLE_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_VID_ERR_SEND_LVL_POS)) /**< IRQ_ENABLE_VID_ERR_SEND_LVL Mask */ 424 425 #define MXC_F_CSI2_REVA_IRQ_ENABLE_VID_ERR_FIFO_WR_OV_POS 6 /**< IRQ_ENABLE_VID_ERR_FIFO_WR_OV Position */ 426 #define MXC_F_CSI2_REVA_IRQ_ENABLE_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_ENABLE_VID_ERR_FIFO_WR_OV_POS)) /**< IRQ_ENABLE_VID_ERR_FIFO_WR_OV Mask */ 427 428 /**@} end of group CSI2_REVA_IRQ_ENABLE_Register */ 429 430 /** 431 * @ingroup csi2_reva_registers 432 * @defgroup CSI2_REVA_IRQ_CLR CSI2_REVA_IRQ_CLR 433 * @brief IRQ_CLR. 434 * @{ 435 */ 436 #define MXC_F_CSI2_REVA_IRQ_CLR_CRC_POS 0 /**< IRQ_CLR_CRC Position */ 437 #define MXC_F_CSI2_REVA_IRQ_CLR_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_CRC_POS)) /**< IRQ_CLR_CRC Mask */ 438 439 #define MXC_F_CSI2_REVA_IRQ_CLR_SBE_POS 1 /**< IRQ_CLR_SBE Position */ 440 #define MXC_F_CSI2_REVA_IRQ_CLR_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_SBE_POS)) /**< IRQ_CLR_SBE Mask */ 441 442 #define MXC_F_CSI2_REVA_IRQ_CLR_MBE_POS 2 /**< IRQ_CLR_MBE Position */ 443 #define MXC_F_CSI2_REVA_IRQ_CLR_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_MBE_POS)) /**< IRQ_CLR_MBE Mask */ 444 445 #define MXC_F_CSI2_REVA_IRQ_CLR_ULPS_ACTIVE_POS 3 /**< IRQ_CLR_ULPS_ACTIVE Position */ 446 #define MXC_F_CSI2_REVA_IRQ_CLR_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_ULPS_ACTIVE_POS)) /**< IRQ_CLR_ULPS_ACTIVE Mask */ 447 448 #define MXC_F_CSI2_REVA_IRQ_CLR_ULPS_MARK_ACTIVE_POS 4 /**< IRQ_CLR_ULPS_MARK_ACTIVE Position */ 449 #define MXC_F_CSI2_REVA_IRQ_CLR_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_ULPS_MARK_ACTIVE_POS)) /**< IRQ_CLR_ULPS_MARK_ACTIVE Mask */ 450 451 #define MXC_F_CSI2_REVA_IRQ_CLR_VID_ERR_SEND_LVL_POS 5 /**< IRQ_CLR_VID_ERR_SEND_LVL Position */ 452 #define MXC_F_CSI2_REVA_IRQ_CLR_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_VID_ERR_SEND_LVL_POS)) /**< IRQ_CLR_VID_ERR_SEND_LVL Mask */ 453 454 #define MXC_F_CSI2_REVA_IRQ_CLR_VID_ERR_FIFO_WR_OV_POS 6 /**< IRQ_CLR_VID_ERR_FIFO_WR_OV Position */ 455 #define MXC_F_CSI2_REVA_IRQ_CLR_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_IRQ_CLR_VID_ERR_FIFO_WR_OV_POS)) /**< IRQ_CLR_VID_ERR_FIFO_WR_OV Mask */ 456 457 /**@} end of group CSI2_REVA_IRQ_CLR_Register */ 458 459 /** 460 * @ingroup csi2_reva_registers 461 * @defgroup CSI2_REVA_ULPS_CLK_STATUS CSI2_REVA_ULPS_CLK_STATUS 462 * @brief ULPS_CLK_STATUS. 463 * @{ 464 */ 465 #define MXC_F_CSI2_REVA_ULPS_CLK_STATUS_FIFO_POS 0 /**< ULPS_CLK_STATUS_FIFO Position */ 466 #define MXC_F_CSI2_REVA_ULPS_CLK_STATUS_FIFO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_ULPS_CLK_STATUS_FIFO_POS)) /**< ULPS_CLK_STATUS_FIFO Mask */ 467 468 /**@} end of group CSI2_REVA_ULPS_CLK_STATUS_Register */ 469 470 /** 471 * @ingroup csi2_reva_registers 472 * @defgroup CSI2_REVA_ULPS_STATUS CSI2_REVA_ULPS_STATUS 473 * @brief ULPS_STATUS. 474 * @{ 475 */ 476 #define MXC_F_CSI2_REVA_ULPS_STATUS_DATA_LANE0_POS 0 /**< ULPS_STATUS_DATA_LANE0 Position */ 477 #define MXC_F_CSI2_REVA_ULPS_STATUS_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_ULPS_STATUS_DATA_LANE0_POS)) /**< ULPS_STATUS_DATA_LANE0 Mask */ 478 479 #define MXC_F_CSI2_REVA_ULPS_STATUS_DATA_LANE1_POS 1 /**< ULPS_STATUS_DATA_LANE1 Position */ 480 #define MXC_F_CSI2_REVA_ULPS_STATUS_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_ULPS_STATUS_DATA_LANE1_POS)) /**< ULPS_STATUS_DATA_LANE1 Mask */ 481 482 /**@} end of group CSI2_REVA_ULPS_STATUS_Register */ 483 484 /** 485 * @ingroup csi2_reva_registers 486 * @defgroup CSI2_REVA_ULPS_CLK_MARK_STATUS CSI2_REVA_ULPS_CLK_MARK_STATUS 487 * @brief ULPS_CLK_MARK_STATUS. 488 * @{ 489 */ 490 #define MXC_F_CSI2_REVA_ULPS_CLK_MARK_STATUS_CLK_LANE_POS 0 /**< ULPS_CLK_MARK_STATUS_CLK_LANE Position */ 491 #define MXC_F_CSI2_REVA_ULPS_CLK_MARK_STATUS_CLK_LANE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_ULPS_CLK_MARK_STATUS_CLK_LANE_POS)) /**< ULPS_CLK_MARK_STATUS_CLK_LANE Mask */ 492 493 /**@} end of group CSI2_REVA_ULPS_CLK_MARK_STATUS_Register */ 494 495 /** 496 * @ingroup csi2_reva_registers 497 * @defgroup CSI2_REVA_ULPS_MARK_STATUS CSI2_REVA_ULPS_MARK_STATUS 498 * @brief ULPS_MARK_STATUS. 499 * @{ 500 */ 501 #define MXC_F_CSI2_REVA_ULPS_MARK_STATUS_DATA_LANE0_POS 0 /**< ULPS_MARK_STATUS_DATA_LANE0 Position */ 502 #define MXC_F_CSI2_REVA_ULPS_MARK_STATUS_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_ULPS_MARK_STATUS_DATA_LANE0_POS)) /**< ULPS_MARK_STATUS_DATA_LANE0 Mask */ 503 504 #define MXC_F_CSI2_REVA_ULPS_MARK_STATUS_DATA_LANE1_POS 1 /**< ULPS_MARK_STATUS_DATA_LANE1 Position */ 505 #define MXC_F_CSI2_REVA_ULPS_MARK_STATUS_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_ULPS_MARK_STATUS_DATA_LANE1_POS)) /**< ULPS_MARK_STATUS_DATA_LANE1 Mask */ 506 507 /**@} end of group CSI2_REVA_ULPS_MARK_STATUS_Register */ 508 509 /** 510 * @ingroup csi2_reva_registers 511 * @defgroup CSI2_REVA_CFG_DISABLE_PAYLOAD_0 CSI2_REVA_CFG_DISABLE_PAYLOAD_0 512 * @brief CFG_DISABLE_PAYLOAD_0. 513 * @{ 514 */ 515 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_NULL_POS 0 /**< CFG_DISABLE_PAYLOAD_0_NULL Position */ 516 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_NULL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_NULL_POS)) /**< CFG_DISABLE_PAYLOAD_0_NULL Mask */ 517 518 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_BLANK_POS 1 /**< CFG_DISABLE_PAYLOAD_0_BLANK Position */ 519 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_BLANK ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_BLANK_POS)) /**< CFG_DISABLE_PAYLOAD_0_BLANK Mask */ 520 521 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_EMBEDDED_POS 2 /**< CFG_DISABLE_PAYLOAD_0_EMBEDDED Position */ 522 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_EMBEDDED ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_EMBEDDED_POS)) /**< CFG_DISABLE_PAYLOAD_0_EMBEDDED Mask */ 523 524 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_POS 8 /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT Position */ 525 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT Mask */ 526 527 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_POS 9 /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT Position */ 528 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT Mask */ 529 530 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG_POS 10 /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG Position */ 531 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG Mask */ 532 533 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP_POS 12 /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP Position */ 534 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP Mask */ 535 536 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP_POS 13 /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP Position */ 537 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP Mask */ 538 539 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT_POS 14 /**< CFG_DISABLE_PAYLOAD_0_YUV422_8BIT Position */ 540 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV422_8BIT Mask */ 541 542 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT_POS 15 /**< CFG_DISABLE_PAYLOAD_0_YUV422_10BIT Position */ 543 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV422_10BIT Mask */ 544 545 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB444_POS 16 /**< CFG_DISABLE_PAYLOAD_0_RGB444 Position */ 546 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB444 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB444_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB444 Mask */ 547 548 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB555_POS 17 /**< CFG_DISABLE_PAYLOAD_0_RGB555 Position */ 549 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB555 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB555_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB555 Mask */ 550 551 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB565_POS 18 /**< CFG_DISABLE_PAYLOAD_0_RGB565 Position */ 552 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB565 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB565_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB565 Mask */ 553 554 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB666_POS 19 /**< CFG_DISABLE_PAYLOAD_0_RGB666 Position */ 555 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB666 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB666_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB666 Mask */ 556 557 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB888_POS 20 /**< CFG_DISABLE_PAYLOAD_0_RGB888 Position */ 558 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB888 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RGB888_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB888 Mask */ 559 560 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW6_POS 24 /**< CFG_DISABLE_PAYLOAD_0_RAW6 Position */ 561 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW6 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW6_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW6 Mask */ 562 563 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW7_POS 25 /**< CFG_DISABLE_PAYLOAD_0_RAW7 Position */ 564 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW7 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW7_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW7 Mask */ 565 566 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW8_POS 26 /**< CFG_DISABLE_PAYLOAD_0_RAW8 Position */ 567 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW8 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW8_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW8 Mask */ 568 569 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW10_POS 27 /**< CFG_DISABLE_PAYLOAD_0_RAW10 Position */ 570 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW10 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW10_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW10 Mask */ 571 572 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW12_POS 28 /**< CFG_DISABLE_PAYLOAD_0_RAW12 Position */ 573 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW12 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW12_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW12 Mask */ 574 575 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW14_POS 29 /**< CFG_DISABLE_PAYLOAD_0_RAW14 Position */ 576 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW14 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW14_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW14 Mask */ 577 578 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW16_POS 30 /**< CFG_DISABLE_PAYLOAD_0_RAW16 Position */ 579 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW16 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW16_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW16 Mask */ 580 581 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW20_POS 31 /**< CFG_DISABLE_PAYLOAD_0_RAW20 Position */ 582 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW20 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_0_RAW20_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW20 Mask */ 583 584 /**@} end of group CSI2_REVA_CFG_DISABLE_PAYLOAD_0_Register */ 585 586 /** 587 * @ingroup csi2_reva_registers 588 * @defgroup CSI2_REVA_CFG_DISABLE_PAYLOAD_1 CSI2_REVA_CFG_DISABLE_PAYLOAD_1 589 * @brief CFG_DISABLE_PAYLOAD_1. 590 * @{ 591 */ 592 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30_POS 0 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 Position */ 593 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 Mask */ 594 595 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31_POS 1 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 Position */ 596 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 Mask */ 597 598 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32_POS 2 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 Position */ 599 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 Mask */ 600 601 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33_POS 3 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 Position */ 602 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 Mask */ 603 604 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34_POS 4 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 Position */ 605 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 Mask */ 606 607 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35_POS 5 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 Position */ 608 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 Mask */ 609 610 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36_POS 6 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 Position */ 611 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 Mask */ 612 613 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37_POS 7 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 Position */ 614 #define MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 Mask */ 615 616 /**@} end of group CSI2_REVA_CFG_DISABLE_PAYLOAD_1_Register */ 617 618 /** 619 * @ingroup csi2_reva_registers 620 * @defgroup CSI2_REVA_CFG_DATABUS16_SEL CSI2_REVA_CFG_DATABUS16_SEL 621 * @brief CFG_DATABUS16_SEL. 622 * @{ 623 */ 624 #define MXC_F_CSI2_REVA_CFG_DATABUS16_SEL_EN_POS 0 /**< CFG_DATABUS16_SEL_EN Position */ 625 #define MXC_F_CSI2_REVA_CFG_DATABUS16_SEL_EN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DATABUS16_SEL_EN_POS)) /**< CFG_DATABUS16_SEL_EN Mask */ 626 627 /**@} end of group CSI2_REVA_CFG_DATABUS16_SEL_Register */ 628 629 /** 630 * @ingroup csi2_reva_registers 631 * @defgroup CSI2_REVA_CFG_D0_SWAP_SEL CSI2_REVA_CFG_D0_SWAP_SEL 632 * @brief CFG_D0_SWAP_SEL. 633 * @{ 634 */ 635 #define MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS 0 /**< CFG_D0_SWAP_SEL_SRC Position */ 636 #define MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS)) /**< CFG_D0_SWAP_SEL_SRC Mask */ 637 #define MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 638 #define MXC_S_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 639 #define MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 640 #define MXC_S_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 641 #define MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 642 #define MXC_S_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 643 #define MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 644 #define MXC_S_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 645 #define MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 646 #define MXC_S_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_REVA_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 647 648 /**@} end of group CSI2_REVA_CFG_D0_SWAP_SEL_Register */ 649 650 /** 651 * @ingroup csi2_reva_registers 652 * @defgroup CSI2_REVA_CFG_D1_SWAP_SEL CSI2_REVA_CFG_D1_SWAP_SEL 653 * @brief CFG_D1_SWAP_SEL. 654 * @{ 655 */ 656 #define MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS 0 /**< CFG_D1_SWAP_SEL_SRC Position */ 657 #define MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS)) /**< CFG_D1_SWAP_SEL_SRC Mask */ 658 #define MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 659 #define MXC_S_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 660 #define MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 661 #define MXC_S_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 662 #define MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 663 #define MXC_S_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 664 #define MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 665 #define MXC_S_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 666 #define MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 667 #define MXC_S_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_REVA_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 668 669 /**@} end of group CSI2_REVA_CFG_D1_SWAP_SEL_Register */ 670 671 /** 672 * @ingroup csi2_reva_registers 673 * @defgroup CSI2_REVA_CFG_D2_SWAP_SEL CSI2_REVA_CFG_D2_SWAP_SEL 674 * @brief CFG_D2_SWAP_SEL. 675 * @{ 676 */ 677 #define MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS 0 /**< CFG_D2_SWAP_SEL_SRC Position */ 678 #define MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS)) /**< CFG_D2_SWAP_SEL_SRC Mask */ 679 #define MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 680 #define MXC_S_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 681 #define MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 682 #define MXC_S_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 683 #define MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 684 #define MXC_S_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 685 #define MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 686 #define MXC_S_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 687 #define MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 688 #define MXC_S_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_REVA_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 689 690 /**@} end of group CSI2_REVA_CFG_D2_SWAP_SEL_Register */ 691 692 /** 693 * @ingroup csi2_reva_registers 694 * @defgroup CSI2_REVA_CFG_D3_SWAP_SEL CSI2_REVA_CFG_D3_SWAP_SEL 695 * @brief CFG_D3_SWAP_SEL. 696 * @{ 697 */ 698 #define MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS 0 /**< CFG_D3_SWAP_SEL_SRC Position */ 699 #define MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS)) /**< CFG_D3_SWAP_SEL_SRC Mask */ 700 #define MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 701 #define MXC_S_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 702 #define MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 703 #define MXC_S_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 704 #define MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 705 #define MXC_S_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 706 #define MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 707 #define MXC_S_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 708 #define MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 709 #define MXC_S_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_REVA_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 710 711 /**@} end of group CSI2_REVA_CFG_D3_SWAP_SEL_Register */ 712 713 /** 714 * @ingroup csi2_reva_registers 715 * @defgroup CSI2_REVA_CFG_C0_SWAP_SEL CSI2_REVA_CFG_C0_SWAP_SEL 716 * @brief CFG_C0_SWAP_SEL. 717 * @{ 718 */ 719 #define MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS 0 /**< CFG_C0_SWAP_SEL_SRC Position */ 720 #define MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS)) /**< CFG_C0_SWAP_SEL_SRC Mask */ 721 #define MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 722 #define MXC_S_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 723 #define MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 724 #define MXC_S_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 725 #define MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 726 #define MXC_S_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 727 #define MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 728 #define MXC_S_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 729 #define MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 730 #define MXC_S_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_REVA_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 731 732 /**@} end of group CSI2_REVA_CFG_C0_SWAP_SEL_Register */ 733 734 /** 735 * @ingroup csi2_reva_registers 736 * @defgroup CSI2_REVA_CFG_DPDN_SWAP CSI2_REVA_CFG_DPDN_SWAP 737 * @brief CFG_DPDN_SWAP. 738 * @{ 739 */ 740 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE0_POS 0 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE0 Position */ 741 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE0_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE0 Mask */ 742 743 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE1_POS 1 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE1 Position */ 744 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE1_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE1 Mask */ 745 746 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE2_POS 2 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE2 Position */ 747 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE2 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE2_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE2 Mask */ 748 749 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE3_POS 3 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE3 Position */ 750 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE3 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_DATA_LANE3_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE3 Mask */ 751 752 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_CLK_LANE_POS 4 /**< CFG_DPDN_SWAP_SWAP_CLK_LANE Position */ 753 #define MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_CLK_LANE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_CFG_DPDN_SWAP_SWAP_CLK_LANE_POS)) /**< CFG_DPDN_SWAP_SWAP_CLK_LANE Mask */ 754 755 /**@} end of group CSI2_REVA_CFG_DPDN_SWAP_Register */ 756 757 /** 758 * @ingroup csi2_reva_registers 759 * @defgroup CSI2_REVA_RESET_DESKEW CSI2_REVA_RESET_DESKEW 760 * @brief RESET_DESKEW. 761 * @{ 762 */ 763 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE0_POS 0 /**< RESET_DESKEW_DATA_LANE0 Position */ 764 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE0_POS)) /**< RESET_DESKEW_DATA_LANE0 Mask */ 765 766 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE1_POS 1 /**< RESET_DESKEW_DATA_LANE1 Position */ 767 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE1_POS)) /**< RESET_DESKEW_DATA_LANE1 Mask */ 768 769 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE2_POS 2 /**< RESET_DESKEW_DATA_LANE2 Position */ 770 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE2 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE2_POS)) /**< RESET_DESKEW_DATA_LANE2 Mask */ 771 772 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE3_POS 3 /**< RESET_DESKEW_DATA_LANE3 Position */ 773 #define MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE3 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RESET_DESKEW_DATA_LANE3_POS)) /**< RESET_DESKEW_DATA_LANE3 Mask */ 774 775 /**@} end of group CSI2_REVA_RESET_DESKEW_Register */ 776 777 /** 778 * @ingroup csi2_reva_registers 779 * @defgroup CSI2_REVA_VCONTROL CSI2_REVA_VCONTROL 780 * @brief PMA_RDY. 781 * @{ 782 */ 783 #define MXC_F_CSI2_REVA_VCONTROL_NORMAL_MODE_POS 0 /**< VCONTROL_NORMAL_MODE Position */ 784 #define MXC_F_CSI2_REVA_VCONTROL_NORMAL_MODE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_NORMAL_MODE_POS)) /**< VCONTROL_NORMAL_MODE Mask */ 785 786 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_TEST_POS 1 /**< VCONTROL_LP_RX_DC_TEST Position */ 787 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_TEST ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_TEST_POS)) /**< VCONTROL_LP_RX_DC_TEST Mask */ 788 789 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_1_POS 2 /**< VCONTROL_LP_RX_DC_1 Position */ 790 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_1_POS)) /**< VCONTROL_LP_RX_DC_1 Mask */ 791 792 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_0_POS 3 /**< VCONTROL_LP_RX_DC_0 Position */ 793 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_LP_RX_DC_0_POS)) /**< VCONTROL_LP_RX_DC_0 Mask */ 794 795 #define MXC_F_CSI2_REVA_VCONTROL_CAL_SEN_1_POS 4 /**< VCONTROL_CAL_SEN_1 Position */ 796 #define MXC_F_CSI2_REVA_VCONTROL_CAL_SEN_1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_CAL_SEN_1_POS)) /**< VCONTROL_CAL_SEN_1 Mask */ 797 798 #define MXC_F_CSI2_REVA_VCONTROL_CAL_SEN_0_POS 5 /**< VCONTROL_CAL_SEN_0 Position */ 799 #define MXC_F_CSI2_REVA_VCONTROL_CAL_SEN_0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_CAL_SEN_0_POS)) /**< VCONTROL_CAL_SEN_0 Mask */ 800 801 #define MXC_F_CSI2_REVA_VCONTROL_HSRT_0_POS 7 /**< VCONTROL_HSRT_0 Position */ 802 #define MXC_F_CSI2_REVA_VCONTROL_HSRT_0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_HSRT_0_POS)) /**< VCONTROL_HSRT_0 Mask */ 803 804 #define MXC_F_CSI2_REVA_VCONTROL_HSRT_1_POS 8 /**< VCONTROL_HSRT_1 Position */ 805 #define MXC_F_CSI2_REVA_VCONTROL_HSRT_1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_HSRT_1_POS)) /**< VCONTROL_HSRT_1 Mask */ 806 807 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_PARTBERT_POS 10 /**< VCONTROL_LP_RX_PARTBERT Position */ 808 #define MXC_F_CSI2_REVA_VCONTROL_LP_RX_PARTBERT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_LP_RX_PARTBERT_POS)) /**< VCONTROL_LP_RX_PARTBERT Mask */ 809 810 #define MXC_F_CSI2_REVA_VCONTROL_HS_INT_LOOPBACK_POS 11 /**< VCONTROL_HS_INT_LOOPBACK Position */ 811 #define MXC_F_CSI2_REVA_VCONTROL_HS_INT_LOOPBACK ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_HS_INT_LOOPBACK_POS)) /**< VCONTROL_HS_INT_LOOPBACK Mask */ 812 813 #define MXC_F_CSI2_REVA_VCONTROL_HS_RX_PARTBERT_POS 27 /**< VCONTROL_HS_RX_PARTBERT Position */ 814 #define MXC_F_CSI2_REVA_VCONTROL_HS_RX_PARTBERT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_HS_RX_PARTBERT_POS)) /**< VCONTROL_HS_RX_PARTBERT Mask */ 815 816 #define MXC_F_CSI2_REVA_VCONTROL_HS_RX_PRBS9_POS 28 /**< VCONTROL_HS_RX_PRBS9 Position */ 817 #define MXC_F_CSI2_REVA_VCONTROL_HS_RX_PRBS9 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_HS_RX_PRBS9_POS)) /**< VCONTROL_HS_RX_PRBS9 Mask */ 818 819 #define MXC_F_CSI2_REVA_VCONTROL_SUSPEND_MODE_POS 31 /**< VCONTROL_SUSPEND_MODE Position */ 820 #define MXC_F_CSI2_REVA_VCONTROL_SUSPEND_MODE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VCONTROL_SUSPEND_MODE_POS)) /**< VCONTROL_SUSPEND_MODE Mask */ 821 822 /**@} end of group CSI2_REVA_VCONTROL_Register */ 823 824 /** 825 * @ingroup csi2_reva_registers 826 * @defgroup CSI2_REVA_RG_CDRX_DSIRX_EN CSI2_REVA_RG_CDRX_DSIRX_EN 827 * @brief RG_CDRX_DSIRX_EN. 828 * @{ 829 */ 830 #define MXC_F_CSI2_REVA_RG_CDRX_DSIRX_EN_RXMODE_POS 0 /**< RG_CDRX_DSIRX_EN_RXMODE Position */ 831 #define MXC_F_CSI2_REVA_RG_CDRX_DSIRX_EN_RXMODE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RG_CDRX_DSIRX_EN_RXMODE_POS)) /**< RG_CDRX_DSIRX_EN_RXMODE Mask */ 832 833 /**@} end of group CSI2_REVA_RG_CDRX_DSIRX_EN_Register */ 834 835 /** 836 * @ingroup csi2_reva_registers 837 * @defgroup CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2 CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2 838 * @brief RG_CDRX_BISTHS_PLL_PRE_DIV2. 839 * @{ 840 */ 841 #define MXC_F_CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE_POS 0 /**< RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE Position */ 842 #define MXC_F_CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE_POS)) /**< RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE Mask */ 843 844 /**@} end of group CSI2_REVA_RG_CDRX_BISTHS_PLL_PRE_DIV2_Register */ 845 846 /** 847 * @ingroup csi2_reva_registers 848 * @defgroup CSI2_REVA_VFIFO_CFG0 CSI2_REVA_VFIFO_CFG0 849 * @brief Video FIFO Configuration Register 0. 850 * @{ 851 */ 852 #define MXC_F_CSI2_REVA_VFIFO_CFG0_VC_POS 0 /**< VFIFO_CFG0_VC Position */ 853 #define MXC_F_CSI2_REVA_VFIFO_CFG0_VC ((uint32_t)(0x3UL << MXC_F_CSI2_REVA_VFIFO_CFG0_VC_POS)) /**< VFIFO_CFG0_VC Mask */ 854 855 #define MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE_POS 6 /**< VFIFO_CFG0_DMAMODE Position */ 856 #define MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE ((uint32_t)(0x3UL << MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE_POS)) /**< VFIFO_CFG0_DMAMODE Mask */ 857 #define MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_NO_DMA ((uint32_t)0x0UL) /**< VFIFO_CFG0_DMAMODE_NO_DMA Value */ 858 #define MXC_S_CSI2_REVA_VFIFO_CFG0_DMAMODE_NO_DMA (MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_NO_DMA << MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_NO_DMA Setting */ 859 #define MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_DMA_REQ ((uint32_t)0x1UL) /**< VFIFO_CFG0_DMAMODE_DMA_REQ Value */ 860 #define MXC_S_CSI2_REVA_VFIFO_CFG0_DMAMODE_DMA_REQ (MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_DMA_REQ << MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_DMA_REQ Setting */ 861 #define MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_FIFO_THD ((uint32_t)0x2UL) /**< VFIFO_CFG0_DMAMODE_FIFO_THD Value */ 862 #define MXC_S_CSI2_REVA_VFIFO_CFG0_DMAMODE_FIFO_THD (MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_FIFO_THD << MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_FIFO_THD Setting */ 863 #define MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_FIFO_FULL ((uint32_t)0x3UL) /**< VFIFO_CFG0_DMAMODE_FIFO_FULL Value */ 864 #define MXC_S_CSI2_REVA_VFIFO_CFG0_DMAMODE_FIFO_FULL (MXC_V_CSI2_REVA_VFIFO_CFG0_DMAMODE_FIFO_FULL << MXC_F_CSI2_REVA_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_FIFO_FULL Setting */ 865 866 #define MXC_F_CSI2_REVA_VFIFO_CFG0_AHBWAIT_POS 8 /**< VFIFO_CFG0_AHBWAIT Position */ 867 #define MXC_F_CSI2_REVA_VFIFO_CFG0_AHBWAIT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG0_AHBWAIT_POS)) /**< VFIFO_CFG0_AHBWAIT Mask */ 868 869 #define MXC_F_CSI2_REVA_VFIFO_CFG0_FIFORM_POS 9 /**< VFIFO_CFG0_FIFORM Position */ 870 #define MXC_F_CSI2_REVA_VFIFO_CFG0_FIFORM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG0_FIFORM_POS)) /**< VFIFO_CFG0_FIFORM Mask */ 871 872 #define MXC_F_CSI2_REVA_VFIFO_CFG0_ERRDE_POS 10 /**< VFIFO_CFG0_ERRDE Position */ 873 #define MXC_F_CSI2_REVA_VFIFO_CFG0_ERRDE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG0_ERRDE_POS)) /**< VFIFO_CFG0_ERRDE Mask */ 874 875 #define MXC_F_CSI2_REVA_VFIFO_CFG0_FBWM_POS 11 /**< VFIFO_CFG0_FBWM Position */ 876 #define MXC_F_CSI2_REVA_VFIFO_CFG0_FBWM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG0_FBWM_POS)) /**< VFIFO_CFG0_FBWM Mask */ 877 878 /**@} end of group CSI2_REVA_VFIFO_CFG0_Register */ 879 880 /** 881 * @ingroup csi2_reva_registers 882 * @defgroup CSI2_REVA_VFIFO_CFG1 CSI2_REVA_VFIFO_CFG1 883 * @brief Video FIFO Configuration Register 1. 884 * @{ 885 */ 886 #define MXC_F_CSI2_REVA_VFIFO_CFG1_AHBWCYC_POS 0 /**< VFIFO_CFG1_AHBWCYC Position */ 887 #define MXC_F_CSI2_REVA_VFIFO_CFG1_AHBWCYC ((uint32_t)(0xFFFFUL << MXC_F_CSI2_REVA_VFIFO_CFG1_AHBWCYC_POS)) /**< VFIFO_CFG1_AHBWCYC Mask */ 888 889 #define MXC_F_CSI2_REVA_VFIFO_CFG1_WAIT_FIRST_FS_POS 16 /**< VFIFO_CFG1_WAIT_FIRST_FS Position */ 890 #define MXC_F_CSI2_REVA_VFIFO_CFG1_WAIT_FIRST_FS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG1_WAIT_FIRST_FS_POS)) /**< VFIFO_CFG1_WAIT_FIRST_FS Mask */ 891 892 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_FRAME_CTRL_POS 17 /**< VFIFO_CFG1_ACCU_FRAME_CTRL Position */ 893 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_FRAME_CTRL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_FRAME_CTRL_POS)) /**< VFIFO_CFG1_ACCU_FRAME_CTRL Mask */ 894 895 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_LINE_CTRL_POS 18 /**< VFIFO_CFG1_ACCU_LINE_CTRL Position */ 896 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_LINE_CTRL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_LINE_CTRL_POS)) /**< VFIFO_CFG1_ACCU_LINE_CTRL Mask */ 897 898 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_LINE_CNT_POS 19 /**< VFIFO_CFG1_ACCU_LINE_CNT Position */ 899 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_LINE_CNT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_LINE_CNT_POS)) /**< VFIFO_CFG1_ACCU_LINE_CNT Mask */ 900 901 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_PIXEL_CNT_POS 20 /**< VFIFO_CFG1_ACCU_PIXEL_CNT Position */ 902 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_PIXEL_CNT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_PIXEL_CNT_POS)) /**< VFIFO_CFG1_ACCU_PIXEL_CNT Mask */ 903 904 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_PIXEL_ZERO_POS 21 /**< VFIFO_CFG1_ACCU_PIXEL_ZERO Position */ 905 #define MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_PIXEL_ZERO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CFG1_ACCU_PIXEL_ZERO_POS)) /**< VFIFO_CFG1_ACCU_PIXEL_ZERO Mask */ 906 907 /**@} end of group CSI2_REVA_VFIFO_CFG1_Register */ 908 909 /** 910 * @ingroup csi2_reva_registers 911 * @defgroup CSI2_REVA_VFIFO_CTRL CSI2_REVA_VFIFO_CTRL 912 * @brief Video FIFO Control Register. 913 * @{ 914 */ 915 #define MXC_F_CSI2_REVA_VFIFO_CTRL_FIFOEN_POS 0 /**< VFIFO_CTRL_FIFOEN Position */ 916 #define MXC_F_CSI2_REVA_VFIFO_CTRL_FIFOEN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CTRL_FIFOEN_POS)) /**< VFIFO_CTRL_FIFOEN Mask */ 917 918 #define MXC_F_CSI2_REVA_VFIFO_CTRL_FLUSH_POS 4 /**< VFIFO_CTRL_FLUSH Position */ 919 #define MXC_F_CSI2_REVA_VFIFO_CTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_CTRL_FLUSH_POS)) /**< VFIFO_CTRL_FLUSH Mask */ 920 921 #define MXC_F_CSI2_REVA_VFIFO_CTRL_THD_POS 8 /**< VFIFO_CTRL_THD Position */ 922 #define MXC_F_CSI2_REVA_VFIFO_CTRL_THD ((uint32_t)(0x7FUL << MXC_F_CSI2_REVA_VFIFO_CTRL_THD_POS)) /**< VFIFO_CTRL_THD Mask */ 923 924 /**@} end of group CSI2_REVA_VFIFO_CTRL_Register */ 925 926 /** 927 * @ingroup csi2_reva_registers 928 * @defgroup CSI2_REVA_VFIFO_STS CSI2_REVA_VFIFO_STS 929 * @brief Video FIFO Status Register. 930 * @{ 931 */ 932 #define MXC_F_CSI2_REVA_VFIFO_STS_FEMPTY_POS 0 /**< VFIFO_STS_FEMPTY Position */ 933 #define MXC_F_CSI2_REVA_VFIFO_STS_FEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_FEMPTY_POS)) /**< VFIFO_STS_FEMPTY Mask */ 934 935 #define MXC_F_CSI2_REVA_VFIFO_STS_FTHD_POS 1 /**< VFIFO_STS_FTHD Position */ 936 #define MXC_F_CSI2_REVA_VFIFO_STS_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_FTHD_POS)) /**< VFIFO_STS_FTHD Mask */ 937 938 #define MXC_F_CSI2_REVA_VFIFO_STS_FFULL_POS 2 /**< VFIFO_STS_FFULL Position */ 939 #define MXC_F_CSI2_REVA_VFIFO_STS_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_FFULL_POS)) /**< VFIFO_STS_FFULL Mask */ 940 941 #define MXC_F_CSI2_REVA_VFIFO_STS_UNDERRUN_POS 3 /**< VFIFO_STS_UNDERRUN Position */ 942 #define MXC_F_CSI2_REVA_VFIFO_STS_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_UNDERRUN_POS)) /**< VFIFO_STS_UNDERRUN Mask */ 943 944 #define MXC_F_CSI2_REVA_VFIFO_STS_OVERRUN_POS 4 /**< VFIFO_STS_OVERRUN Position */ 945 #define MXC_F_CSI2_REVA_VFIFO_STS_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_OVERRUN_POS)) /**< VFIFO_STS_OVERRUN Mask */ 946 947 #define MXC_F_CSI2_REVA_VFIFO_STS_OUTSYNC_POS 5 /**< VFIFO_STS_OUTSYNC Position */ 948 #define MXC_F_CSI2_REVA_VFIFO_STS_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_OUTSYNC_POS)) /**< VFIFO_STS_OUTSYNC Mask */ 949 950 #define MXC_F_CSI2_REVA_VFIFO_STS_FMTERR_POS 6 /**< VFIFO_STS_FMTERR Position */ 951 #define MXC_F_CSI2_REVA_VFIFO_STS_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_FMTERR_POS)) /**< VFIFO_STS_FMTERR Mask */ 952 953 #define MXC_F_CSI2_REVA_VFIFO_STS_AHBWTO_POS 7 /**< VFIFO_STS_AHBWTO Position */ 954 #define MXC_F_CSI2_REVA_VFIFO_STS_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_AHBWTO_POS)) /**< VFIFO_STS_AHBWTO Mask */ 955 956 #define MXC_F_CSI2_REVA_VFIFO_STS_FS_POS 8 /**< VFIFO_STS_FS Position */ 957 #define MXC_F_CSI2_REVA_VFIFO_STS_FS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_FS_POS)) /**< VFIFO_STS_FS Mask */ 958 959 #define MXC_F_CSI2_REVA_VFIFO_STS_FE_POS 9 /**< VFIFO_STS_FE Position */ 960 #define MXC_F_CSI2_REVA_VFIFO_STS_FE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_FE_POS)) /**< VFIFO_STS_FE Mask */ 961 962 #define MXC_F_CSI2_REVA_VFIFO_STS_LS_POS 10 /**< VFIFO_STS_LS Position */ 963 #define MXC_F_CSI2_REVA_VFIFO_STS_LS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_LS_POS)) /**< VFIFO_STS_LS Mask */ 964 965 #define MXC_F_CSI2_REVA_VFIFO_STS_LE_POS 11 /**< VFIFO_STS_LE Position */ 966 #define MXC_F_CSI2_REVA_VFIFO_STS_LE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_STS_LE_POS)) /**< VFIFO_STS_LE Mask */ 967 968 #define MXC_F_CSI2_REVA_VFIFO_STS_FELT_POS 16 /**< VFIFO_STS_FELT Position */ 969 #define MXC_F_CSI2_REVA_VFIFO_STS_FELT ((uint32_t)(0x7FUL << MXC_F_CSI2_REVA_VFIFO_STS_FELT_POS)) /**< VFIFO_STS_FELT Mask */ 970 971 #define MXC_F_CSI2_REVA_VFIFO_STS_FMT_POS 24 /**< VFIFO_STS_FMT Position */ 972 #define MXC_F_CSI2_REVA_VFIFO_STS_FMT ((uint32_t)(0x3FUL << MXC_F_CSI2_REVA_VFIFO_STS_FMT_POS)) /**< VFIFO_STS_FMT Mask */ 973 974 /**@} end of group CSI2_REVA_VFIFO_STS_Register */ 975 976 /** 977 * @ingroup csi2_reva_registers 978 * @defgroup CSI2_REVA_VFIFO_LINE_NUM CSI2_REVA_VFIFO_LINE_NUM 979 * @brief Video FIFO CSI Line Number Per Frame. 980 * @{ 981 */ 982 #define MXC_F_CSI2_REVA_VFIFO_LINE_NUM_LINE_NUM_POS 0 /**< VFIFO_LINE_NUM_LINE_NUM Position */ 983 #define MXC_F_CSI2_REVA_VFIFO_LINE_NUM_LINE_NUM ((uint32_t)(0x1FFFUL << MXC_F_CSI2_REVA_VFIFO_LINE_NUM_LINE_NUM_POS)) /**< VFIFO_LINE_NUM_LINE_NUM Mask */ 984 985 /**@} end of group CSI2_REVA_VFIFO_LINE_NUM_Register */ 986 987 /** 988 * @ingroup csi2_reva_registers 989 * @defgroup CSI2_REVA_VFIFO_PIXEL_NUM CSI2_REVA_VFIFO_PIXEL_NUM 990 * @brief Video FIFO CSI Pixel Number Per Line. 991 * @{ 992 */ 993 #define MXC_F_CSI2_REVA_VFIFO_PIXEL_NUM_PIXEL_NUM_POS 0 /**< VFIFO_PIXEL_NUM_PIXEL_NUM Position */ 994 #define MXC_F_CSI2_REVA_VFIFO_PIXEL_NUM_PIXEL_NUM ((uint32_t)(0x3FFFUL << MXC_F_CSI2_REVA_VFIFO_PIXEL_NUM_PIXEL_NUM_POS)) /**< VFIFO_PIXEL_NUM_PIXEL_NUM Mask */ 995 996 /**@} end of group CSI2_REVA_VFIFO_PIXEL_NUM_Register */ 997 998 /** 999 * @ingroup csi2_reva_registers 1000 * @defgroup CSI2_REVA_VFIFO_LINE_CNT CSI2_REVA_VFIFO_LINE_CNT 1001 * @brief Video FIFO CSI Line Count. 1002 * @{ 1003 */ 1004 #define MXC_F_CSI2_REVA_VFIFO_LINE_CNT_LINE_CNT_POS 0 /**< VFIFO_LINE_CNT_LINE_CNT Position */ 1005 #define MXC_F_CSI2_REVA_VFIFO_LINE_CNT_LINE_CNT ((uint32_t)(0xFFFUL << MXC_F_CSI2_REVA_VFIFO_LINE_CNT_LINE_CNT_POS)) /**< VFIFO_LINE_CNT_LINE_CNT Mask */ 1006 1007 /**@} end of group CSI2_REVA_VFIFO_LINE_CNT_Register */ 1008 1009 /** 1010 * @ingroup csi2_reva_registers 1011 * @defgroup CSI2_REVA_VFIFO_PIXEL_CNT CSI2_REVA_VFIFO_PIXEL_CNT 1012 * @brief Video FIFO CSI Pixel Count. 1013 * @{ 1014 */ 1015 #define MXC_F_CSI2_REVA_VFIFO_PIXEL_CNT_PIXEL_CNT_POS 0 /**< VFIFO_PIXEL_CNT_PIXEL_CNT Position */ 1016 #define MXC_F_CSI2_REVA_VFIFO_PIXEL_CNT_PIXEL_CNT ((uint32_t)(0x1FFFUL << MXC_F_CSI2_REVA_VFIFO_PIXEL_CNT_PIXEL_CNT_POS)) /**< VFIFO_PIXEL_CNT_PIXEL_CNT Mask */ 1017 1018 /**@} end of group CSI2_REVA_VFIFO_PIXEL_CNT_Register */ 1019 1020 /** 1021 * @ingroup csi2_reva_registers 1022 * @defgroup CSI2_REVA_VFIFO_FRAME_STS CSI2_REVA_VFIFO_FRAME_STS 1023 * @brief Video FIFO Frame Status Register. 1024 * @{ 1025 */ 1026 #define MXC_F_CSI2_REVA_VFIFO_FRAME_STS_FRAME_STATE_POS 0 /**< VFIFO_FRAME_STS_FRAME_STATE Position */ 1027 #define MXC_F_CSI2_REVA_VFIFO_FRAME_STS_FRAME_STATE ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_VFIFO_FRAME_STS_FRAME_STATE_POS)) /**< VFIFO_FRAME_STS_FRAME_STATE Mask */ 1028 1029 #define MXC_F_CSI2_REVA_VFIFO_FRAME_STS_ERROR_CODE_POS 3 /**< VFIFO_FRAME_STS_ERROR_CODE Position */ 1030 #define MXC_F_CSI2_REVA_VFIFO_FRAME_STS_ERROR_CODE ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_VFIFO_FRAME_STS_ERROR_CODE_POS)) /**< VFIFO_FRAME_STS_ERROR_CODE Mask */ 1031 1032 /**@} end of group CSI2_REVA_VFIFO_FRAME_STS_Register */ 1033 1034 /** 1035 * @ingroup csi2_reva_registers 1036 * @defgroup CSI2_REVA_VFIFO_RAW_CTRL CSI2_REVA_VFIFO_RAW_CTRL 1037 * @brief Video FIFO RAW-to-RGB Control Register. 1038 * @{ 1039 */ 1040 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_CEN_POS 0 /**< VFIFO_RAW_CTRL_RAW_CEN Position */ 1041 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_CEN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_CEN_POS)) /**< VFIFO_RAW_CTRL_RAW_CEN Mask */ 1042 1043 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FF_AFO_POS 1 /**< VFIFO_RAW_CTRL_RAW_FF_AFO Position */ 1044 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FF_AFO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FF_AFO_POS)) /**< VFIFO_RAW_CTRL_RAW_FF_AFO Mask */ 1045 1046 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FF_FO_POS 4 /**< VFIFO_RAW_CTRL_RAW_FF_FO Position */ 1047 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FF_FO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FF_FO_POS)) /**< VFIFO_RAW_CTRL_RAW_FF_FO Mask */ 1048 1049 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_POS 8 /**< VFIFO_RAW_CTRL_RAW_FMT Position */ 1050 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT ((uint32_t)(0x3UL << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_POS)) /**< VFIFO_RAW_CTRL_RAW_FMT Mask */ 1051 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB ((uint32_t)0x0UL) /**< VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB Value */ 1052 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB Setting */ 1053 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG ((uint32_t)0x1UL) /**< VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG Value */ 1054 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG Setting */ 1055 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG ((uint32_t)0x2UL) /**< VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG Value */ 1056 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG Setting */ 1057 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR ((uint32_t)0x3UL) /**< VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR Value */ 1058 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR Setting */ 1059 1060 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS 12 /**< VFIFO_RAW_CTRL_RGB_TYP Position */ 1061 #define MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP ((uint32_t)(0x7UL << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS)) /**< VFIFO_RAW_CTRL_RGB_TYP Mask */ 1062 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB444 ((uint32_t)0x0UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB444 Value */ 1063 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB444 (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB444 << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB444 Setting */ 1064 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB555 ((uint32_t)0x1UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB555 Value */ 1065 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB555 (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB555 << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB555 Setting */ 1066 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB565 ((uint32_t)0x2UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB565 Value */ 1067 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB565 (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB565 << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB565 Setting */ 1068 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB666 ((uint32_t)0x3UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB666 Value */ 1069 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB666 (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGB666 << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB666 Setting */ 1070 #define MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGG888 ((uint32_t)0x4UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGG888 Value */ 1071 #define MXC_S_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGG888 (MXC_V_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_RGG888 << MXC_F_CSI2_REVA_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGG888 Setting */ 1072 1073 /**@} end of group CSI2_REVA_VFIFO_RAW_CTRL_Register */ 1074 1075 /** 1076 * @ingroup csi2_reva_registers 1077 * @defgroup CSI2_REVA_VFIFO_RAW_BUF0_ADDR CSI2_REVA_VFIFO_RAW_BUF0_ADDR 1078 * @brief Video FIFO RAW-to-RGB Line Buffer0 Address. 1079 * @{ 1080 */ 1081 #define MXC_F_CSI2_REVA_VFIFO_RAW_BUF0_ADDR_ADDR_POS 2 /**< VFIFO_RAW_BUF0_ADDR_ADDR Position */ 1082 #define MXC_F_CSI2_REVA_VFIFO_RAW_BUF0_ADDR_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_REVA_VFIFO_RAW_BUF0_ADDR_ADDR_POS)) /**< VFIFO_RAW_BUF0_ADDR_ADDR Mask */ 1083 1084 /**@} end of group CSI2_REVA_VFIFO_RAW_BUF0_ADDR_Register */ 1085 1086 /** 1087 * @ingroup csi2_reva_registers 1088 * @defgroup CSI2_REVA_VFIFO_RAW_BUF1_ADDR CSI2_REVA_VFIFO_RAW_BUF1_ADDR 1089 * @brief Video FIFO RAW-to-RGB Line Buffer1 Address. 1090 * @{ 1091 */ 1092 #define MXC_F_CSI2_REVA_VFIFO_RAW_BUF1_ADDR_ADDR_POS 2 /**< VFIFO_RAW_BUF1_ADDR_ADDR Position */ 1093 #define MXC_F_CSI2_REVA_VFIFO_RAW_BUF1_ADDR_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_REVA_VFIFO_RAW_BUF1_ADDR_ADDR_POS)) /**< VFIFO_RAW_BUF1_ADDR_ADDR Mask */ 1094 1095 /**@} end of group CSI2_REVA_VFIFO_RAW_BUF1_ADDR_Register */ 1096 1097 /** 1098 * @ingroup csi2_reva_registers 1099 * @defgroup CSI2_REVA_VFIFO_AHBM_CTRL CSI2_REVA_VFIFO_AHBM_CTRL 1100 * @brief Video FIFO AHB Master Control Register. 1101 * @{ 1102 */ 1103 #define MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_AHBMEN_POS 0 /**< VFIFO_AHBM_CTRL_AHBMEN Position */ 1104 #define MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_AHBMEN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_AHBMEN_POS)) /**< VFIFO_AHBM_CTRL_AHBMEN Mask */ 1105 1106 #define MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_AHBMCLR_POS 1 /**< VFIFO_AHBM_CTRL_AHBMCLR Position */ 1107 #define MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_AHBMCLR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_AHBMCLR_POS)) /**< VFIFO_AHBM_CTRL_AHBMCLR Mask */ 1108 1109 #define MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_POS 4 /**< VFIFO_AHBM_CTRL_BSTLEN Position */ 1110 #define MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN ((uint32_t)(0x3UL << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_POS)) /**< VFIFO_AHBM_CTRL_BSTLEN Mask */ 1111 #define MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD ((uint32_t)0x0UL) /**< VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD Value */ 1112 #define MXC_S_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD (MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD Setting */ 1113 #define MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD ((uint32_t)0x1UL) /**< VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD Value */ 1114 #define MXC_S_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD (MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD Setting */ 1115 #define MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS ((uint32_t)0x2UL) /**< VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS Value */ 1116 #define MXC_S_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS (MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS Setting */ 1117 #define MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS ((uint32_t)0x3UL) /**< VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS Value */ 1118 #define MXC_S_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS (MXC_V_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS << MXC_F_CSI2_REVA_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS Setting */ 1119 1120 /**@} end of group CSI2_REVA_VFIFO_AHBM_CTRL_Register */ 1121 1122 /** 1123 * @ingroup csi2_reva_registers 1124 * @defgroup CSI2_REVA_VFIFO_AHBM_STS CSI2_REVA_VFIFO_AHBM_STS 1125 * @brief Video FIFO AHB Master Status Register. 1126 * @{ 1127 */ 1128 #define MXC_F_CSI2_REVA_VFIFO_AHBM_STS_HRDY_TO_POS 0 /**< VFIFO_AHBM_STS_HRDY_TO Position */ 1129 #define MXC_F_CSI2_REVA_VFIFO_AHBM_STS_HRDY_TO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_AHBM_STS_HRDY_TO_POS)) /**< VFIFO_AHBM_STS_HRDY_TO Mask */ 1130 1131 #define MXC_F_CSI2_REVA_VFIFO_AHBM_STS_IDLE_TO_POS 1 /**< VFIFO_AHBM_STS_IDLE_TO Position */ 1132 #define MXC_F_CSI2_REVA_VFIFO_AHBM_STS_IDLE_TO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_AHBM_STS_IDLE_TO_POS)) /**< VFIFO_AHBM_STS_IDLE_TO Mask */ 1133 1134 #define MXC_F_CSI2_REVA_VFIFO_AHBM_STS_TRANS_MAX_POS 2 /**< VFIFO_AHBM_STS_TRANS_MAX Position */ 1135 #define MXC_F_CSI2_REVA_VFIFO_AHBM_STS_TRANS_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_VFIFO_AHBM_STS_TRANS_MAX_POS)) /**< VFIFO_AHBM_STS_TRANS_MAX Mask */ 1136 1137 /**@} end of group CSI2_REVA_VFIFO_AHBM_STS_Register */ 1138 1139 /** 1140 * @ingroup csi2_reva_registers 1141 * @defgroup CSI2_REVA_VFIFO_AHBM_START_ADDR CSI2_REVA_VFIFO_AHBM_START_ADDR 1142 * @brief Video FIFO AHB Master Start Address Register. 1143 * @{ 1144 */ 1145 #define MXC_F_CSI2_REVA_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR_POS 2 /**< VFIFO_AHBM_START_ADDR_AHBM_START_ADDR Position */ 1146 #define MXC_F_CSI2_REVA_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_REVA_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR_POS)) /**< VFIFO_AHBM_START_ADDR_AHBM_START_ADDR Mask */ 1147 1148 /**@} end of group CSI2_REVA_VFIFO_AHBM_START_ADDR_Register */ 1149 1150 /** 1151 * @ingroup csi2_reva_registers 1152 * @defgroup CSI2_REVA_VFIFO_AHBM_ADDR_RANGE CSI2_REVA_VFIFO_AHBM_ADDR_RANGE 1153 * @brief Video FIFO AHB Master Address Range Register. 1154 * @{ 1155 */ 1156 #define MXC_F_CSI2_REVA_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE_POS 2 /**< VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE Position */ 1157 #define MXC_F_CSI2_REVA_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE ((uint32_t)(0x3FFFUL << MXC_F_CSI2_REVA_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE_POS)) /**< VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE Mask */ 1158 1159 /**@} end of group CSI2_REVA_VFIFO_AHBM_ADDR_RANGE_Register */ 1160 1161 /** 1162 * @ingroup csi2_reva_registers 1163 * @defgroup CSI2_REVA_VFIFO_AHBM_MAX_TRANS CSI2_REVA_VFIFO_AHBM_MAX_TRANS 1164 * @brief Video FIFO AHB Master Maximal Transfer Number Register. 1165 * @{ 1166 */ 1167 #define MXC_F_CSI2_REVA_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS_POS 0 /**< VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS Position */ 1168 #define MXC_F_CSI2_REVA_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CSI2_REVA_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS_POS)) /**< VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS Mask */ 1169 1170 /**@} end of group CSI2_REVA_VFIFO_AHBM_MAX_TRANS_Register */ 1171 1172 /** 1173 * @ingroup csi2_reva_registers 1174 * @defgroup CSI2_REVA_VFIFO_AHBM_TRANS_CNT CSI2_REVA_VFIFO_AHBM_TRANS_CNT 1175 * @brief Video FIFO AHB Master Transfer Count Register. 1176 * @{ 1177 */ 1178 #define MXC_F_CSI2_REVA_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT_POS 0 /**< VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT Position */ 1179 #define MXC_F_CSI2_REVA_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_CSI2_REVA_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT_POS)) /**< VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT Mask */ 1180 1181 /**@} end of group CSI2_REVA_VFIFO_AHBM_TRANS_CNT_Register */ 1182 1183 /** 1184 * @ingroup csi2_reva_registers 1185 * @defgroup CSI2_REVA_RX_EINT_VFF_IE CSI2_REVA_RX_EINT_VFF_IE 1186 * @brief RX Video FIFO Interrupt Enable Register. 1187 * @{ 1188 */ 1189 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FNEMPTY_POS 0 /**< RX_EINT_VFF_IE_FNEMPTY Position */ 1190 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FNEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FNEMPTY_POS)) /**< RX_EINT_VFF_IE_FNEMPTY Mask */ 1191 1192 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FTHD_POS 1 /**< RX_EINT_VFF_IE_FTHD Position */ 1193 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FTHD_POS)) /**< RX_EINT_VFF_IE_FTHD Mask */ 1194 1195 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FFULL_POS 2 /**< RX_EINT_VFF_IE_FFULL Position */ 1196 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FFULL_POS)) /**< RX_EINT_VFF_IE_FFULL Mask */ 1197 1198 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_UNDERRUN_POS 3 /**< RX_EINT_VFF_IE_UNDERRUN Position */ 1199 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_UNDERRUN_POS)) /**< RX_EINT_VFF_IE_UNDERRUN Mask */ 1200 1201 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_OVERRUN_POS 4 /**< RX_EINT_VFF_IE_OVERRUN Position */ 1202 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_OVERRUN_POS)) /**< RX_EINT_VFF_IE_OVERRUN Mask */ 1203 1204 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_OUTSYNC_POS 5 /**< RX_EINT_VFF_IE_OUTSYNC Position */ 1205 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_OUTSYNC_POS)) /**< RX_EINT_VFF_IE_OUTSYNC Mask */ 1206 1207 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FMTERR_POS 6 /**< RX_EINT_VFF_IE_FMTERR Position */ 1208 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FMTERR_POS)) /**< RX_EINT_VFF_IE_FMTERR Mask */ 1209 1210 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBWTO_POS 7 /**< RX_EINT_VFF_IE_AHBWTO Position */ 1211 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBWTO_POS)) /**< RX_EINT_VFF_IE_AHBWTO Mask */ 1212 1213 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FS_POS 8 /**< RX_EINT_VFF_IE_FS Position */ 1214 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FS_POS)) /**< RX_EINT_VFF_IE_FS Mask */ 1215 1216 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FE_POS 9 /**< RX_EINT_VFF_IE_FE Position */ 1217 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FE_POS)) /**< RX_EINT_VFF_IE_FE Mask */ 1218 1219 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_LS_POS 10 /**< RX_EINT_VFF_IE_LS Position */ 1220 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_LS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_LS_POS)) /**< RX_EINT_VFF_IE_LS Mask */ 1221 1222 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_LE_POS 11 /**< RX_EINT_VFF_IE_LE Position */ 1223 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_LE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_LE_POS)) /**< RX_EINT_VFF_IE_LE Mask */ 1224 1225 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_RAW_OVR_POS 12 /**< RX_EINT_VFF_IE_RAW_OVR Position */ 1226 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_RAW_OVR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_RAW_OVR_POS)) /**< RX_EINT_VFF_IE_RAW_OVR Mask */ 1227 1228 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_RAW_AHBERR_POS 13 /**< RX_EINT_VFF_IE_RAW_AHBERR Position */ 1229 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_RAW_AHBERR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_RAW_AHBERR_POS)) /**< RX_EINT_VFF_IE_RAW_AHBERR Mask */ 1230 1231 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FNEMP_MD_POS 16 /**< RX_EINT_VFF_IE_FNEMP_MD Position */ 1232 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FNEMP_MD ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FNEMP_MD_POS)) /**< RX_EINT_VFF_IE_FNEMP_MD Mask */ 1233 1234 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FTHD_MD_POS 17 /**< RX_EINT_VFF_IE_FTHD_MD Position */ 1235 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FTHD_MD ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FTHD_MD_POS)) /**< RX_EINT_VFF_IE_FTHD_MD Mask */ 1236 1237 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FFUL_MD_POS 18 /**< RX_EINT_VFF_IE_FFUL_MD Position */ 1238 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FFUL_MD ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_FFUL_MD_POS)) /**< RX_EINT_VFF_IE_FFUL_MD Mask */ 1239 1240 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_RDTO_POS 24 /**< RX_EINT_VFF_IE_AHBM_RDTO Position */ 1241 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_RDTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_RDTO_POS)) /**< RX_EINT_VFF_IE_AHBM_RDTO Mask */ 1242 1243 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_IDTO_POS 25 /**< RX_EINT_VFF_IE_AHBM_IDTO Position */ 1244 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_IDTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_IDTO_POS)) /**< RX_EINT_VFF_IE_AHBM_IDTO Mask */ 1245 1246 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_MAX_POS 26 /**< RX_EINT_VFF_IE_AHBM_MAX Position */ 1247 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IE_AHBM_MAX_POS)) /**< RX_EINT_VFF_IE_AHBM_MAX Mask */ 1248 1249 /**@} end of group CSI2_REVA_RX_EINT_VFF_IE_Register */ 1250 1251 /** 1252 * @ingroup csi2_reva_registers 1253 * @defgroup CSI2_REVA_RX_EINT_VFF_IF CSI2_REVA_RX_EINT_VFF_IF 1254 * @brief RX Video FIFO Interrupt Flag Register. 1255 * @{ 1256 */ 1257 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FNEMPTY_POS 0 /**< RX_EINT_VFF_IF_FNEMPTY Position */ 1258 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FNEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FNEMPTY_POS)) /**< RX_EINT_VFF_IF_FNEMPTY Mask */ 1259 1260 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FTHD_POS 1 /**< RX_EINT_VFF_IF_FTHD Position */ 1261 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FTHD_POS)) /**< RX_EINT_VFF_IF_FTHD Mask */ 1262 1263 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FFULL_POS 2 /**< RX_EINT_VFF_IF_FFULL Position */ 1264 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FFULL_POS)) /**< RX_EINT_VFF_IF_FFULL Mask */ 1265 1266 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_UNDERRUN_POS 3 /**< RX_EINT_VFF_IF_UNDERRUN Position */ 1267 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_UNDERRUN_POS)) /**< RX_EINT_VFF_IF_UNDERRUN Mask */ 1268 1269 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_OVERRUN_POS 4 /**< RX_EINT_VFF_IF_OVERRUN Position */ 1270 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_OVERRUN_POS)) /**< RX_EINT_VFF_IF_OVERRUN Mask */ 1271 1272 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_OUTSYNC_POS 5 /**< RX_EINT_VFF_IF_OUTSYNC Position */ 1273 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_OUTSYNC_POS)) /**< RX_EINT_VFF_IF_OUTSYNC Mask */ 1274 1275 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FMTERR_POS 6 /**< RX_EINT_VFF_IF_FMTERR Position */ 1276 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FMTERR_POS)) /**< RX_EINT_VFF_IF_FMTERR Mask */ 1277 1278 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBWTO_POS 7 /**< RX_EINT_VFF_IF_AHBWTO Position */ 1279 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBWTO_POS)) /**< RX_EINT_VFF_IF_AHBWTO Mask */ 1280 1281 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FS_POS 8 /**< RX_EINT_VFF_IF_FS Position */ 1282 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FS_POS)) /**< RX_EINT_VFF_IF_FS Mask */ 1283 1284 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FE_POS 9 /**< RX_EINT_VFF_IF_FE Position */ 1285 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_FE_POS)) /**< RX_EINT_VFF_IF_FE Mask */ 1286 1287 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_LS_POS 10 /**< RX_EINT_VFF_IF_LS Position */ 1288 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_LS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_LS_POS)) /**< RX_EINT_VFF_IF_LS Mask */ 1289 1290 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_LE_POS 11 /**< RX_EINT_VFF_IF_LE Position */ 1291 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_LE ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_LE_POS)) /**< RX_EINT_VFF_IF_LE Mask */ 1292 1293 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_RAW_OVR_POS 12 /**< RX_EINT_VFF_IF_RAW_OVR Position */ 1294 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_RAW_OVR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_RAW_OVR_POS)) /**< RX_EINT_VFF_IF_RAW_OVR Mask */ 1295 1296 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_RAW_AHBERR_POS 13 /**< RX_EINT_VFF_IF_RAW_AHBERR Position */ 1297 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_RAW_AHBERR ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_RAW_AHBERR_POS)) /**< RX_EINT_VFF_IF_RAW_AHBERR Mask */ 1298 1299 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_RDTO_POS 24 /**< RX_EINT_VFF_IF_AHBM_RDTO Position */ 1300 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_RDTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_RDTO_POS)) /**< RX_EINT_VFF_IF_AHBM_RDTO Mask */ 1301 1302 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_IDTO_POS 25 /**< RX_EINT_VFF_IF_AHBM_IDTO Position */ 1303 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_IDTO ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_IDTO_POS)) /**< RX_EINT_VFF_IF_AHBM_IDTO Mask */ 1304 1305 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_MAX_POS 26 /**< RX_EINT_VFF_IF_AHBM_MAX Position */ 1306 #define MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_VFF_IF_AHBM_MAX_POS)) /**< RX_EINT_VFF_IF_AHBM_MAX Mask */ 1307 1308 /**@} end of group CSI2_REVA_RX_EINT_VFF_IF_Register */ 1309 1310 /** 1311 * @ingroup csi2_reva_registers 1312 * @defgroup CSI2_REVA_RX_EINT_PPI_IE CSI2_REVA_RX_EINT_PPI_IE 1313 * @brief RX D-PHY Interrupt Enable Register. 1314 * @{ 1315 */ 1316 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0STOP_POS 0 /**< RX_EINT_PPI_IE_DL0STOP Position */ 1317 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0STOP_POS)) /**< RX_EINT_PPI_IE_DL0STOP Mask */ 1318 1319 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1STOP_POS 1 /**< RX_EINT_PPI_IE_DL1STOP Position */ 1320 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1STOP_POS)) /**< RX_EINT_PPI_IE_DL1STOP Mask */ 1321 1322 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_CL0STOP_POS 4 /**< RX_EINT_PPI_IE_CL0STOP Position */ 1323 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_CL0STOP_POS)) /**< RX_EINT_PPI_IE_CL0STOP Mask */ 1324 1325 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECONT0_POS 6 /**< RX_EINT_PPI_IE_DL0ECONT0 Position */ 1326 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECONT0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECONT0_POS)) /**< RX_EINT_PPI_IE_DL0ECONT0 Mask */ 1327 1328 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECONT1_POS 7 /**< RX_EINT_PPI_IE_DL0ECONT1 Position */ 1329 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECONT1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECONT1_POS)) /**< RX_EINT_PPI_IE_DL0ECONT1 Mask */ 1330 1331 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESOT_POS 8 /**< RX_EINT_PPI_IE_DL0ESOT Position */ 1332 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESOT_POS)) /**< RX_EINT_PPI_IE_DL0ESOT Mask */ 1333 1334 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESOT_POS 9 /**< RX_EINT_PPI_IE_DL1ESOT Position */ 1335 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESOT_POS)) /**< RX_EINT_PPI_IE_DL1ESOT Mask */ 1336 1337 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESOTS_POS 12 /**< RX_EINT_PPI_IE_DL0ESOTS Position */ 1338 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESOTS_POS)) /**< RX_EINT_PPI_IE_DL0ESOTS Mask */ 1339 1340 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESOTS_POS 13 /**< RX_EINT_PPI_IE_DL1ESOTS Position */ 1341 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESOTS_POS)) /**< RX_EINT_PPI_IE_DL1ESOTS Mask */ 1342 1343 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0EESC_POS 16 /**< RX_EINT_PPI_IE_DL0EESC Position */ 1344 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0EESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0EESC_POS)) /**< RX_EINT_PPI_IE_DL0EESC Mask */ 1345 1346 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1EESC_POS 17 /**< RX_EINT_PPI_IE_DL1EESC Position */ 1347 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1EESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1EESC_POS)) /**< RX_EINT_PPI_IE_DL1EESC Mask */ 1348 1349 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESESC_POS 20 /**< RX_EINT_PPI_IE_DL0ESESC Position */ 1350 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ESESC_POS)) /**< RX_EINT_PPI_IE_DL0ESESC Mask */ 1351 1352 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESESC_POS 21 /**< RX_EINT_PPI_IE_DL1ESESC Position */ 1353 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ESESC_POS)) /**< RX_EINT_PPI_IE_DL1ESESC Mask */ 1354 1355 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECTL_POS 24 /**< RX_EINT_PPI_IE_DL0ECTL Position */ 1356 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL0ECTL_POS)) /**< RX_EINT_PPI_IE_DL0ECTL Mask */ 1357 1358 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ECTL_POS 25 /**< RX_EINT_PPI_IE_DL1ECTL Position */ 1359 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IE_DL1ECTL_POS)) /**< RX_EINT_PPI_IE_DL1ECTL Mask */ 1360 1361 /**@} end of group CSI2_REVA_RX_EINT_PPI_IE_Register */ 1362 1363 /** 1364 * @ingroup csi2_reva_registers 1365 * @defgroup CSI2_REVA_RX_EINT_PPI_IF CSI2_REVA_RX_EINT_PPI_IF 1366 * @brief RX D-PHY Interrupt Flag Register. 1367 * @{ 1368 */ 1369 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0STOP_POS 0 /**< RX_EINT_PPI_IF_DL0STOP Position */ 1370 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0STOP_POS)) /**< RX_EINT_PPI_IF_DL0STOP Mask */ 1371 1372 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1STOP_POS 1 /**< RX_EINT_PPI_IF_DL1STOP Position */ 1373 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1STOP_POS)) /**< RX_EINT_PPI_IF_DL1STOP Mask */ 1374 1375 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_CL0STOP_POS 4 /**< RX_EINT_PPI_IF_CL0STOP Position */ 1376 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_CL0STOP_POS)) /**< RX_EINT_PPI_IF_CL0STOP Mask */ 1377 1378 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECONT0_POS 6 /**< RX_EINT_PPI_IF_DL0ECONT0 Position */ 1379 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECONT0 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECONT0_POS)) /**< RX_EINT_PPI_IF_DL0ECONT0 Mask */ 1380 1381 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECONT1_POS 7 /**< RX_EINT_PPI_IF_DL0ECONT1 Position */ 1382 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECONT1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECONT1_POS)) /**< RX_EINT_PPI_IF_DL0ECONT1 Mask */ 1383 1384 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESOT_POS 8 /**< RX_EINT_PPI_IF_DL0ESOT Position */ 1385 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESOT_POS)) /**< RX_EINT_PPI_IF_DL0ESOT Mask */ 1386 1387 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESOT_POS 9 /**< RX_EINT_PPI_IF_DL1ESOT Position */ 1388 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESOT_POS)) /**< RX_EINT_PPI_IF_DL1ESOT Mask */ 1389 1390 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESOTS_POS 12 /**< RX_EINT_PPI_IF_DL0ESOTS Position */ 1391 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESOTS_POS)) /**< RX_EINT_PPI_IF_DL0ESOTS Mask */ 1392 1393 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESOTS_POS 13 /**< RX_EINT_PPI_IF_DL1ESOTS Position */ 1394 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESOTS_POS)) /**< RX_EINT_PPI_IF_DL1ESOTS Mask */ 1395 1396 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0EESC_POS 16 /**< RX_EINT_PPI_IF_DL0EESC Position */ 1397 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0EESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0EESC_POS)) /**< RX_EINT_PPI_IF_DL0EESC Mask */ 1398 1399 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1EESC_POS 17 /**< RX_EINT_PPI_IF_DL1EESC Position */ 1400 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1EESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1EESC_POS)) /**< RX_EINT_PPI_IF_DL1EESC Mask */ 1401 1402 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESESC_POS 20 /**< RX_EINT_PPI_IF_DL0ESESC Position */ 1403 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ESESC_POS)) /**< RX_EINT_PPI_IF_DL0ESESC Mask */ 1404 1405 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESESC_POS 21 /**< RX_EINT_PPI_IF_DL1ESESC Position */ 1406 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ESESC_POS)) /**< RX_EINT_PPI_IF_DL1ESESC Mask */ 1407 1408 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECTL_POS 24 /**< RX_EINT_PPI_IF_DL0ECTL Position */ 1409 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL0ECTL_POS)) /**< RX_EINT_PPI_IF_DL0ECTL Mask */ 1410 1411 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ECTL_POS 25 /**< RX_EINT_PPI_IF_DL1ECTL Position */ 1412 #define MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_PPI_IF_DL1ECTL_POS)) /**< RX_EINT_PPI_IF_DL1ECTL Mask */ 1413 1414 /**@} end of group CSI2_REVA_RX_EINT_PPI_IF_Register */ 1415 1416 /** 1417 * @ingroup csi2_reva_registers 1418 * @defgroup CSI2_REVA_RX_EINT_CTRL_IE CSI2_REVA_RX_EINT_CTRL_IE 1419 * @brief RX Controller Interrupt Enable Register. 1420 * @{ 1421 */ 1422 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EECC2_POS 0 /**< RX_EINT_CTRL_IE_EECC2 Position */ 1423 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EECC2 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EECC2_POS)) /**< RX_EINT_CTRL_IE_EECC2 Mask */ 1424 1425 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EECC1_POS 1 /**< RX_EINT_CTRL_IE_EECC1 Position */ 1426 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EECC1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EECC1_POS)) /**< RX_EINT_CTRL_IE_EECC1 Mask */ 1427 1428 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_ECRC_POS 2 /**< RX_EINT_CTRL_IE_ECRC Position */ 1429 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_ECRC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_ECRC_POS)) /**< RX_EINT_CTRL_IE_ECRC Mask */ 1430 1431 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EID_POS 3 /**< RX_EINT_CTRL_IE_EID Position */ 1432 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EID ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_EID_POS)) /**< RX_EINT_CTRL_IE_EID Mask */ 1433 1434 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_PKTFFOV_POS 4 /**< RX_EINT_CTRL_IE_PKTFFOV Position */ 1435 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_PKTFFOV ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_PKTFFOV_POS)) /**< RX_EINT_CTRL_IE_PKTFFOV Mask */ 1436 1437 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL0ULPSA_POS 8 /**< RX_EINT_CTRL_IE_DL0ULPSA Position */ 1438 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL0ULPSA_POS)) /**< RX_EINT_CTRL_IE_DL0ULPSA Mask */ 1439 1440 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL1ULPSA_POS 9 /**< RX_EINT_CTRL_IE_DL1ULPSA Position */ 1441 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL1ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL1ULPSA_POS)) /**< RX_EINT_CTRL_IE_DL1ULPSA Mask */ 1442 1443 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL0ULPSM_POS 12 /**< RX_EINT_CTRL_IE_DL0ULPSM Position */ 1444 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL0ULPSM_POS)) /**< RX_EINT_CTRL_IE_DL0ULPSM Mask */ 1445 1446 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL1ULPSM_POS 13 /**< RX_EINT_CTRL_IE_DL1ULPSM Position */ 1447 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL1ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_DL1ULPSM_POS)) /**< RX_EINT_CTRL_IE_DL1ULPSM Mask */ 1448 1449 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_CL0ULPSA_POS 16 /**< RX_EINT_CTRL_IE_CL0ULPSA Position */ 1450 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_CL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_CL0ULPSA_POS)) /**< RX_EINT_CTRL_IE_CL0ULPSA Mask */ 1451 1452 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_CL0ULPSM_POS 17 /**< RX_EINT_CTRL_IE_CL0ULPSM Position */ 1453 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_CL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IE_CL0ULPSM_POS)) /**< RX_EINT_CTRL_IE_CL0ULPSM Mask */ 1454 1455 /**@} end of group CSI2_REVA_RX_EINT_CTRL_IE_Register */ 1456 1457 /** 1458 * @ingroup csi2_reva_registers 1459 * @defgroup CSI2_REVA_RX_EINT_CTRL_IF CSI2_REVA_RX_EINT_CTRL_IF 1460 * @brief RX Controller Interrupt Flag Register. 1461 * @{ 1462 */ 1463 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EECC2_POS 0 /**< RX_EINT_CTRL_IF_EECC2 Position */ 1464 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EECC2 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EECC2_POS)) /**< RX_EINT_CTRL_IF_EECC2 Mask */ 1465 1466 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EECC1_POS 1 /**< RX_EINT_CTRL_IF_EECC1 Position */ 1467 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EECC1 ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EECC1_POS)) /**< RX_EINT_CTRL_IF_EECC1 Mask */ 1468 1469 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_ECRC_POS 2 /**< RX_EINT_CTRL_IF_ECRC Position */ 1470 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_ECRC ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_ECRC_POS)) /**< RX_EINT_CTRL_IF_ECRC Mask */ 1471 1472 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EID_POS 3 /**< RX_EINT_CTRL_IF_EID Position */ 1473 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EID ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_EID_POS)) /**< RX_EINT_CTRL_IF_EID Mask */ 1474 1475 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_PKTFFOV_POS 4 /**< RX_EINT_CTRL_IF_PKTFFOV Position */ 1476 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_PKTFFOV ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_PKTFFOV_POS)) /**< RX_EINT_CTRL_IF_PKTFFOV Mask */ 1477 1478 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL0ULPSA_POS 8 /**< RX_EINT_CTRL_IF_DL0ULPSA Position */ 1479 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL0ULPSA_POS)) /**< RX_EINT_CTRL_IF_DL0ULPSA Mask */ 1480 1481 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL1ULPSA_POS 9 /**< RX_EINT_CTRL_IF_DL1ULPSA Position */ 1482 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL1ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL1ULPSA_POS)) /**< RX_EINT_CTRL_IF_DL1ULPSA Mask */ 1483 1484 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL0ULPSM_POS 12 /**< RX_EINT_CTRL_IF_DL0ULPSM Position */ 1485 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL0ULPSM_POS)) /**< RX_EINT_CTRL_IF_DL0ULPSM Mask */ 1486 1487 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL1ULPSM_POS 13 /**< RX_EINT_CTRL_IF_DL1ULPSM Position */ 1488 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL1ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_DL1ULPSM_POS)) /**< RX_EINT_CTRL_IF_DL1ULPSM Mask */ 1489 1490 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_CL0ULPSA_POS 16 /**< RX_EINT_CTRL_IF_CL0ULPSA Position */ 1491 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_CL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_CL0ULPSA_POS)) /**< RX_EINT_CTRL_IF_CL0ULPSA Mask */ 1492 1493 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_CL0ULPSM_POS 17 /**< RX_EINT_CTRL_IF_CL0ULPSM Position */ 1494 #define MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_CL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_RX_EINT_CTRL_IF_CL0ULPSM_POS)) /**< RX_EINT_CTRL_IF_CL0ULPSM Mask */ 1495 1496 /**@} end of group CSI2_REVA_RX_EINT_CTRL_IF_Register */ 1497 1498 /** 1499 * @ingroup csi2_reva_registers 1500 * @defgroup CSI2_REVA_PPI_STOPSTATE CSI2_REVA_PPI_STOPSTATE 1501 * @brief DPHY PPI Stop State Register. 1502 * @{ 1503 */ 1504 #define MXC_F_CSI2_REVA_PPI_STOPSTATE_DL0STOP_POS 0 /**< PPI_STOPSTATE_DL0STOP Position */ 1505 #define MXC_F_CSI2_REVA_PPI_STOPSTATE_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_PPI_STOPSTATE_DL0STOP_POS)) /**< PPI_STOPSTATE_DL0STOP Mask */ 1506 1507 #define MXC_F_CSI2_REVA_PPI_STOPSTATE_DL1STOP_POS 1 /**< PPI_STOPSTATE_DL1STOP Position */ 1508 #define MXC_F_CSI2_REVA_PPI_STOPSTATE_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_PPI_STOPSTATE_DL1STOP_POS)) /**< PPI_STOPSTATE_DL1STOP Mask */ 1509 1510 #define MXC_F_CSI2_REVA_PPI_STOPSTATE_CL0STOP_POS 2 /**< PPI_STOPSTATE_CL0STOP Position */ 1511 #define MXC_F_CSI2_REVA_PPI_STOPSTATE_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_PPI_STOPSTATE_CL0STOP_POS)) /**< PPI_STOPSTATE_CL0STOP Mask */ 1512 1513 /**@} end of group CSI2_REVA_PPI_STOPSTATE_Register */ 1514 1515 /** 1516 * @ingroup csi2_reva_registers 1517 * @defgroup CSI2_REVA_PPI_TURNAROUND_CFG CSI2_REVA_PPI_TURNAROUND_CFG 1518 * @brief DPHY PPI Turn-Around Configuration Register. 1519 * @{ 1520 */ 1521 #define MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0TAREQ_POS 0 /**< PPI_TURNAROUND_CFG_DL0TAREQ Position */ 1522 #define MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0TAREQ ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0TAREQ_POS)) /**< PPI_TURNAROUND_CFG_DL0TAREQ Mask */ 1523 1524 #define MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0TADIS_POS 1 /**< PPI_TURNAROUND_CFG_DL0TADIS Position */ 1525 #define MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0TADIS ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0TADIS_POS)) /**< PPI_TURNAROUND_CFG_DL0TADIS Mask */ 1526 1527 #define MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0FRCRX_POS 2 /**< PPI_TURNAROUND_CFG_DL0FRCRX Position */ 1528 #define MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0FRCRX ((uint32_t)(0x1UL << MXC_F_CSI2_REVA_PPI_TURNAROUND_CFG_DL0FRCRX_POS)) /**< PPI_TURNAROUND_CFG_DL0FRCRX Mask */ 1529 1530 /**@} end of group CSI2_REVA_PPI_TURNAROUND_CFG_Register */ 1531 1532 #ifdef __cplusplus 1533 } 1534 #endif 1535 1536 #endif /* _CSI2_REVA_REGS_H_ */ 1537
