1 /** 2 * @file cameraif_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CAMERAIF_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _CAMERAIF_REVA_REGS_H_ 27 #define _CAMERAIF_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup cameraif_reva 65 * @defgroup cameraif_reva_registers CAMERAIF_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the CAMERAIF_REVA Peripheral Module. 67 * @details CameraIF Interface. 68 */ 69 70 /** 71 * @ingroup cameraif_reva_registers 72 * Structure type to access the CAMERAIF_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ver; /**< <tt>\b 0x0000:</tt> CAMERAIF_REVA VER Register */ 76 __IO uint32_t fifo_size; /**< <tt>\b 0x0004:</tt> CAMERAIF_REVA FIFO_SIZE Register */ 77 __IO uint32_t ctrl; /**< <tt>\b 0x0008:</tt> CAMERAIF_REVA CTRL Register */ 78 __IO uint32_t int_en; /**< <tt>\b 0x000C:</tt> CAMERAIF_REVA INT_EN Register */ 79 __IO uint32_t int_fl; /**< <tt>\b 0x0010:</tt> CAMERAIF_REVA INT_FL Register */ 80 __IO uint32_t ds_timing_codes; /**< <tt>\b 0x0014:</tt> CAMERAIF_REVA DS_TIMING_CODES Register */ 81 __R uint32_t rsv_0x18_0x2f[6]; 82 __IO uint32_t fifo_data; /**< <tt>\b 0x0030:</tt> CAMERAIF_REVA FIFO_DATA Register */ 83 } mxc_cameraif_reva_regs_t; 84 85 /* Register offsets for module CAMERAIF_REVA */ 86 /** 87 * @ingroup cameraif_reva_registers 88 * @defgroup CAMERAIF_REVA_Register_Offsets Register Offsets 89 * @brief CAMERAIF_REVA Peripheral Register Offsets from the CAMERAIF_REVA Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_CAMERAIF_REVA_VER ((uint32_t)0x00000000UL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_CAMERAIF_REVA_FIFO_SIZE ((uint32_t)0x00000004UL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_CAMERAIF_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_CAMERAIF_REVA_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_CAMERAIF_REVA_INT_FL ((uint32_t)0x00000010UL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_CAMERAIF_REVA_DS_TIMING_CODES ((uint32_t)0x00000014UL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x0014</tt> */ 98 #define MXC_R_CAMERAIF_REVA_FIFO_DATA ((uint32_t)0x00000030UL) /**< Offset from CAMERAIF_REVA Base Address: <tt> 0x0030</tt> */ 99 /**@} end of group cameraif_reva_registers */ 100 101 /** 102 * @ingroup cameraif_reva_registers 103 * @defgroup CAMERAIF_REVA_VER CAMERAIF_REVA_VER 104 * @brief CameraIF Version 105 * @{ 106 */ 107 #define MXC_F_CAMERAIF_REVA_VER_MINOR_POS 0 /**< VER_MINOR Position */ 108 #define MXC_F_CAMERAIF_REVA_VER_MINOR ((uint32_t)(0xFFUL << MXC_F_CAMERAIF_REVA_VER_MINOR_POS)) /**< VER_MINOR Mask */ 109 110 #define MXC_F_CAMERAIF_REVA_VER_MAJOR_POS 8 /**< VER_MAJOR Position */ 111 #define MXC_F_CAMERAIF_REVA_VER_MAJOR ((uint32_t)(0xFFUL << MXC_F_CAMERAIF_REVA_VER_MAJOR_POS)) /**< VER_MAJOR Mask */ 112 113 /**@} end of group CAMERAIF_REVA_VER_Register */ 114 115 /** 116 * @ingroup cameraif_reva_registers 117 * @defgroup CAMERAIF_REVA_FIFO_SIZE CAMERAIF_REVA_FIFO_SIZE 118 * @brief 1-Wire Master Clock Divisor. 119 * @{ 120 */ 121 #define MXC_F_CAMERAIF_REVA_FIFO_SIZE_FIFO_SIZE_POS 0 /**< FIFO_SIZE_FIFO_SIZE Position */ 122 #define MXC_F_CAMERAIF_REVA_FIFO_SIZE_FIFO_SIZE ((uint32_t)(0xFFUL << MXC_F_CAMERAIF_REVA_FIFO_SIZE_FIFO_SIZE_POS)) /**< FIFO_SIZE_FIFO_SIZE Mask */ 123 124 /**@} end of group CAMERAIF_REVA_FIFO_SIZE_Register */ 125 126 /** 127 * @ingroup cameraif_reva_registers 128 * @defgroup CAMERAIF_REVA_CTRL CAMERAIF_REVA_CTRL 129 * @brief Control register 130 * @{ 131 */ 132 #define MXC_F_CAMERAIF_REVA_CTRL_READ_MODE_POS 0 /**< CTRL_READ_MODE Position */ 133 #define MXC_F_CAMERAIF_REVA_CTRL_READ_MODE ((uint32_t)(0x3UL << MXC_F_CAMERAIF_REVA_CTRL_READ_MODE_POS)) /**< CTRL_READ_MODE Mask */ 134 #define MXC_V_CAMERAIF_REVA_CTRL_READ_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_READ_MODE_DIS Value */ 135 #define MXC_S_CAMERAIF_REVA_CTRL_READ_MODE_DIS (MXC_V_CAMERAIF_REVA_CTRL_READ_MODE_DIS << MXC_F_CAMERAIF_REVA_CTRL_READ_MODE_POS) /**< CTRL_READ_MODE_DIS Setting */ 136 #define MXC_V_CAMERAIF_REVA_CTRL_READ_MODE_SINGLE_IMG ((uint32_t)0x1UL) /**< CTRL_READ_MODE_SINGLE_IMG Value */ 137 #define MXC_S_CAMERAIF_REVA_CTRL_READ_MODE_SINGLE_IMG (MXC_V_CAMERAIF_REVA_CTRL_READ_MODE_SINGLE_IMG << MXC_F_CAMERAIF_REVA_CTRL_READ_MODE_POS) /**< CTRL_READ_MODE_SINGLE_IMG Setting */ 138 #define MXC_V_CAMERAIF_REVA_CTRL_READ_MODE_CONTINUOUS ((uint32_t)0x2UL) /**< CTRL_READ_MODE_CONTINUOUS Value */ 139 #define MXC_S_CAMERAIF_REVA_CTRL_READ_MODE_CONTINUOUS (MXC_V_CAMERAIF_REVA_CTRL_READ_MODE_CONTINUOUS << MXC_F_CAMERAIF_REVA_CTRL_READ_MODE_POS) /**< CTRL_READ_MODE_CONTINUOUS Setting */ 140 141 #define MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH_POS 2 /**< CTRL_DATA_WIDTH Position */ 142 #define MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH_POS)) /**< CTRL_DATA_WIDTH Mask */ 143 #define MXC_V_CAMERAIF_REVA_CTRL_DATA_WIDTH_8BIT ((uint32_t)0x0UL) /**< CTRL_DATA_WIDTH_8BIT Value */ 144 #define MXC_S_CAMERAIF_REVA_CTRL_DATA_WIDTH_8BIT (MXC_V_CAMERAIF_REVA_CTRL_DATA_WIDTH_8BIT << MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH_POS) /**< CTRL_DATA_WIDTH_8BIT Setting */ 145 #define MXC_V_CAMERAIF_REVA_CTRL_DATA_WIDTH_10BIT ((uint32_t)0x1UL) /**< CTRL_DATA_WIDTH_10BIT Value */ 146 #define MXC_S_CAMERAIF_REVA_CTRL_DATA_WIDTH_10BIT (MXC_V_CAMERAIF_REVA_CTRL_DATA_WIDTH_10BIT << MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH_POS) /**< CTRL_DATA_WIDTH_10BIT Setting */ 147 #define MXC_V_CAMERAIF_REVA_CTRL_DATA_WIDTH_12BIT ((uint32_t)0x2UL) /**< CTRL_DATA_WIDTH_12BIT Value */ 148 #define MXC_S_CAMERAIF_REVA_CTRL_DATA_WIDTH_12BIT (MXC_V_CAMERAIF_REVA_CTRL_DATA_WIDTH_12BIT << MXC_F_CAMERAIF_REVA_CTRL_DATA_WIDTH_POS) /**< CTRL_DATA_WIDTH_12BIT Setting */ 149 150 #define MXC_F_CAMERAIF_REVA_CTRL_DS_TIMING_EN_POS 4 /**< CTRL_DS_TIMING_EN Position */ 151 #define MXC_F_CAMERAIF_REVA_CTRL_DS_TIMING_EN ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_CTRL_DS_TIMING_EN_POS)) /**< CTRL_DS_TIMING_EN Mask */ 152 153 #define MXC_F_CAMERAIF_REVA_CTRL_FIFO_THRSH_POS 5 /**< CTRL_FIFO_THRSH Position */ 154 #define MXC_F_CAMERAIF_REVA_CTRL_FIFO_THRSH ((uint32_t)(0x1FUL << MXC_F_CAMERAIF_REVA_CTRL_FIFO_THRSH_POS)) /**< CTRL_FIFO_THRSH Mask */ 155 156 #define MXC_F_CAMERAIF_REVA_CTRL_RX_DMA_POS 10 /**< CTRL_RX_DMA Position */ 157 #define MXC_F_CAMERAIF_REVA_CTRL_RX_DMA ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_CTRL_RX_DMA_POS)) /**< CTRL_RX_DMA Mask */ 158 159 #define MXC_F_CAMERAIF_REVA_CTRL_RX_DMA_THRSH_POS 11 /**< CTRL_RX_DMA_THRSH Position */ 160 #define MXC_F_CAMERAIF_REVA_CTRL_RX_DMA_THRSH ((uint32_t)(0xFUL << MXC_F_CAMERAIF_REVA_CTRL_RX_DMA_THRSH_POS)) /**< CTRL_RX_DMA_THRSH Mask */ 161 162 #define MXC_F_CAMERAIF_REVA_CTRL_PCIF_SYS_POS 15 /**< CTRL_PCIF_SYS Position */ 163 #define MXC_F_CAMERAIF_REVA_CTRL_PCIF_SYS ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_CTRL_PCIF_SYS_POS)) /**< CTRL_PCIF_SYS Mask */ 164 165 /**@} end of group CAMERAIF_REVA_CTRL_Register */ 166 167 /** 168 * @ingroup cameraif_reva_registers 169 * @defgroup CAMERAIF_REVA_INT_EN CAMERAIF_REVA_INT_EN 170 * @brief Interupt Enable register 171 * @{ 172 */ 173 #define MXC_F_CAMERAIF_REVA_INT_EN_IMG_DONE_POS 0 /**< INT_EN_IMG_DONE Position */ 174 #define MXC_F_CAMERAIF_REVA_INT_EN_IMG_DONE ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_EN_IMG_DONE_POS)) /**< INT_EN_IMG_DONE Mask */ 175 176 #define MXC_F_CAMERAIF_REVA_INT_EN_FIFO_FULL_POS 1 /**< INT_EN_FIFO_FULL Position */ 177 #define MXC_F_CAMERAIF_REVA_INT_EN_FIFO_FULL ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_EN_FIFO_FULL_POS)) /**< INT_EN_FIFO_FULL Mask */ 178 179 #define MXC_F_CAMERAIF_REVA_INT_EN_FIFO_THRESH_POS 2 /**< INT_EN_FIFO_THRESH Position */ 180 #define MXC_F_CAMERAIF_REVA_INT_EN_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_EN_FIFO_THRESH_POS)) /**< INT_EN_FIFO_THRESH Mask */ 181 182 #define MXC_F_CAMERAIF_REVA_INT_EN_FIFO_NOT_EMPTY_POS 3 /**< INT_EN_FIFO_NOT_EMPTY Position */ 183 #define MXC_F_CAMERAIF_REVA_INT_EN_FIFO_NOT_EMPTY ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_EN_FIFO_NOT_EMPTY_POS)) /**< INT_EN_FIFO_NOT_EMPTY Mask */ 184 185 /**@} end of group CAMERAIF_REVA_INT_EN_Register */ 186 187 /** 188 * @ingroup cameraif_reva_registers 189 * @defgroup CAMERAIF_REVA_INT_FL CAMERAIF_REVA_INT_FL 190 * @brief Interupt Flags register 191 * @{ 192 */ 193 #define MXC_F_CAMERAIF_REVA_INT_FL_IMG_DONE_POS 0 /**< INT_FL_IMG_DONE Position */ 194 #define MXC_F_CAMERAIF_REVA_INT_FL_IMG_DONE ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_FL_IMG_DONE_POS)) /**< INT_FL_IMG_DONE Mask */ 195 196 #define MXC_F_CAMERAIF_REVA_INT_FL_FIFO_FULL_POS 1 /**< INT_FL_FIFO_FULL Position */ 197 #define MXC_F_CAMERAIF_REVA_INT_FL_FIFO_FULL ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_FL_FIFO_FULL_POS)) /**< INT_FL_FIFO_FULL Mask */ 198 199 #define MXC_F_CAMERAIF_REVA_INT_FL_FIFO_THRESH_POS 2 /**< INT_FL_FIFO_THRESH Position */ 200 #define MXC_F_CAMERAIF_REVA_INT_FL_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_FL_FIFO_THRESH_POS)) /**< INT_FL_FIFO_THRESH Mask */ 201 202 #define MXC_F_CAMERAIF_REVA_INT_FL_FIFO_NOT_EMPTY_POS 3 /**< INT_FL_FIFO_NOT_EMPTY Position */ 203 #define MXC_F_CAMERAIF_REVA_INT_FL_FIFO_NOT_EMPTY ((uint32_t)(0x1UL << MXC_F_CAMERAIF_REVA_INT_FL_FIFO_NOT_EMPTY_POS)) /**< INT_FL_FIFO_NOT_EMPTY Mask */ 204 205 /**@} end of group CAMERAIF_REVA_INT_FL_Register */ 206 207 /** 208 * @ingroup cameraif_reva_registers 209 * @defgroup CAMERAIF_REVA_DS_TIMING_CODES CAMERAIF_REVA_DS_TIMING_CODES 210 * @brief DS Timing Codes register 211 * @{ 212 */ 213 #define MXC_F_CAMERAIF_REVA_DS_TIMING_CODES_SAV_POS 0 /**< DS_TIMING_CODES_SAV Position */ 214 #define MXC_F_CAMERAIF_REVA_DS_TIMING_CODES_SAV ((uint32_t)(0xFFUL << MXC_F_CAMERAIF_REVA_DS_TIMING_CODES_SAV_POS)) /**< DS_TIMING_CODES_SAV Mask */ 215 216 #define MXC_F_CAMERAIF_REVA_DS_TIMING_CODES_EAV_POS 8 /**< DS_TIMING_CODES_EAV Position */ 217 #define MXC_F_CAMERAIF_REVA_DS_TIMING_CODES_EAV ((uint32_t)(0xFFUL << MXC_F_CAMERAIF_REVA_DS_TIMING_CODES_EAV_POS)) /**< DS_TIMING_CODES_EAV Mask */ 218 219 /**@} end of group CAMERAIF_REVA_DS_TIMING_CODES_Register */ 220 221 /** 222 * @ingroup cameraif_reva_registers 223 * @defgroup CAMERAIF_REVA_FIFO_DATA CAMERAIF_REVA_FIFO_DATA 224 * @brief FIFO DATA register 225 * @{ 226 */ 227 #define MXC_F_CAMERAIF_REVA_FIFO_DATA_FIFO_DATA_POS 0 /**< FIFO_DATA_FIFO_DATA Position */ 228 #define MXC_F_CAMERAIF_REVA_FIFO_DATA_FIFO_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAMERAIF_REVA_FIFO_DATA_FIFO_DATA_POS)) /**< FIFO_DATA_FIFO_DATA Mask */ 229 230 /**@} end of group CAMERAIF_REVA_FIFO_DATA_Register */ 231 232 #ifdef __cplusplus 233 } 234 #endif 235 236 #endif /* _CAMERAIF_REVA_REGS_H_ */ 237
