1 /** 2 * @file scn_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SCN Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SCN_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SCN_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup scn 66 * @defgroup scn_registers SCN_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the SCN Peripheral Module. 68 * @details Smart Card Interface. 69 */ 70 71 /** 72 * @ingroup scn_registers 73 * Structure type to access the SCN Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cr; /**< <tt>\b 0x00:</tt> SCN CR Register */ 77 __IO uint32_t sr; /**< <tt>\b 0x04:</tt> SCN SR Register */ 78 __IO uint32_t pn; /**< <tt>\b 0x08:</tt> SCN PN Register */ 79 __IO uint32_t etur; /**< <tt>\b 0x0C:</tt> SCN ETUR Register */ 80 __IO uint32_t gtr; /**< <tt>\b 0x10:</tt> SCN GTR Register */ 81 __IO uint32_t wt0r; /**< <tt>\b 0x14:</tt> SCN WT0R Register */ 82 __IO uint32_t wt1r; /**< <tt>\b 0x18:</tt> SCN WT1R Register */ 83 __IO uint32_t ier; /**< <tt>\b 0x1C:</tt> SCN IER Register */ 84 __IO uint32_t isr; /**< <tt>\b 0x20:</tt> SCN ISR Register */ 85 __IO uint32_t txr; /**< <tt>\b 0x24:</tt> SCN TXR Register */ 86 __IO uint32_t rxr; /**< <tt>\b 0x28:</tt> SCN RXR Register */ 87 __IO uint32_t ccr; /**< <tt>\b 0x2C:</tt> SCN CCR Register */ 88 } mxc_scn_regs_t; 89 90 /* Register offsets for module SCN */ 91 /** 92 * @ingroup scn_registers 93 * @defgroup SCN_Register_Offsets Register Offsets 94 * @brief SCN Peripheral Register Offsets from the SCN Base Peripheral Address. 95 * @{ 96 */ 97 #define MXC_R_SCN_CR ((uint32_t)0x00000000UL) /**< Offset from SCN Base Address: <tt> 0x0000</tt> */ 98 #define MXC_R_SCN_SR ((uint32_t)0x00000004UL) /**< Offset from SCN Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_SCN_PN ((uint32_t)0x00000008UL) /**< Offset from SCN Base Address: <tt> 0x0008</tt> */ 100 #define MXC_R_SCN_ETUR ((uint32_t)0x0000000CUL) /**< Offset from SCN Base Address: <tt> 0x000C</tt> */ 101 #define MXC_R_SCN_GTR ((uint32_t)0x00000010UL) /**< Offset from SCN Base Address: <tt> 0x0010</tt> */ 102 #define MXC_R_SCN_WT0R ((uint32_t)0x00000014UL) /**< Offset from SCN Base Address: <tt> 0x0014</tt> */ 103 #define MXC_R_SCN_WT1R ((uint32_t)0x00000018UL) /**< Offset from SCN Base Address: <tt> 0x0018</tt> */ 104 #define MXC_R_SCN_IER ((uint32_t)0x0000001CUL) /**< Offset from SCN Base Address: <tt> 0x001C</tt> */ 105 #define MXC_R_SCN_ISR ((uint32_t)0x00000020UL) /**< Offset from SCN Base Address: <tt> 0x0020</tt> */ 106 #define MXC_R_SCN_TXR ((uint32_t)0x00000024UL) /**< Offset from SCN Base Address: <tt> 0x0024</tt> */ 107 #define MXC_R_SCN_RXR ((uint32_t)0x00000028UL) /**< Offset from SCN Base Address: <tt> 0x0028</tt> */ 108 #define MXC_R_SCN_CCR ((uint32_t)0x0000002CUL) /**< Offset from SCN Base Address: <tt> 0x002C</tt> */ 109 /**@} end of group scn_registers */ 110 111 /** 112 * @ingroup scn_registers 113 * @defgroup SCN_CR SCN_CR 114 * @brief Control Register. 115 * @{ 116 */ 117 #define MXC_F_SCN_CR_CONV_POS 0 /**< CR_CONV Position */ 118 #define MXC_F_SCN_CR_CONV ((uint32_t)(0x1UL << MXC_F_SCN_CR_CONV_POS)) /**< CR_CONV Mask */ 119 120 #define MXC_F_SCN_CR_CREP_POS 1 /**< CR_CREP Position */ 121 #define MXC_F_SCN_CR_CREP ((uint32_t)(0x1UL << MXC_F_SCN_CR_CREP_POS)) /**< CR_CREP Mask */ 122 123 #define MXC_F_SCN_CR_WTEN_POS 2 /**< CR_WTEN Position */ 124 #define MXC_F_SCN_CR_WTEN ((uint32_t)(0x1UL << MXC_F_SCN_CR_WTEN_POS)) /**< CR_WTEN Mask */ 125 126 #define MXC_F_SCN_CR_UART_POS 3 /**< CR_UART Position */ 127 #define MXC_F_SCN_CR_UART ((uint32_t)(0x1UL << MXC_F_SCN_CR_UART_POS)) /**< CR_UART Mask */ 128 129 #define MXC_F_SCN_CR_CCEN_POS 4 /**< CR_CCEN Position */ 130 #define MXC_F_SCN_CR_CCEN ((uint32_t)(0x1UL << MXC_F_SCN_CR_CCEN_POS)) /**< CR_CCEN Mask */ 131 132 #define MXC_F_SCN_CR_RXFLUSH_POS 5 /**< CR_RXFLUSH Position */ 133 #define MXC_F_SCN_CR_RXFLUSH ((uint32_t)(0x1UL << MXC_F_SCN_CR_RXFLUSH_POS)) /**< CR_RXFLUSH Mask */ 134 135 #define MXC_F_SCN_CR_TXFLUSH_POS 6 /**< CR_TXFLUSH Position */ 136 #define MXC_F_SCN_CR_TXFLUSH ((uint32_t)(0x1UL << MXC_F_SCN_CR_TXFLUSH_POS)) /**< CR_TXFLUSH Mask */ 137 138 #define MXC_F_SCN_CR_RXTHD_POS 8 /**< CR_RXTHD Position */ 139 #define MXC_F_SCN_CR_RXTHD ((uint32_t)(0xFUL << MXC_F_SCN_CR_RXTHD_POS)) /**< CR_RXTHD Mask */ 140 141 #define MXC_F_SCN_CR_TXTHD_POS 12 /**< CR_TXTHD Position */ 142 #define MXC_F_SCN_CR_TXTHD ((uint32_t)(0xFUL << MXC_F_SCN_CR_TXTHD_POS)) /**< CR_TXTHD Mask */ 143 144 /**@} end of group SCN_CR_Register */ 145 146 /** 147 * @ingroup scn_registers 148 * @defgroup SCN_SR SCN_SR 149 * @brief Status Register. 150 * @{ 151 */ 152 #define MXC_F_SCN_SR_PAR_POS 0 /**< SR_PAR Position */ 153 #define MXC_F_SCN_SR_PAR ((uint32_t)(0x1UL << MXC_F_SCN_SR_PAR_POS)) /**< SR_PAR Mask */ 154 155 #define MXC_F_SCN_SR_WTOV_POS 1 /**< SR_WTOV Position */ 156 #define MXC_F_SCN_SR_WTOV ((uint32_t)(0x1UL << MXC_F_SCN_SR_WTOV_POS)) /**< SR_WTOV Mask */ 157 158 #define MXC_F_SCN_SR_CCOV_POS 2 /**< SR_CCOV Position */ 159 #define MXC_F_SCN_SR_CCOV ((uint32_t)(0x1UL << MXC_F_SCN_SR_CCOV_POS)) /**< SR_CCOV Mask */ 160 161 #define MXC_F_SCN_SR_TXCF_POS 3 /**< SR_TXCF Position */ 162 #define MXC_F_SCN_SR_TXCF ((uint32_t)(0x1UL << MXC_F_SCN_SR_TXCF_POS)) /**< SR_TXCF Mask */ 163 164 #define MXC_F_SCN_SR_RXEMPTY_POS 4 /**< SR_RXEMPTY Position */ 165 #define MXC_F_SCN_SR_RXEMPTY ((uint32_t)(0x1UL << MXC_F_SCN_SR_RXEMPTY_POS)) /**< SR_RXEMPTY Mask */ 166 167 #define MXC_F_SCN_SR_RXFULL_POS 5 /**< SR_RXFULL Position */ 168 #define MXC_F_SCN_SR_RXFULL ((uint32_t)(0x1UL << MXC_F_SCN_SR_RXFULL_POS)) /**< SR_RXFULL Mask */ 169 170 #define MXC_F_SCN_SR_TXEMPTY_POS 6 /**< SR_TXEMPTY Position */ 171 #define MXC_F_SCN_SR_TXEMPTY ((uint32_t)(0x1UL << MXC_F_SCN_SR_TXEMPTY_POS)) /**< SR_TXEMPTY Mask */ 172 173 #define MXC_F_SCN_SR_TXFULL_POS 7 /**< SR_TXFULL Position */ 174 #define MXC_F_SCN_SR_TXFULL ((uint32_t)(0x1UL << MXC_F_SCN_SR_TXFULL_POS)) /**< SR_TXFULL Mask */ 175 176 #define MXC_F_SCN_SR_RXELT_POS 8 /**< SR_RXELT Position */ 177 #define MXC_F_SCN_SR_RXELT ((uint32_t)(0xFUL << MXC_F_SCN_SR_RXELT_POS)) /**< SR_RXELT Mask */ 178 179 #define MXC_F_SCN_SR_TXELT_POS 12 /**< SR_TXELT Position */ 180 #define MXC_F_SCN_SR_TXELT ((uint32_t)(0xFUL << MXC_F_SCN_SR_TXELT_POS)) /**< SR_TXELT Mask */ 181 182 /**@} end of group SCN_SR_Register */ 183 184 /** 185 * @ingroup scn_registers 186 * @defgroup SCN_PN SCN_PN 187 * @brief Pin Register, 188 * @{ 189 */ 190 #define MXC_F_SCN_PN_CRDRST_POS 0 /**< PN_CRDRST Position */ 191 #define MXC_F_SCN_PN_CRDRST ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDRST_POS)) /**< PN_CRDRST Mask */ 192 193 #define MXC_F_SCN_PN_CRDCLK_POS 1 /**< PN_CRDCLK Position */ 194 #define MXC_F_SCN_PN_CRDCLK ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDCLK_POS)) /**< PN_CRDCLK Mask */ 195 196 #define MXC_F_SCN_PN_CRDIO_POS 2 /**< PN_CRDIO Position */ 197 #define MXC_F_SCN_PN_CRDIO ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDIO_POS)) /**< PN_CRDIO Mask */ 198 199 #define MXC_F_SCN_PN_CRDC4_POS 3 /**< PN_CRDC4 Position */ 200 #define MXC_F_SCN_PN_CRDC4 ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDC4_POS)) /**< PN_CRDC4 Mask */ 201 202 #define MXC_F_SCN_PN_CRDC8_POS 4 /**< PN_CRDC8 Position */ 203 #define MXC_F_SCN_PN_CRDC8 ((uint32_t)(0x1UL << MXC_F_SCN_PN_CRDC8_POS)) /**< PN_CRDC8 Mask */ 204 205 #define MXC_F_SCN_PN_CLKSEL_POS 5 /**< PN_CLKSEL Position */ 206 #define MXC_F_SCN_PN_CLKSEL ((uint32_t)(0x1UL << MXC_F_SCN_PN_CLKSEL_POS)) /**< PN_CLKSEL Mask */ 207 208 /**@} end of group SCN_PN_Register */ 209 210 /** 211 * @ingroup scn_registers 212 * @defgroup SCN_ETUR SCN_ETUR 213 * @brief ETU Register. 214 * @{ 215 */ 216 #define MXC_F_SCN_ETUR_ETU_POS 0 /**< ETUR_ETU Position */ 217 #define MXC_F_SCN_ETUR_ETU ((uint32_t)(0x7FFFUL << MXC_F_SCN_ETUR_ETU_POS)) /**< ETUR_ETU Mask */ 218 219 #define MXC_F_SCN_ETUR_COMP_POS 15 /**< ETUR_COMP Position */ 220 #define MXC_F_SCN_ETUR_COMP ((uint32_t)(0x1UL << MXC_F_SCN_ETUR_COMP_POS)) /**< ETUR_COMP Mask */ 221 222 #define MXC_F_SCN_ETUR_HALF_POS 16 /**< ETUR_HALF Position */ 223 #define MXC_F_SCN_ETUR_HALF ((uint32_t)(0x1UL << MXC_F_SCN_ETUR_HALF_POS)) /**< ETUR_HALF Mask */ 224 225 /**@} end of group SCN_ETUR_Register */ 226 227 /** 228 * @ingroup scn_registers 229 * @defgroup SCN_GTR SCN_GTR 230 * @brief Guard Time Register. 231 * @{ 232 */ 233 #define MXC_F_SCN_GTR_GT_POS 0 /**< GTR_GT Position */ 234 #define MXC_F_SCN_GTR_GT ((uint32_t)(0xFFFFUL << MXC_F_SCN_GTR_GT_POS)) /**< GTR_GT Mask */ 235 236 /**@} end of group SCN_GTR_Register */ 237 238 /** 239 * @ingroup scn_registers 240 * @defgroup SCN_WT0R SCN_WT0R 241 * @brief Waiting Time 0 Register. 242 * @{ 243 */ 244 #define MXC_F_SCN_WT0R_WT_POS 0 /**< WT0R_WT Position */ 245 #define MXC_F_SCN_WT0R_WT ((uint32_t)(0xFFFFFFFFUL << MXC_F_SCN_WT0R_WT_POS)) /**< WT0R_WT Mask */ 246 247 /**@} end of group SCN_WT0R_Register */ 248 249 /** 250 * @ingroup scn_registers 251 * @defgroup SCN_WT1R SCN_WT1R 252 * @brief Waiting Time 1 Register. 253 * @{ 254 */ 255 #define MXC_F_SCN_WT1R_WT_POS 0 /**< WT1R_WT Position */ 256 #define MXC_F_SCN_WT1R_WT ((uint32_t)(0xFFUL << MXC_F_SCN_WT1R_WT_POS)) /**< WT1R_WT Mask */ 257 258 /**@} end of group SCN_WT1R_Register */ 259 260 /** 261 * @ingroup scn_registers 262 * @defgroup SCN_IER SCN_IER 263 * @brief Interrupt Enable Register. 264 * @{ 265 */ 266 #define MXC_F_SCN_IER_PARIE_POS 0 /**< IER_PARIE Position */ 267 #define MXC_F_SCN_IER_PARIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_PARIE_POS)) /**< IER_PARIE Mask */ 268 269 #define MXC_F_SCN_IER_WTIE_POS 1 /**< IER_WTIE Position */ 270 #define MXC_F_SCN_IER_WTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_WTIE_POS)) /**< IER_WTIE Mask */ 271 272 #define MXC_F_SCN_IER_CTIE_POS 2 /**< IER_CTIE Position */ 273 #define MXC_F_SCN_IER_CTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_CTIE_POS)) /**< IER_CTIE Mask */ 274 275 #define MXC_F_SCN_IER_TCIE_POS 3 /**< IER_TCIE Position */ 276 #define MXC_F_SCN_IER_TCIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_TCIE_POS)) /**< IER_TCIE Mask */ 277 278 #define MXC_F_SCN_IER_RXEIE_POS 4 /**< IER_RXEIE Position */ 279 #define MXC_F_SCN_IER_RXEIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_RXEIE_POS)) /**< IER_RXEIE Mask */ 280 281 #define MXC_F_SCN_IER_RXTIE_POS 5 /**< IER_RXTIE Position */ 282 #define MXC_F_SCN_IER_RXTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_RXTIE_POS)) /**< IER_RXTIE Mask */ 283 284 #define MXC_F_SCN_IER_RXFIE_POS 6 /**< IER_RXFIE Position */ 285 #define MXC_F_SCN_IER_RXFIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_RXFIE_POS)) /**< IER_RXFIE Mask */ 286 287 #define MXC_F_SCN_IER_TXEIE_POS 7 /**< IER_TXEIE Position */ 288 #define MXC_F_SCN_IER_TXEIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_TXEIE_POS)) /**< IER_TXEIE Mask */ 289 290 #define MXC_F_SCN_IER_TXTIE_POS 8 /**< IER_TXTIE Position */ 291 #define MXC_F_SCN_IER_TXTIE ((uint32_t)(0x1UL << MXC_F_SCN_IER_TXTIE_POS)) /**< IER_TXTIE Mask */ 292 293 /**@} end of group SCN_IER_Register */ 294 295 /** 296 * @ingroup scn_registers 297 * @defgroup SCN_ISR SCN_ISR 298 * @brief Interrupt Status Register. 299 * @{ 300 */ 301 #define MXC_F_SCN_ISR_PARIS_POS 0 /**< ISR_PARIS Position */ 302 #define MXC_F_SCN_ISR_PARIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_PARIS_POS)) /**< ISR_PARIS Mask */ 303 304 #define MXC_F_SCN_ISR_WTIS_POS 1 /**< ISR_WTIS Position */ 305 #define MXC_F_SCN_ISR_WTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_WTIS_POS)) /**< ISR_WTIS Mask */ 306 307 #define MXC_F_SCN_ISR_CTIS_POS 2 /**< ISR_CTIS Position */ 308 #define MXC_F_SCN_ISR_CTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_CTIS_POS)) /**< ISR_CTIS Mask */ 309 310 #define MXC_F_SCN_ISR_TCIS_POS 3 /**< ISR_TCIS Position */ 311 #define MXC_F_SCN_ISR_TCIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_TCIS_POS)) /**< ISR_TCIS Mask */ 312 313 #define MXC_F_SCN_ISR_RXEIS_POS 4 /**< ISR_RXEIS Position */ 314 #define MXC_F_SCN_ISR_RXEIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_RXEIS_POS)) /**< ISR_RXEIS Mask */ 315 316 #define MXC_F_SCN_ISR_RXTIS_POS 5 /**< ISR_RXTIS Position */ 317 #define MXC_F_SCN_ISR_RXTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_RXTIS_POS)) /**< ISR_RXTIS Mask */ 318 319 #define MXC_F_SCN_ISR_RXFIS_POS 6 /**< ISR_RXFIS Position */ 320 #define MXC_F_SCN_ISR_RXFIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_RXFIS_POS)) /**< ISR_RXFIS Mask */ 321 322 #define MXC_F_SCN_ISR_TXEIS_POS 7 /**< ISR_TXEIS Position */ 323 #define MXC_F_SCN_ISR_TXEIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_TXEIS_POS)) /**< ISR_TXEIS Mask */ 324 325 #define MXC_F_SCN_ISR_TXTIS_POS 8 /**< ISR_TXTIS Position */ 326 #define MXC_F_SCN_ISR_TXTIS ((uint32_t)(0x1UL << MXC_F_SCN_ISR_TXTIS_POS)) /**< ISR_TXTIS Mask */ 327 328 /**@} end of group SCN_ISR_Register */ 329 330 /** 331 * @ingroup scn_registers 332 * @defgroup SCN_TXR SCN_TXR 333 * @brief Transmit Register. 334 * @{ 335 */ 336 #define MXC_F_SCN_TXR_DATA_POS 0 /**< TXR_DATA Position */ 337 #define MXC_F_SCN_TXR_DATA ((uint32_t)(0xFFUL << MXC_F_SCN_TXR_DATA_POS)) /**< TXR_DATA Mask */ 338 339 /**@} end of group SCN_TXR_Register */ 340 341 /** 342 * @ingroup scn_registers 343 * @defgroup SCN_RXR SCN_RXR 344 * @brief Receive Register. 345 * @{ 346 */ 347 #define MXC_F_SCN_RXR_DATA_POS 0 /**< RXR_DATA Position */ 348 #define MXC_F_SCN_RXR_DATA ((uint32_t)(0xFFUL << MXC_F_SCN_RXR_DATA_POS)) /**< RXR_DATA Mask */ 349 350 #define MXC_F_SCN_RXR_PARER_POS 8 /**< RXR_PARER Position */ 351 #define MXC_F_SCN_RXR_PARER ((uint32_t)(0x1UL << MXC_F_SCN_RXR_PARER_POS)) /**< RXR_PARER Mask */ 352 353 /**@} end of group SCN_RXR_Register */ 354 355 /** 356 * @ingroup scn_registers 357 * @defgroup SCN_CCR SCN_CCR 358 * @brief Clock Counter Register, 359 * @{ 360 */ 361 #define MXC_F_SCN_CCR_CCYC_POS 0 /**< CCR_CCYC Position */ 362 #define MXC_F_SCN_CCR_CCYC ((uint32_t)(0xFFFFFFUL << MXC_F_SCN_CCR_CCYC_POS)) /**< CCR_CCYC Mask */ 363 364 #define MXC_F_SCN_CCR_MAN_POS 31 /**< CCR_MAN Position */ 365 #define MXC_F_SCN_CCR_MAN ((uint32_t)(0x1UL << MXC_F_SCN_CCR_MAN_POS)) /**< CCR_MAN Mask */ 366 367 /**@} end of group SCN_CCR_Register */ 368 369 #ifdef __cplusplus 370 } 371 #endif 372 373 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_SCN_REGS_H_ 374
