1<?xml version='1.0' encoding='utf-8'?> 2<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <vendor>Maxim-Integrated</vendor> 4 <vendorID>Maxim</vendorID> 5 <name>max32570</name> 6 <series>ARMCM4</series> 7 <version>1.0</version> 8 <description>MAX32570 32-bit ARM Cortex-M4 microcontroller, 1024KB of flash, 760KB of system RAM, 128KB of Boot ROM.</description> 9 <cpu> 10 <name>CM4</name> 11 <revision>r2p1</revision> 12 <endian>little</endian> 13 <mpuPresent>true</mpuPresent> 14 <fpuPresent>true</fpuPresent> 15 <nvicPrioBits>3</nvicPrioBits> 16 <vendorSystickConfig>false</vendorSystickConfig> 17 </cpu> 18 <addressUnitBits>8</addressUnitBits> 19 <width>32</width> 20 <size>0x20</size> 21 <access>read-write</access> 22 <resetValue>0x00000000</resetValue> 23 <resetMask>0xFFFFFFFF</resetMask> 24 <peripherals> 25 <peripheral> 26 <name>ADC</name> 27 <description>10-bit Analog to Digital Converter</description> 28 <baseAddress>0x40034000</baseAddress> 29 <size>32</size> 30 <access>read-write</access> 31 <addressBlock> 32 <offset>0</offset> 33 <size>0x1000</size> 34 <usage>registers</usage> 35 </addressBlock> 36 <interrupt> 37 <name>ADC</name> 38 <description>ADC IRQ</description> 39 <value>20</value> 40 </interrupt> 41 <registers> 42 <register> 43 <name>CTRL</name> 44 <description>ADC Control</description> 45 <addressOffset>0x0000</addressOffset> 46 <access>read-write</access> 47 <fields> 48 <field> 49 <name>START</name> 50 <description>Start ADC Conversion</description> 51 <bitRange>[0:0]</bitRange> 52 <access>read-write</access> 53 </field> 54 <field> 55 <name>PWR</name> 56 <description>ADC Power Up</description> 57 <bitRange>[1:1]</bitRange> 58 <access>read-write</access> 59 </field> 60 <field> 61 <name>REBUF_PWR</name> 62 <description>ADC Reference Buffer Power Up</description> 63 <bitRange>[3:3]</bitRange> 64 <access>read-write</access> 65 </field> 66 <field> 67 <name>CHGPUMP_PWR</name> 68 <description>ADC Charge Pump Power Up</description> 69 <bitRange>[4:4]</bitRange> 70 <access>read-write</access> 71 </field> 72 <field> 73 <name>REF_SCALE</name> 74 <description>ADC Reference Scale</description> 75 <bitRange>[8:8]</bitRange> 76 <access>read-write</access> 77 </field> 78 <field> 79 <name>SCALE</name> 80 <description>ADC Scale</description> 81 <bitRange>[9:9]</bitRange> 82 <access>read-write</access> 83 </field> 84 <field> 85 <name>CLK_EN</name> 86 <description>ADC Clock Enable</description> 87 <bitRange>[11:11]</bitRange> 88 <access>read-write</access> 89 </field> 90 <field> 91 <name>CH_SEL</name> 92 <description>ADC Channel Select</description> 93 <bitRange>[16:12]</bitRange> 94 <access>read-write</access> 95 <enumeratedValues> 96 <enumeratedValue> 97 <name>AIN0</name> 98 <value>0</value> 99 </enumeratedValue> 100 <enumeratedValue> 101 <name>AIN1</name> 102 <value>1</value> 103 </enumeratedValue> 104 <enumeratedValue> 105 <name>AIN2</name> 106 <value>2</value> 107 </enumeratedValue> 108 <enumeratedValue> 109 <name>AIN3</name> 110 <value>3</value> 111 </enumeratedValue> 112 <enumeratedValue> 113 <name>AIN4</name> 114 <value>4</value> 115 </enumeratedValue> 116 <enumeratedValue> 117 <name>AIN5</name> 118 <value>5</value> 119 </enumeratedValue> 120 <enumeratedValue> 121 <name>AIN6</name> 122 <value>6</value> 123 </enumeratedValue> 124 <enumeratedValue> 125 <name>AIN7</name> 126 <value>7</value> 127 </enumeratedValue> 128 <enumeratedValue> 129 <name>VcoreA</name> 130 <value>8</value> 131 </enumeratedValue> 132 <enumeratedValue> 133 <name>VcoreB</name> 134 <value>9</value> 135 </enumeratedValue> 136 <enumeratedValue> 137 <name>Vrxout</name> 138 <value>10</value> 139 </enumeratedValue> 140 <enumeratedValue> 141 <name>Vtxout</name> 142 <value>11</value> 143 </enumeratedValue> 144 <enumeratedValue> 145 <name>VddA</name> 146 <value>12</value> 147 </enumeratedValue> 148 <enumeratedValue> 149 <name>VddB</name> 150 <description>VddB/4</description> 151 <value>13</value> 152 </enumeratedValue> 153 <enumeratedValue> 154 <name>Vddio</name> 155 <description>Vddio/4</description> 156 <value>14</value> 157 </enumeratedValue> 158 <enumeratedValue> 159 <name>Vddioh</name> 160 <description>Vddioh/4</description> 161 <value>15</value> 162 </enumeratedValue> 163 <enumeratedValue> 164 <name>VregI</name> 165 <description>VregI/4</description> 166 <value>16</value> 167 </enumeratedValue> 168 </enumeratedValues> 169 </field> 170 <field> 171 <name>ADC_DIVSEL</name> 172 <description>Scales the external inputs, all inputs are scaled the same</description> 173 <bitRange>[18:17]</bitRange> 174 <access>read-write</access> 175 <enumeratedValues> 176 <enumeratedValue> 177 <name>DIV1</name> 178 <value>0</value> 179 </enumeratedValue> 180 <enumeratedValue> 181 <name>DIV2</name> 182 <value>1</value> 183 </enumeratedValue> 184 <enumeratedValue> 185 <name>DIV3</name> 186 <value>2</value> 187 </enumeratedValue> 188 <enumeratedValue> 189 <name>DIV4</name> 190 <value>3</value> 191 </enumeratedValue> 192 </enumeratedValues> 193 </field> 194 <field> 195 <name>DATA_ALIGN</name> 196 <description>ADC Data Alignment Select</description> 197 <bitRange>[20:20]</bitRange> 198 <access>read-write</access> 199 </field> 200 </fields> 201 </register> 202 <register> 203 <name>STATUS</name> 204 <description>ADC Status</description> 205 <addressOffset>0x0004</addressOffset> 206 <access>read-write</access> 207 <fields> 208 <field> 209 <name>ACTIVE</name> 210 <description>ADC Conversion In Progress</description> 211 <bitRange>[0:0]</bitRange> 212 <access>read-only</access> 213 </field> 214 <field> 215 <name>AFE_PWR_UP_ACTIVE</name> 216 <description>AFE Power Up Delay Active</description> 217 <bitRange>[2:2]</bitRange> 218 <access>read-only</access> 219 </field> 220 <field> 221 <name>OVERFLOW</name> 222 <description>ADC Overflow</description> 223 <bitRange>[3:3]</bitRange> 224 <access>read-only</access> 225 </field> 226 </fields> 227 </register> 228 <register> 229 <name>DATA</name> 230 <description>ADC Output Data</description> 231 <addressOffset>0x0008</addressOffset> 232 <access>read-write</access> 233 <fields> 234 <field> 235 <name>DATA</name> 236 <description>ADC Converted Sample Data Output</description> 237 <bitRange>[15:0]</bitRange> 238 <access>read-only</access> 239 </field> 240 </fields> 241 </register> 242 <register> 243 <name>INTR</name> 244 <description>ADC Interrupt Control Register</description> 245 <addressOffset>0x000C</addressOffset> 246 <access>read-write</access> 247 <fields> 248 <field> 249 <name>DONE_IE</name> 250 <description>ADC Done Interrupt Enable</description> 251 <bitRange>[0:0]</bitRange> 252 <access>read-write</access> 253 </field> 254 <field> 255 <name>REF_READY_IE</name> 256 <description>ADC Reference Ready Interrupt Enable</description> 257 <bitRange>[1:1]</bitRange> 258 <access>read-write</access> 259 </field> 260 <field> 261 <name>HI_LIMIT_IE</name> 262 <description>ADC Hi Limit Monitor Interrupt Enable</description> 263 <bitRange>[2:2]</bitRange> 264 <access>read-write</access> 265 </field> 266 <field> 267 <name>LO_LIMIT_IE</name> 268 <description>ADC Lo Limit Monitor Interrupt Enable</description> 269 <bitRange>[3:3]</bitRange> 270 <access>read-write</access> 271 </field> 272 <field> 273 <name>OVERFLOW_IE</name> 274 <description>ADC Overflow Interrupt Enable</description> 275 <bitRange>[4:4]</bitRange> 276 <access>read-write</access> 277 </field> 278 <field> 279 <name>DONE_IF</name> 280 <description>ADC Done Interrupt Flag</description> 281 <bitRange>[16:16]</bitRange> 282 <access>read-write</access> 283 <modifiedWriteValues>oneToClear</modifiedWriteValues> 284 </field> 285 <field> 286 <name>REF_READY_IF</name> 287 <description>ADC Reference Ready Interrupt Flag</description> 288 <bitRange>[17:17]</bitRange> 289 <access>read-write</access> 290 <modifiedWriteValues>oneToClear</modifiedWriteValues> 291 </field> 292 <field> 293 <name>HI_LIMIT_IF</name> 294 <description>ADC Hi Limit Monitor Interrupt Flag</description> 295 <bitRange>[18:18]</bitRange> 296 <access>read-write</access> 297 <modifiedWriteValues>oneToClear</modifiedWriteValues> 298 </field> 299 <field> 300 <name>LO_LIMIT_IF</name> 301 <description>ADC Lo Limit Monitor Interrupt Flag</description> 302 <bitRange>[19:19]</bitRange> 303 <access>read-write</access> 304 <modifiedWriteValues>oneToClear</modifiedWriteValues> 305 </field> 306 <field> 307 <name>OVERFLOW_IF</name> 308 <description>ADC Overflow Interrupt Flag</description> 309 <bitRange>[20:20]</bitRange> 310 <access>read-write</access> 311 <modifiedWriteValues>oneToClear</modifiedWriteValues> 312 </field> 313 <field> 314 <name>PENDING</name> 315 <description>ADC Interrupt Pending Status</description> 316 <bitRange>[22:22]</bitRange> 317 <access>read-only</access> 318 </field> 319 </fields> 320 </register> 321 <register> 322 <dim>4</dim> 323 <dimIncrement>4</dimIncrement> 324 <name>LIMIT[%s]</name> 325 <description>ADC Limit</description> 326 <addressOffset>0x0010</addressOffset> 327 <access>read-write</access> 328 <fields> 329 <field> 330 <name>CH_LO_LIMIT</name> 331 <description>Low Limit Threshold</description> 332 <bitRange>[9:0]</bitRange> 333 <access>read-write</access> 334 </field> 335 <field> 336 <name>CH_HI_LIMIT</name> 337 <description>High Limit Threshold</description> 338 <bitRange>[21:12]</bitRange> 339 <access>read-write</access> 340 </field> 341 <field> 342 <name>CH_SEL</name> 343 <description>ADC Channel Select</description> 344 <bitRange>[28:24]</bitRange> 345 <access>read-write</access> 346 </field> 347 <field> 348 <name>CH_LO_LIMIT_EN</name> 349 <description>Low Limit Monitoring Enable</description> 350 <bitRange>[29:29]</bitRange> 351 <access>read-write</access> 352 </field> 353 <field> 354 <name>CH_HI_LIMIT_EN</name> 355 <description>High Limit Monitoring Enable</description> 356 <bitRange>[30:30]</bitRange> 357 <access>read-write</access> 358 </field> 359 </fields> 360 </register> 361 </registers> 362 </peripheral> 363<!--ADC 10-bit Analog to Digital Converter--> 364 <peripheral> 365 <name>ADC9</name> 366 <description>Magnetic Strip Reader - 9 bit ADC</description> 367 <baseAddress>0x4002B000</baseAddress> 368 <size>32</size> 369 <access>read-write</access> 370 <addressBlock> 371 <offset>0</offset> 372 <size>0x1000</size> 373 <usage>registers</usage> 374 </addressBlock> 375 <interrupt> 376 <name>ADC9</name> 377 <description>ADC IRQ</description> 378 <value>22</value> 379 </interrupt> 380 <registers> 381 <register> 382 <name>CFG</name> 383 <description>ADC Control</description> 384 <addressOffset>0x0000</addressOffset> 385 <access>read-write</access> 386 <fields> 387 <field> 388 <name>CLKDIV</name> 389 <description>ADC Clock Divider.</description> 390 <bitRange>[7:0]</bitRange> 391 <access>read-write</access> 392 </field> 393 <field> 394 <name>ACHSEL</name> 395 <description>A Channel ADC Input Pin Selection.</description> 396 <bitRange>[10:8]</bitRange> 397 <access>read-write</access> 398 <enumeratedValues> 399 <enumeratedValue> 400 <name>INVALID_000</name> 401 <value>0</value> 402 </enumeratedValue> 403 <enumeratedValue> 404 <name>IN0</name> 405 <value>1</value> 406 </enumeratedValue> 407 <enumeratedValue> 408 <name>IN1</name> 409 <value>2</value> 410 </enumeratedValue> 411 <enumeratedValue> 412 <name>IN2</name> 413 <value>3</value> 414 </enumeratedValue> 415 <enumeratedValue> 416 <name>IN3</name> 417 <value>4</value> 418 </enumeratedValue> 419 <enumeratedValue> 420 <name>IN4</name> 421 <value>5</value> 422 </enumeratedValue> 423 <enumeratedValue> 424 <name>IN5</name> 425 <value>6</value> 426 </enumeratedValue> 427 <enumeratedValue> 428 <name>INVALID_111</name> 429 <value>7</value> 430 </enumeratedValue> 431 </enumeratedValues> 432 </field> 433 <field derivedFrom="ACHSEL"> 434 <name>BCHSEL</name> 435 <description>B Channel ADC Input Pin Selection.</description> 436 <bitRange>[13:11]</bitRange> 437 <access>read-write</access> 438 </field> 439 <field derivedFrom="ACHSEL"> 440 <name>CCHSEL</name> 441 <description>C Channel ADC Input Pin Selection.</description> 442 <bitRange>[16:14]</bitRange> 443 <access>read-write</access> 444 </field> 445 <field derivedFrom="ACHSEL"> 446 <name>DCHSEL</name> 447 <description>D Channel ADC Input Pin Selection.</description> 448 <bitRange>[19:17]</bitRange> 449 <access>read-write</access> 450 </field> 451 <field derivedFrom="ACHSEL"> 452 <name>ECHSEL</name> 453 <description>E Channel ADC Input Pin Selection.</description> 454 <bitRange>[22:20]</bitRange> 455 <access>read-write</access> 456 </field> 457 <field derivedFrom="ACHSEL"> 458 <name>FCHSEL</name> 459 <description>F Channel ADC Input Pin Selection.</description> 460 <bitRange>[25:23]</bitRange> 461 <access>read-write</access> 462 </field> 463 <field derivedFrom="ACHSEL"> 464 <name>GCHSEL</name> 465 <description>G Channel ADC Input Pin Selection.</description> 466 <bitRange>[28:26]</bitRange> 467 <access>read-write</access> 468 </field> 469 <field derivedFrom="ACHSEL"> 470 <name>HCHSEL</name> 471 <description>H Channel ADC Input Pin Selection.</description> 472 <bitRange>[31:29]</bitRange> 473 <access>read-write</access> 474 </field> 475 </fields> 476 </register> 477 <register> 478 <name>CMD</name> 479 <description>MSRADC Command</description> 480 <addressOffset>0x0004</addressOffset> 481 <access>read-write</access> 482 <fields> 483 <field> 484 <name>RST</name> 485 <description>ADC Reset.</description> 486 <bitRange>[0:0]</bitRange> 487 <access>read-write</access> 488 <enumeratedValues> 489 <enumeratedValue> 490 <name>NO_RESET</name> 491 <value>0</value> 492 </enumeratedValue> 493 <enumeratedValue> 494 <name>RESET</name> 495 <value>1</value> 496 </enumeratedValue> 497 </enumeratedValues> 498 </field> 499 <field> 500 <name>SNGLSMPL</name> 501 <description>Single Sample Mode.</description> 502 <bitRange>[1:1]</bitRange> 503 <access>read-write</access> 504 <enumeratedValues> 505 <enumeratedValue> 506 <name>NO_EFFECT</name> 507 <value>0</value> 508 </enumeratedValue> 509 <enumeratedValue> 510 <name>SINGLE_SMPL</name> 511 <value>1</value> 512 </enumeratedValue> 513 </enumeratedValues> 514 </field> 515 <field> 516 <name>CONTSMPL</name> 517 <description>Continuous Sample Mode Enable.</description> 518 <bitRange>[2:2]</bitRange> 519 <access>read-write</access> 520 <enumeratedValues> 521 <enumeratedValue> 522 <name>NO_CONTINUOUS_SMPL_MODE</name> 523 <value>0</value> 524 </enumeratedValue> 525 <enumeratedValue> 526 <name>CONTINUOUS_SMPL_MODE</name> 527 <value>1</value> 528 </enumeratedValue> 529 </enumeratedValues> 530 </field> 531 <field> 532 <name>ROTLIMIT</name> 533 <description>Rotation Limit.</description> 534 <bitRange>[6:4]</bitRange> 535 <access>read-write</access> 536 <enumeratedValues> 537 <enumeratedValue> 538 <name>1_channel</name> 539 <value>0</value> 540 </enumeratedValue> 541 <enumeratedValue> 542 <name>2_channels</name> 543 <value>1</value> 544 </enumeratedValue> 545 <enumeratedValue> 546 <name>3_channels</name> 547 <value>2</value> 548 </enumeratedValue> 549 <enumeratedValue> 550 <name>4_channels</name> 551 <value>3</value> 552 </enumeratedValue> 553 <enumeratedValue> 554 <name>5_channels</name> 555 <value>4</value> 556 </enumeratedValue> 557 <enumeratedValue> 558 <name>6_channels</name> 559 <value>5</value> 560 </enumeratedValue> 561 <enumeratedValue> 562 <name>7_channels</name> 563 <value>6</value> 564 </enumeratedValue> 565 <enumeratedValue> 566 <name>8_channels</name> 567 <value>7</value> 568 </enumeratedValue> 569 </enumeratedValues> 570 </field> 571 <field> 572 <name>CLKSEL</name> 573 <description>Clock Select.</description> 574 <bitRange>[10:8]</bitRange> 575 <access>read-write</access> 576 <enumeratedValues> 577 <enumeratedValue> 578 <name>3_samples</name> 579 <value>0</value> 580 </enumeratedValue> 581 <enumeratedValue> 582 <name>5_samples</name> 583 <value>1</value> 584 </enumeratedValue> 585 <enumeratedValue> 586 <name>4_samples</name> 587 <value>2</value> 588 </enumeratedValue> 589 <enumeratedValue> 590 <name>8_samples</name> 591 <value>3</value> 592 </enumeratedValue> 593 <enumeratedValue> 594 <name>16_samples</name> 595 <value>4</value> 596 </enumeratedValue> 597 <enumeratedValue> 598 <name>32_samples</name> 599 <value>5</value> 600 </enumeratedValue> 601 <enumeratedValue> 602 <name>64_samples</name> 603 <value>6</value> 604 </enumeratedValue> 605 <enumeratedValue> 606 <name>128_samples</name> 607 <value>7</value> 608 </enumeratedValue> 609 </enumeratedValues> 610 </field> 611 </fields> 612 </register> 613 <register> 614 <name>FIFO</name> 615 <description>ADC FIFO</description> 616 <addressOffset>0x0008</addressOffset> 617 <access>read-write</access> 618 <fields> 619 <field> 620 <name>SAMPLE</name> 621 <description>ADC Converted Sample Data Output</description> 622 <bitRange>[8:0]</bitRange> 623 <access>read-only</access> 624 </field> 625 <field> 626 <name>SMPLIN</name> 627 <description>ADC Sample Pin</description> 628 <bitRange>[11:9]</bitRange> 629 <access>read-only</access> 630 <enumeratedValues> 631 <enumeratedValue> 632 <name>INVALID_000</name> 633 <value>0</value> 634 </enumeratedValue> 635 <enumeratedValue> 636 <name>IN0</name> 637 <value>1</value> 638 </enumeratedValue> 639 <enumeratedValue> 640 <name>IN1</name> 641 <value>2</value> 642 </enumeratedValue> 643 <enumeratedValue> 644 <name>IN2</name> 645 <value>3</value> 646 </enumeratedValue> 647 <enumeratedValue> 648 <name>IN3</name> 649 <value>4</value> 650 </enumeratedValue> 651 <enumeratedValue> 652 <name>IN4</name> 653 <value>5</value> 654 </enumeratedValue> 655 <enumeratedValue> 656 <name>IN5</name> 657 <value>6</value> 658 </enumeratedValue> 659 <enumeratedValue> 660 <name>INVALID_111</name> 661 <value>7</value> 662 </enumeratedValue> 663 </enumeratedValues> 664 </field> 665 </fields> 666 </register> 667 <register> 668 <name>INTR</name> 669 <description>ADC Interrupt Enable Register</description> 670 <addressOffset>0x000C</addressOffset> 671 <access>read-write</access> 672 <fields> 673 <field> 674 <name>FIFOLVL</name> 675 <description>Set FIFO Interrupt Level.</description> 676 <bitRange>[2:0]</bitRange> 677 <access>read-write</access> 678 <enumeratedValues> 679 <enumeratedValue> 680 <name>at_least_1</name> 681 <value>0</value> 682 </enumeratedValue> 683 <enumeratedValue> 684 <name>at_least_2</name> 685 <value>1</value> 686 </enumeratedValue> 687 <enumeratedValue> 688 <name>at_least_3</name> 689 <value>2</value> 690 </enumeratedValue> 691 <enumeratedValue> 692 <name>at_least_4</name> 693 <value>3</value> 694 </enumeratedValue> 695 <enumeratedValue> 696 <name>at_least_5</name> 697 <value>4</value> 698 </enumeratedValue> 699 <enumeratedValue> 700 <name>at_least_6</name> 701 <value>5</value> 702 </enumeratedValue> 703 <enumeratedValue> 704 <name>at_least_7</name> 705 <value>6</value> 706 </enumeratedValue> 707 <enumeratedValue> 708 <name>at_least_8</name> 709 <value>7</value> 710 </enumeratedValue> 711 </enumeratedValues> 712 </field> 713 <field> 714 <name>DMAREQEN</name> 715 <description>DMA Request Enable.</description> 716 <bitRange>[3:3]</bitRange> 717 <access>read-write</access> 718 <enumeratedValues> 719 <enumeratedValue> 720 <name>DISABLED</name> 721 <value>0</value> 722 </enumeratedValue> 723 <enumeratedValue> 724 <name>ENABLED</name> 725 <value>1</value> 726 </enumeratedValue> 727 </enumeratedValues> 728 </field> 729 <field> 730 <name>OVERFIE</name> 731 <description>FIFO Overflow Interrupt Enable.</description> 732 <bitRange>[6:6]</bitRange> 733 <access>read-write</access> 734 <enumeratedValues> 735 <enumeratedValue> 736 <name>DISABLED</name> 737 <value>0</value> 738 </enumeratedValue> 739 <enumeratedValue> 740 <name>ENABLED</name> 741 <value>1</value> 742 </enumeratedValue> 743 </enumeratedValues> 744 </field> 745 <field> 746 <name>UNDRFIE</name> 747 <description>FIFO Underflow Interrupt Enable.</description> 748 <bitRange>[7:7]</bitRange> 749 <access>read-write</access> 750 <enumeratedValues> 751 <enumeratedValue> 752 <name>DISABLED</name> 753 <value>0</value> 754 </enumeratedValue> 755 <enumeratedValue> 756 <name>ENABLED</name> 757 <value>1</value> 758 </enumeratedValue> 759 </enumeratedValues> 760 </field> 761 <field> 762 <name>FIFOLVLIE</name> 763 <description>FIFO Level Interrupt Enable.</description> 764 <bitRange>[8:8]</bitRange> 765 <access>read-write</access> 766 <enumeratedValues> 767 <enumeratedValue> 768 <name>DISABLED</name> 769 <value>0</value> 770 </enumeratedValue> 771 <enumeratedValue> 772 <name>ENABLED</name> 773 <value>1</value> 774 </enumeratedValue> 775 </enumeratedValues> 776 </field> 777 <field> 778 <name>GLOBIE</name> 779 <description>ADC Global Interrupt Enable.</description> 780 <bitRange>[9:9]</bitRange> 781 <access>read-write</access> 782 <enumeratedValues> 783 <enumeratedValue> 784 <name>DISABLED</name> 785 <value>0</value> 786 </enumeratedValue> 787 <enumeratedValue> 788 <name>ENABLED</name> 789 <value>1</value> 790 </enumeratedValue> 791 </enumeratedValues> 792 </field> 793 </fields> 794 </register> 795 <register> 796 <name>STAT</name> 797 <description>ADC Interrupt Flag Register.</description> 798 <access>read-write</access> 799 <addressOffset>0x0010</addressOffset> 800 <fields> 801 <field> 802 <name>FIFOCNT</name> 803 <description>FIFO Count.</description> 804 <bitRange>[3:0]</bitRange> 805 <access>read-only</access> 806 <enumeratedValues> 807 <enumeratedValue> 808 <name>FIFO_EMPTY</name> 809 <value>0</value> 810 </enumeratedValue> 811 <enumeratedValue> 812 <name>ONE_SAMPLE</name> 813 <value>1</value> 814 </enumeratedValue> 815 <enumeratedValue> 816 <name>TWO_SAMPLE</name> 817 <value>2</value> 818 </enumeratedValue> 819 <enumeratedValue> 820 <name>THREE_SAMPLE</name> 821 <value>3</value> 822 </enumeratedValue> 823 <enumeratedValue> 824 <name>FOUR_SAMPLE</name> 825 <value>4</value> 826 </enumeratedValue> 827 <enumeratedValue> 828 <name>FIVE_SAMPLE</name> 829 <value>5</value> 830 </enumeratedValue> 831 <enumeratedValue> 832 <name>SIX_SAMPLE</name> 833 <value>6</value> 834 </enumeratedValue> 835 <enumeratedValue> 836 <name>SEVEN_SAMPLE</name> 837 <value>7</value> 838 </enumeratedValue> 839 <enumeratedValue> 840 <name>EIGHT_SAMPLE</name> 841 <value>8</value> 842 </enumeratedValue> 843 </enumeratedValues> 844 </field> 845 <field> 846 <name>FULL</name> 847 <description>FIFO Full Status.</description> 848 <bitRange>[4:4]</bitRange> 849 <access>read-only</access> 850 <enumeratedValues> 851 <enumeratedValue> 852 <name>FIFO_NOT_FULL</name> 853 <value>0</value> 854 </enumeratedValue> 855 <enumeratedValue> 856 <name>FIFO_FULL</name> 857 <value>1</value> 858 </enumeratedValue> 859 </enumeratedValues> 860 </field> 861 <field> 862 <name>EMPTY</name> 863 <description>FIFO Empty Status.</description> 864 <bitRange>[5:5]</bitRange> 865 <access>read-only</access> 866 <enumeratedValues> 867 <enumeratedValue> 868 <name>FIFO_NOT_EMPTY</name> 869 <value>0</value> 870 </enumeratedValue> 871 <enumeratedValue> 872 <name>FIFO_EMPTY</name> 873 <value>1</value> 874 </enumeratedValue> 875 </enumeratedValues> 876 </field> 877 <field> 878 <name>OVERFINT</name> 879 <description>FIFO Overflow Status.</description> 880 <bitRange>[6:6]</bitRange> 881 <access>read-only</access> 882 <enumeratedValues> 883 <enumeratedValue> 884 <name>NOT_FIFO_OVERFLOW</name> 885 <value>0</value> 886 </enumeratedValue> 887 <enumeratedValue> 888 <name>FIFO_OVERFLOW</name> 889 <value>1</value> 890 </enumeratedValue> 891 </enumeratedValues> 892 </field> 893 <field> 894 <name>UNDRFINT</name> 895 <description>FIFO Underflow Status.</description> 896 <bitRange>[7:7]</bitRange> 897 <access>read-only</access> 898 <enumeratedValues> 899 <enumeratedValue> 900 <name>NOT_FIFO_UNDERFLOW</name> 901 <value>0</value> 902 </enumeratedValue> 903 <enumeratedValue> 904 <name>FIFO_UNDERFLOW</name> 905 <value>1</value> 906 </enumeratedValue> 907 </enumeratedValues> 908 </field> 909 <field> 910 <name>FIFOLVLST</name> 911 <description>FIFO Level Status.</description> 912 <bitRange>[8:8]</bitRange> 913 <access>read-only</access> 914 <enumeratedValues> 915 <enumeratedValue> 916 <name>BELOW_LVL</name> 917 <value>0</value> 918 </enumeratedValue> 919 <enumeratedValue> 920 <name>ABOVE_LVL</name> 921 <value>1</value> 922 </enumeratedValue> 923 </enumeratedValues> 924 </field> 925 <field> 926 <name>GLOBINT</name> 927 <description>ADC Global Interrupt Status.</description> 928 <bitRange>[9:9]</bitRange> 929 <access>read-only</access> 930 <enumeratedValues> 931 <enumeratedValue> 932 <name>NOT_ACTIVE</name> 933 <value>0</value> 934 </enumeratedValue> 935 <enumeratedValue> 936 <name>ACTIVE</name> 937 <value>1</value> 938 </enumeratedValue> 939 </enumeratedValues> 940 </field> 941 </fields> 942 </register> 943 </registers> 944 </peripheral> 945<!--ADC9 Magnetic Strip Reader - 9 bit ADC--> 946 <peripheral> 947 <name>AES</name> 948 <description>AES Keys.</description> 949 <baseAddress>0x40005000</baseAddress> 950 <addressBlock> 951 <offset>0x00</offset> 952 <size>0x400</size> 953 <usage>registers</usage> 954 </addressBlock> 955 <registers> 956 <register> 957 <name>AES_SRAM_KEY</name> 958 <description>AES SRAM KEY</description> 959 <addressOffset>0x000</addressOffset> 960 <size>32</size> 961 </register> 962 <register> 963 <name>AES_CODE_KEY</name> 964 <description>AES CODE Key </description> 965 <addressOffset>0x080</addressOffset> 966 </register> 967 <register> 968 <name>AES_DATA_KEY</name> 969 <description>AES DATA KEY</description> 970 <addressOffset>0x100</addressOffset> 971 </register> 972 </registers> 973 </peripheral> 974<!--AES AES Keys.--> 975 <peripheral> 976 <name>CAMERAIF</name> 977 <description>Parallel Camera Interface.</description> 978 <baseAddress>0x4000E000</baseAddress> 979 <size>32</size> 980 <access>read-write</access> 981 <addressBlock> 982 <offset>0</offset> 983 <size>0x1000</size> 984 <usage>registers</usage> 985 </addressBlock> 986 <interrupt> 987 <name>CameraIF</name> 988 <value>91</value> 989 </interrupt> 990 <registers> 991 <register> 992 <name>VER</name> 993 <description>Hardware Version.</description> 994 <addressOffset>0x0000</addressOffset> 995 <access>read-write</access> 996 <fields> 997 <field> 998 <name>minor</name> 999 <description>Minor Version Number.</description> 1000 <bitRange>[7:0]</bitRange> 1001 <access>read-write</access> 1002 </field> 1003 <field> 1004 <name>major</name> 1005 <description>Major Version Number.</description> 1006 <bitRange>[15:8]</bitRange> 1007 <access>read-write</access> 1008 </field> 1009 </fields> 1010 </register> 1011 <register> 1012 <name>FIFO_SIZE</name> 1013 <description>FIFO Depth.</description> 1014 <addressOffset>0x0004</addressOffset> 1015 <access>read-write</access> 1016 <fields> 1017 <field> 1018 <name>fifo_size</name> 1019 <description>FIFO size.</description> 1020 <bitRange>[7:0]</bitRange> 1021 <access>read-write</access> 1022 </field> 1023 </fields> 1024 </register> 1025 <register> 1026 <name>CTRL</name> 1027 <description>Control Register.</description> 1028 <addressOffset>0x0008</addressOffset> 1029 <access>read-write</access> 1030 <fields> 1031 <field> 1032 <name>READ_MODE</name> 1033 <description>Read Mode.</description> 1034 <bitOffset>0</bitOffset> 1035 <bitWidth>2</bitWidth> 1036 <access>read-write</access> 1037 <enumeratedValues> 1038 <enumeratedValue> 1039 <name>dis</name> 1040 <description>Camera Interface Disabled.</description> 1041 <value>0</value> 1042 </enumeratedValue> 1043 <enumeratedValue> 1044 <name>single_img</name> 1045 <description>Single Image Capture.</description> 1046 <value>1</value> 1047 </enumeratedValue> 1048 <enumeratedValue> 1049 <name>continuous</name> 1050 <description>Continuous Image Capture.</description> 1051 <value>2</value> 1052 </enumeratedValue> 1053 </enumeratedValues> 1054 </field> 1055 <field> 1056 <name>DATA_WIDTH</name> 1057 <description>Data Width.</description> 1058 <bitOffset>2</bitOffset> 1059 <bitWidth>2</bitWidth> 1060 <access>read-write</access> 1061 <enumeratedValues> 1062 <enumeratedValue> 1063 <name>8bit</name> 1064 <description>8 bit.</description> 1065 <value>0</value> 1066 </enumeratedValue> 1067 <enumeratedValue> 1068 <name>10bit</name> 1069 <description>10 bit.</description> 1070 <value>1</value> 1071 </enumeratedValue> 1072 <enumeratedValue> 1073 <name>12bit</name> 1074 <description>12 bit.</description> 1075 <value>2</value> 1076 </enumeratedValue> 1077 </enumeratedValues> 1078 </field> 1079 <field> 1080 <name>DS_TIMING_EN</name> 1081 <description>DS Timing Enable.</description> 1082 <bitOffset>4</bitOffset> 1083 <bitWidth>1</bitWidth> 1084 <access>read-write</access> 1085 <enumeratedValues> 1086 <enumeratedValue> 1087 <name>dis</name> 1088 <description>Timing from VSYNC and HSYNC.</description> 1089 <value>0</value> 1090 </enumeratedValue> 1091 <enumeratedValue> 1092 <name>en</name> 1093 <description>Timing embedded in data using SAV and EAV codes.</description> 1094 <value>1</value> 1095 </enumeratedValue> 1096 </enumeratedValues> 1097 </field> 1098 <field> 1099 <name>FIFO_THRSH</name> 1100 <description>Data FIFO Threshold.</description> 1101 <bitOffset>5</bitOffset> 1102 <bitWidth>5</bitWidth> 1103 <access>read-write</access> 1104 </field> 1105 <field> 1106 <name>RX_DMA</name> 1107 <description>DMA Enable.</description> 1108 <bitOffset>16</bitOffset> 1109 <bitWidth>1</bitWidth> 1110 <access>read-write</access> 1111 <enumeratedValues> 1112 <enumeratedValue> 1113 <name>dis</name> 1114 <description>DMA disabled.</description> 1115 <value>0</value> 1116 </enumeratedValue> 1117 <enumeratedValue> 1118 <name>en</name> 1119 <description>DMA enabled.</description> 1120 <value>1</value> 1121 </enumeratedValue> 1122 </enumeratedValues> 1123 </field> 1124 <field> 1125 <name>RX_DMA_THRSH</name> 1126 <description>DMA Threshold.</description> 1127 <bitOffset>17</bitOffset> 1128 <bitWidth>4</bitWidth> 1129 <access>read-write</access> 1130 </field> 1131 <field> 1132 <name>THREE_CH_EN</name> 1133 <description>Three-channel mode enable.</description> 1134 <bitOffset>30</bitOffset> 1135 <bitWidth>1</bitWidth> 1136 <access>read-write</access> 1137 </field> 1138 <field> 1139 <name>PCIF_SYS</name> 1140 <description>PCIF Control.</description> 1141 <bitOffset>31</bitOffset> 1142 <bitWidth>1</bitWidth> 1143 <access>read-write</access> 1144 <enumeratedValues> 1145 <enumeratedValue> 1146 <name>dis</name> 1147 <description>PCIF disabled.</description> 1148 <value>0</value> 1149 </enumeratedValue> 1150 <enumeratedValue> 1151 <name>en</name> 1152 <description>PCIF enabled.</description> 1153 <value>1</value> 1154 </enumeratedValue> 1155 </enumeratedValues> 1156 </field> 1157 </fields> 1158 </register> 1159 <register> 1160 <name>INT_EN</name> 1161 <description>Interupt Enable Register.</description> 1162 <addressOffset>0x000C</addressOffset> 1163 <access>read-write</access> 1164 <fields> 1165 <field> 1166 <name>IMG_DONE</name> 1167 <description>Image Done.</description> 1168 <bitOffset>0</bitOffset> 1169 <bitWidth>1</bitWidth> 1170 <access>read-write</access> 1171 </field> 1172 <field> 1173 <name>FIFO_FULL</name> 1174 <description>FIFO Full.</description> 1175 <bitOffset>1</bitOffset> 1176 <bitWidth>1</bitWidth> 1177 <access>read-write</access> 1178 </field> 1179 <field> 1180 <name>FIFO_THRESH</name> 1181 <description>FIFO Threshold Level Met.</description> 1182 <bitOffset>2</bitOffset> 1183 <bitWidth>1</bitWidth> 1184 <access>read-write</access> 1185 </field> 1186 <field> 1187 <name>FIFO_NOT_EMPTY</name> 1188 <description>FIFO Not Empty.</description> 1189 <bitOffset>3</bitOffset> 1190 <bitWidth>1</bitWidth> 1191 <access>read-write</access> 1192 </field> 1193 </fields> 1194 </register> 1195 <register> 1196 <name>INT_FL</name> 1197 <description>Interupt Flag Register.</description> 1198 <addressOffset>0x0010</addressOffset> 1199 <access>read-write</access> 1200 <fields> 1201 <field> 1202 <name>IMG_DONE</name> 1203 <description>Image Done.</description> 1204 <bitOffset>0</bitOffset> 1205 <bitWidth>1</bitWidth> 1206 <access>read-write</access> 1207 </field> 1208 <field> 1209 <name>FIFO_FULL</name> 1210 <description>FIFO Full.</description> 1211 <bitOffset>1</bitOffset> 1212 <bitWidth>1</bitWidth> 1213 <access>read-write</access> 1214 </field> 1215 <field> 1216 <name>FIFO_THRESH</name> 1217 <description>FIFO Threshold Level Met.</description> 1218 <bitOffset>2</bitOffset> 1219 <bitWidth>1</bitWidth> 1220 <access>read-write</access> 1221 </field> 1222 <field> 1223 <name>FIFO_NOT_EMPTY</name> 1224 <description>FIFO Not Empty.</description> 1225 <bitOffset>3</bitOffset> 1226 <bitWidth>1</bitWidth> 1227 <access>read-write</access> 1228 </field> 1229 </fields> 1230 </register> 1231 <register> 1232 <name>DS_TIMING_CODES</name> 1233 <description>DS Timing Code Register.</description> 1234 <addressOffset>0x0014</addressOffset> 1235 <access>read-write</access> 1236 <fields> 1237 <field> 1238 <name>SAV</name> 1239 <description>Start Active Video Code.</description> 1240 <bitRange>[7:0]</bitRange> 1241 <access>read-write</access> 1242 </field> 1243 <field> 1244 <name>EAV</name> 1245 <description>End Active Video Code.</description> 1246 <bitRange>[15:8]</bitRange> 1247 <access>read-write</access> 1248 </field> 1249 </fields> 1250 </register> 1251 <register> 1252 <name>FIFO_DATA</name> 1253 <description>FIFO DATA Register.</description> 1254 <addressOffset>0x0030</addressOffset> 1255 <access>read-write</access> 1256 <fields> 1257 <field> 1258 <name>DATA</name> 1259 <description>Data from FIFO to be read by DMA.</description> 1260 <bitRange>[31:0]</bitRange> 1261 <access>read-write</access> 1262 </field> 1263 </fields> 1264 </register> 1265 </registers> 1266 </peripheral> 1267<!--CAMERAIF Parallel Camera Interface.--> 1268 <peripheral> 1269 <name>CLCD</name> 1270 <description>Color LCD Controller</description> 1271 <baseAddress>0x40031000</baseAddress> 1272 <addressBlock> 1273 <offset>0x00</offset> 1274 <size>0x1000</size> 1275 <usage>registers</usage> 1276 </addressBlock> 1277 <registers> 1278 <register> 1279 <name>CLK</name> 1280 <description>LCD Clock Control Register</description> 1281 <addressOffset>0x000</addressOffset> 1282 <fields> 1283 <field> 1284 <name>CLKDIV</name> 1285 <description>Clock divsor</description> 1286 <bitOffset>0</bitOffset> 1287 <bitWidth>8</bitWidth> 1288 </field> 1289 <field> 1290 <name>ACB</name> 1291 <description>ACB</description> 1292 <bitOffset>8</bitOffset> 1293 <bitWidth>8</bitWidth> 1294 </field> 1295 <field> 1296 <name>DPOL</name> 1297 <description>D Polarity</description> 1298 <bitOffset>16</bitOffset> 1299 <bitWidth>1</bitWidth> 1300 <enumeratedValues> 1301 <enumeratedValue> 1302 <name>ACTIVEHI</name> 1303 <description>Active Hi</description> 1304 <value>0</value> 1305 </enumeratedValue> 1306 <enumeratedValue> 1307 <name>ACTIVELO</name> 1308 <description>Active Low</description> 1309 <value>1</value> 1310 </enumeratedValue> 1311 </enumeratedValues> 1312 </field> 1313 <field> 1314 <name>VPOL</name> 1315 <description>V Polarity</description> 1316 <bitOffset>17</bitOffset> 1317 <bitWidth>1</bitWidth> 1318 <enumeratedValues> 1319 <enumeratedValue> 1320 <name>ACTIVEHI</name> 1321 <description>Active Hi</description> 1322 <value>1</value> 1323 </enumeratedValue> 1324 <enumeratedValue> 1325 <name>ACTIVELO</name> 1326 <description>Active Low</description> 1327 <value>0</value> 1328 </enumeratedValue> 1329 </enumeratedValues> 1330 </field> 1331 <field> 1332 <name>HPOL</name> 1333 <description>H Polarity</description> 1334 <bitOffset>18</bitOffset> 1335 <bitWidth>1</bitWidth> 1336 <enumeratedValues> 1337 <enumeratedValue> 1338 <name>ACTIVEHI</name> 1339 <description>Active Hi</description> 1340 <value>1</value> 1341 </enumeratedValue> 1342 <enumeratedValue> 1343 <name>ACTIVELO</name> 1344 <description>Active Low</description> 1345 <value>0</value> 1346 </enumeratedValue> 1347 </enumeratedValues> 1348 </field> 1349 <field> 1350 <name>EDGE</name> 1351 <description>Edge Selection</description> 1352 <bitOffset>19</bitOffset> 1353 <bitWidth>1</bitWidth> 1354 <enumeratedValues> 1355 <enumeratedValue> 1356 <name>RISEEDGE</name> 1357 <description>Rising edge</description> 1358 <value>0</value> 1359 </enumeratedValue> 1360 <enumeratedValue> 1361 <name>FALLEDGE</name> 1362 <description>Falling Edge</description> 1363 <value>1</value> 1364 </enumeratedValue> 1365 </enumeratedValues> 1366 </field> 1367 <field> 1368 <name>PASCLK</name> 1369 <description>Clock Active on Data</description> 1370 <bitOffset>20</bitOffset> 1371 <bitWidth>1</bitWidth> 1372 <enumeratedValues> 1373 <enumeratedValue> 1374 <name>ALWAYSACTIVE</name> 1375 <description>Always Active</description> 1376 <value>0</value> 1377 </enumeratedValue> 1378 <enumeratedValue> 1379 <name>ACTIVEONDATA</name> 1380 <description>ACTIVE ON DATA</description> 1381 <value>1</value> 1382 </enumeratedValue> 1383 </enumeratedValues> 1384 </field> 1385 </fields> 1386 </register> 1387 <register> 1388 <name>VTIM_0</name> 1389 <description>LCD Vertical Timing 0 Register</description> 1390 <addressOffset>0x004</addressOffset> 1391 <fields> 1392 <field> 1393 <name>VLINES</name> 1394 <description>V Lines</description> 1395 <bitOffset>0</bitOffset> 1396 <bitWidth>8</bitWidth> 1397 </field> 1398 <field> 1399 <name>VBACKPORCH</name> 1400 <description>V BACK PORCH</description> 1401 <bitOffset>16</bitOffset> 1402 <bitWidth>8</bitWidth> 1403 </field> 1404 </fields> 1405 </register> 1406 <register> 1407 <name>VTIM_1</name> 1408 <description>LCD Vertical Timing 1 Register</description> 1409 <addressOffset>0x008</addressOffset> 1410 <fields> 1411 <field> 1412 <name>VSYNCWIDTH</name> 1413 <description>V Sync Width</description> 1414 <bitOffset>0</bitOffset> 1415 <bitWidth>8</bitWidth> 1416 </field> 1417 <field> 1418 <name>VFRONTPORCH</name> 1419 <description>V Front PORCH</description> 1420 <bitOffset>16</bitOffset> 1421 <bitWidth>8</bitWidth> 1422 </field> 1423 </fields> 1424 </register> 1425 <register> 1426 <name>HTIM</name> 1427 <description>LCD Horizontal Timing Register.</description> 1428 <addressOffset>0x00C</addressOffset> 1429 <fields> 1430 <field> 1431 <name>HSYNCWIDTH</name> 1432 <description>Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks</description> 1433 <bitOffset>0</bitOffset> 1434 <bitWidth>8</bitWidth> 1435 </field> 1436 <field> 1437 <name>HFRONTPORCH</name> 1438 <description>Horizontal Front Porch size in lines from 1 to 256</description> 1439 <bitOffset>8</bitOffset> 1440 <bitWidth>8</bitWidth> 1441 </field> 1442 <field> 1443 <name>HSIZE</name> 1444 <description>Horizontal Front Porch Size in Pixels = (HSIZE + 1) *16</description> 1445 <bitOffset>16</bitOffset> 1446 <bitWidth>8</bitWidth> 1447 </field> 1448 <field> 1449 <name>HBACKPORCH</name> 1450 <description>Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP= (HBACKPORCH+1) </description> 1451 <bitOffset>24</bitOffset> 1452 <bitWidth>8</bitWidth> 1453 </field> 1454 </fields> 1455 </register> 1456 <register> 1457 <name>CTRL</name> 1458 <description>LCD Control Register</description> 1459 <addressOffset>0x010</addressOffset> 1460 <fields> 1461 <field> 1462 <name>LCDEN</name> 1463 <description>LCD Enable</description> 1464 <bitOffset>0</bitOffset> 1465 <bitWidth>1</bitWidth> 1466 <enumeratedValues> 1467 <enumeratedValue> 1468 <name>DISABLE</name> 1469 <description>Disable</description> 1470 <value>0</value> 1471 </enumeratedValue> 1472 <enumeratedValue> 1473 <name>ENABLE</name> 1474 <description>Enable</description> 1475 <value>1</value> 1476 </enumeratedValue> 1477 </enumeratedValues> 1478 </field> 1479 <field> 1480 <name>VISEL</name> 1481 <description>VI Select</description> 1482 <bitOffset>1</bitOffset> 1483 <bitWidth>2</bitWidth> 1484 <enumeratedValues> 1485 <enumeratedValue> 1486 <name>ONVERTSYNC</name> 1487 <description>On Vertical Sync</description> 1488 <value>0</value> 1489 </enumeratedValue> 1490 <enumeratedValue> 1491 <name>ONVERTBACKPORCH</name> 1492 <description>On Vertical Back Porch</description> 1493 <value>1</value> 1494 </enumeratedValue> 1495 <enumeratedValue> 1496 <name>ONACTIVEVIDEO</name> 1497 <description>On Active Video</description> 1498 <value>2</value> 1499 </enumeratedValue> 1500 <enumeratedValue> 1501 <name>ONVERTFRONTPORCH</name> 1502 <description>On Vertical Front Porch</description> 1503 <value>3</value> 1504 </enumeratedValue> 1505 </enumeratedValues> 1506 </field> 1507 <field> 1508 <name>DISPTYPE</name> 1509 <description>Display Type</description> 1510 <bitOffset>4</bitOffset> 1511 <bitWidth>4</bitWidth> 1512 <enumeratedValues> 1513 <enumeratedValue> 1514 <name>STNCOLOR8BIT</name> 1515 <description>STN Color 8 bit</description> 1516 <value>4</value> 1517 </enumeratedValue> 1518 <enumeratedValue> 1519 <name>CLCD</name> 1520 <description>CLCD</description> 1521 <value>8</value> 1522 </enumeratedValue> 1523 </enumeratedValues> 1524 </field> 1525 <field> 1526 <name>BPP</name> 1527 <description>BPP</description> 1528 <bitOffset>8</bitOffset> 1529 <bitWidth>3</bitWidth> 1530 <enumeratedValues> 1531 <enumeratedValue> 1532 <name>BPP1</name> 1533 <description>BPP 1</description> 1534 <value>0</value> 1535 </enumeratedValue> 1536 <enumeratedValue> 1537 <name>BPP2</name> 1538 <description>BPP 2</description> 1539 <value>1</value> 1540 </enumeratedValue> 1541 <enumeratedValue> 1542 <name>BPP4</name> 1543 <description>BPP 4</description> 1544 <value>2</value> 1545 </enumeratedValue> 1546 <enumeratedValue> 1547 <name>BPP8</name> 1548 <description>BPP 8</description> 1549 <value>3</value> 1550 </enumeratedValue> 1551 <enumeratedValue> 1552 <name>BPP16</name> 1553 <description>BPP 16</description> 1554 <value>4</value> 1555 </enumeratedValue> 1556 <enumeratedValue> 1557 <name>BPP24</name> 1558 <description>BPP 24</description> 1559 <value>5</value> 1560 </enumeratedValue> 1561 </enumeratedValues> 1562 </field> 1563 <field> 1564 <name>MODE565</name> 1565 <description>MODE565</description> 1566 <bitOffset>11</bitOffset> 1567 <bitWidth>1</bitWidth> 1568 <enumeratedValues> 1569 <enumeratedValue> 1570 <name>BGR556</name> 1571 <description>MODE 556</description> 1572 <value>0</value> 1573 </enumeratedValue> 1574 <enumeratedValue> 1575 <name>RGB565</name> 1576 <description>MODE 565</description> 1577 <value>1</value> 1578 </enumeratedValue> 1579 </enumeratedValues> 1580 </field> 1581 <field> 1582 <name>EMODE</name> 1583 <description>EMODE</description> 1584 <bitOffset>12</bitOffset> 1585 <bitWidth>2</bitWidth> 1586 <enumeratedValues> 1587 <enumeratedValue> 1588 <name>LLBP</name> 1589 <description>LLBP</description> 1590 <value>0</value> 1591 </enumeratedValue> 1592 <enumeratedValue> 1593 <name>BBBP</name> 1594 <description>BBBP</description> 1595 <value>1</value> 1596 </enumeratedValue> 1597 <enumeratedValue> 1598 <name>LBBP</name> 1599 <description>LBBP</description> 1600 <value>2</value> 1601 </enumeratedValue> 1602 <enumeratedValue> 1603 <name>RFU</name> 1604 <description>RFU</description> 1605 <value>3</value> 1606 </enumeratedValue> 1607 </enumeratedValues> 1608 </field> 1609 <field> 1610 <name>C24</name> 1611 <description>C24</description> 1612 <bitOffset>15</bitOffset> 1613 <bitWidth>1</bitWidth> 1614 </field> 1615 <field> 1616 <name>BURST</name> 1617 <description>BURST</description> 1618 <bitOffset>19</bitOffset> 1619 <bitWidth>2</bitWidth> 1620 <enumeratedValues> 1621 <enumeratedValue> 1622 <name>WORDS4</name> 1623 <description>WORDS4</description> 1624 <value>0</value> 1625 </enumeratedValue> 1626 <enumeratedValue> 1627 <name>WORDS8</name> 1628 <description>WORDS8</description> 1629 <value>1</value> 1630 </enumeratedValue> 1631 </enumeratedValues> 1632 </field> 1633 <field> 1634 <name>LPOL</name> 1635 <description>LPOL</description> 1636 <bitOffset>21</bitOffset> 1637 <bitWidth>1</bitWidth> 1638 <enumeratedValues> 1639 <enumeratedValue> 1640 <name>ACTIVEHI</name> 1641 <description>ACTIVE HIGH</description> 1642 <value>0</value> 1643 </enumeratedValue> 1644 <enumeratedValue> 1645 <name>ACTIVELO</name> 1646 <description>ACTIVE LOW</description> 1647 <value>1</value> 1648 </enumeratedValue> 1649 </enumeratedValues> 1650 </field> 1651 <field> 1652 <name>PEN</name> 1653 <description>PEN</description> 1654 <bitOffset>22</bitOffset> 1655 <bitWidth>1</bitWidth> 1656 </field> 1657 </fields> 1658 </register> 1659 <register> 1660 <name>FR</name> 1661 <description>FRBUF</description> 1662 <addressOffset>0x18</addressOffset> 1663 </register> 1664 <register> 1665 <name>INT_EN</name> 1666 <description>LCD Interrupt Enable Register.</description> 1667 <addressOffset>0x020</addressOffset> 1668 <fields> 1669 <field> 1670 <name>UFLO</name> 1671 <description>Under FLow Interupt Enable</description> 1672 <bitOffset>0</bitOffset> 1673 <bitWidth>1</bitWidth> 1674 </field> 1675 <field> 1676 <name>ADRRDY</name> 1677 <description>Address Ready Interupt Enable</description> 1678 <bitOffset>1</bitOffset> 1679 <bitWidth>1</bitWidth> 1680 </field> 1681 <field> 1682 <name>VCI</name> 1683 <description>VCI Interupt Enable</description> 1684 <bitOffset>2</bitOffset> 1685 <bitWidth>1</bitWidth> 1686 </field> 1687 <field> 1688 <name>BERR</name> 1689 <description>BERR Interupt Enable</description> 1690 <bitOffset>3</bitOffset> 1691 <bitWidth>1</bitWidth> 1692 </field> 1693 </fields> 1694 </register> 1695 <register> 1696 <name>STAT</name> 1697 <description>LCD Status Register.</description> 1698 <addressOffset>0x024</addressOffset> 1699 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1700 <fields> 1701 <field> 1702 <name>UFLO</name> 1703 <description>Under FLow Interupt Status</description> 1704 <bitOffset>0</bitOffset> 1705 <bitWidth>1</bitWidth> 1706 <enumeratedValues> 1707 <usage>read</usage> 1708 <enumeratedValue> 1709 <name>Inactive</name> 1710 <description>No interrupt pending</description> 1711 <value>0</value> 1712 </enumeratedValue> 1713 <enumeratedValue> 1714 <name>Pending</name> 1715 <description>Interrupt pending</description> 1716 <value>1</value> 1717 </enumeratedValue> 1718 </enumeratedValues> 1719 <enumeratedValues> 1720 <usage>write</usage> 1721 <enumeratedValue> 1722 <name>Clear</name> 1723 <description>Clears the interrupt flag</description> 1724 <value>1</value> 1725 </enumeratedValue> 1726 </enumeratedValues> 1727 </field> 1728 <field> 1729 <name>ADRRDY</name> 1730 <description>Address Ready Interupt Status</description> 1731 <bitOffset>1</bitOffset> 1732 <bitWidth>1</bitWidth> 1733 <enumeratedValues> 1734 <usage>read</usage> 1735 <enumeratedValue> 1736 <name>Inactive</name> 1737 <description>No interrupt pending</description> 1738 <value>0</value> 1739 </enumeratedValue> 1740 <enumeratedValue> 1741 <name>Pending</name> 1742 <description>Interrupt pending</description> 1743 <value>1</value> 1744 </enumeratedValue> 1745 </enumeratedValues> 1746 <enumeratedValues> 1747 <usage>write</usage> 1748 <enumeratedValue> 1749 <name>Clear</name> 1750 <description>Clears the interrupt flag</description> 1751 <value>1</value> 1752 </enumeratedValue> 1753 </enumeratedValues> 1754 </field> 1755 <field> 1756 <name>VCI</name> 1757 <description>VCI Interupt Status</description> 1758 <bitOffset>2</bitOffset> 1759 <bitWidth>1</bitWidth> 1760 <enumeratedValues> 1761 <usage>read</usage> 1762 <enumeratedValue> 1763 <name>Inactive</name> 1764 <description>No interrupt pending</description> 1765 <value>0</value> 1766 </enumeratedValue> 1767 <enumeratedValue> 1768 <name>Pending</name> 1769 <description>Interrupt pending</description> 1770 <value>1</value> 1771 </enumeratedValue> 1772 </enumeratedValues> 1773 <enumeratedValues> 1774 <usage>write</usage> 1775 <enumeratedValue> 1776 <name>Clear</name> 1777 <description>Clears the interrupt flag</description> 1778 <value>1</value> 1779 </enumeratedValue> 1780 </enumeratedValues> 1781 </field> 1782 <field> 1783 <name>BERR</name> 1784 <description>BERR Interupt Status</description> 1785 <bitOffset>3</bitOffset> 1786 <bitWidth>1</bitWidth> 1787 <enumeratedValues> 1788 <usage>read</usage> 1789 <enumeratedValue> 1790 <name>Inactive</name> 1791 <description>No interrupt pending</description> 1792 <value>0</value> 1793 </enumeratedValue> 1794 <enumeratedValue> 1795 <name>Pending</name> 1796 <description>Interrupt pending</description> 1797 <value>1</value> 1798 </enumeratedValue> 1799 </enumeratedValues> 1800 <enumeratedValues> 1801 <usage>write</usage> 1802 <enumeratedValue> 1803 <name>Clear</name> 1804 <description>Clears the interrupt flag</description> 1805 <value>1</value> 1806 </enumeratedValue> 1807 </enumeratedValues> 1808 </field> 1809 <field> 1810 <name>LCDIDLE</name> 1811 <description>LCD IDLE Staus</description> 1812 <bitOffset>8</bitOffset> 1813 <bitWidth>1</bitWidth> 1814 <enumeratedValues> 1815 <enumeratedValue> 1816 <name>BUSY</name> 1817 <description>BUSY</description> 1818 <value>0</value> 1819 </enumeratedValue> 1820 <enumeratedValue> 1821 <name>READY</name> 1822 <description>READY</description> 1823 <value>1</value> 1824 </enumeratedValue> 1825 </enumeratedValues> 1826 </field> 1827 </fields> 1828 </register> 1829 <register> 1830 <dim>256</dim> 1831 <dimIncrement>4</dimIncrement> 1832 <name>PALETTE[%s]</name> 1833 <description>Palette</description> 1834 <addressOffset>0x400</addressOffset> 1835 <fields> 1836 <field> 1837 <name>RED</name> 1838 <description>Red Data for Pallet Entry.</description> 1839 <bitOffset>0</bitOffset> 1840 <bitWidth>8</bitWidth> 1841 </field> 1842 <field> 1843 <name>GREEN</name> 1844 <description>Green Data for Pallet Entry.</description> 1845 <bitOffset>8</bitOffset> 1846 <bitWidth>8</bitWidth> 1847 </field> 1848 <field> 1849 <name>BLUE</name> 1850 <description>Blue Data for Pallet Entry.</description> 1851 <bitOffset>16</bitOffset> 1852 <bitWidth>8</bitWidth> 1853 </field> 1854 </fields> 1855 </register> 1856 </registers> 1857 </peripheral> 1858<!--CLCD Color LCD Controller--> 1859 <peripheral> 1860 <name>CTB</name> 1861 <description>The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.</description> 1862 <baseAddress>0x40001000</baseAddress> 1863 <addressBlock> 1864 <offset>0x00</offset> 1865 <size>0x1000</size> 1866 <usage>registers</usage> 1867 </addressBlock> 1868 <interrupt> 1869 <name>Crypto_Engine</name> 1870 <description>Crypto Engine interrupt.</description> 1871 <value>27</value> 1872 </interrupt> 1873 <registers> 1874 <register> 1875 <name>CRYPTO_CTRL</name> 1876 <description>Crypto Control Register.</description> 1877 <addressOffset>0x00</addressOffset> 1878 <resetValue>0xC0000000</resetValue> 1879 <fields> 1880 <field> 1881 <name>RST</name> 1882 <description>Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.</description> 1883 <bitOffset>0</bitOffset> 1884 <bitWidth>1</bitWidth> 1885 <enumeratedValues> 1886 <name>reset_write</name> 1887 <usage>write</usage> 1888 <enumeratedValue> 1889 <name>reset</name> 1890 <description>Starts reset operation.</description> 1891 <value>1</value> 1892 </enumeratedValue> 1893 </enumeratedValues> 1894 <enumeratedValues> 1895 <name>reset_read</name> 1896 <usage>read</usage> 1897 <enumeratedValue> 1898 <name>reset_done</name> 1899 <description>Reset complete.</description> 1900 <value>0</value> 1901 </enumeratedValue> 1902 <enumeratedValue> 1903 <name>busy</name> 1904 <description>Reset in progress.</description> 1905 <value>1</value> 1906 </enumeratedValue> 1907 </enumeratedValues> 1908 </field> 1909 <field> 1910 <name>INTR</name> 1911 <description>Interrupt Enable. Generates an interrupt when done or error set.</description> 1912 <bitOffset>1</bitOffset> 1913 <bitWidth>1</bitWidth> 1914 <enumeratedValues> 1915 <enumeratedValue> 1916 <name>dis</name> 1917 <description>Disable</description> 1918 <value>0</value> 1919 </enumeratedValue> 1920 <enumeratedValue> 1921 <name>en</name> 1922 <description>Enable</description> 1923 <value>1</value> 1924 </enumeratedValue> 1925 </enumeratedValues> 1926 </field> 1927 <field> 1928 <name>SRC</name> 1929 <description>Source Select. This bit selects the hash function and CRC generator input source.</description> 1930 <bitOffset>2</bitOffset> 1931 <bitWidth>1</bitWidth> 1932 <enumeratedValues> 1933 <enumeratedValue> 1934 <name>inputFIFO</name> 1935 <description>Input FIFO</description> 1936 <value>0</value> 1937 </enumeratedValue> 1938 <enumeratedValue> 1939 <name>outputFIFO</name> 1940 <description>Output FIFO</description> 1941 <value>1</value> 1942 </enumeratedValue> 1943 </enumeratedValues> 1944 </field> 1945 <field derivedFrom="INTR"> 1946 <name>BSO</name> 1947 <description>Byte Swap Output. Note. No byte swap will occur if there is not a full word.</description> 1948 <bitOffset>4</bitOffset> 1949 <bitWidth>1</bitWidth> 1950 </field> 1951 <field derivedFrom="INTR"> 1952 <name>BSI</name> 1953 <description>Byte Swap Input. Note. No byte swap will occur if there is not a full word.</description> 1954 <bitOffset>5</bitOffset> 1955 <bitWidth>1</bitWidth> 1956 </field> 1957 <field derivedFrom="INTR"> 1958 <name>WAIT_EN</name> 1959 <description>Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.</description> 1960 <bitOffset>6</bitOffset> 1961 <bitWidth>1</bitWidth> 1962 </field> 1963 <field> 1964 <name>WAIT_POL</name> 1965 <description>Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.</description> 1966 <bitOffset>7</bitOffset> 1967 <bitWidth>1</bitWidth> 1968 <enumeratedValues> 1969 <enumeratedValue> 1970 <name>activeLo</name> 1971 <description>Active Low.</description> 1972 <value>0</value> 1973 </enumeratedValue> 1974 <enumeratedValue> 1975 <name>activeHi</name> 1976 <description>Active High.</description> 1977 <value>1</value> 1978 </enumeratedValue> 1979 </enumeratedValues> 1980 </field> 1981 <field> 1982 <name>WRSRC</name> 1983 <description>Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.</description> 1984 <bitOffset>8</bitOffset> 1985 <bitWidth>2</bitWidth> 1986 <enumeratedValues> 1987 <enumeratedValue> 1988 <name>none</name> 1989 <description>None.</description> 1990 <value>0</value> 1991 </enumeratedValue> 1992 <enumeratedValue> 1993 <name>cipherOutput</name> 1994 <description>Cipher Output.</description> 1995 <value>1</value> 1996 </enumeratedValue> 1997 <enumeratedValue> 1998 <name>readFIFO</name> 1999 <description>Read FIFO.</description> 2000 <value>2</value> 2001 </enumeratedValue> 2002 </enumeratedValues> 2003 </field> 2004 <field> 2005 <name>RDSRC</name> 2006 <description>Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.</description> 2007 <bitOffset>10</bitOffset> 2008 <bitWidth>2</bitWidth> 2009 <enumeratedValues> 2010 <enumeratedValue> 2011 <name>dmaDisabled</name> 2012 <description>DMA Disable.</description> 2013 <value>0</value> 2014 </enumeratedValue> 2015 <enumeratedValue> 2016 <name>dmaOrApb</name> 2017 <description>DMA Or APB.</description> 2018 <value>1</value> 2019 </enumeratedValue> 2020 <enumeratedValue> 2021 <name>rng</name> 2022 <description>RNG.</description> 2023 <value>2</value> 2024 </enumeratedValue> 2025 </enumeratedValues> 2026 </field> 2027 <field> 2028 <name>FLAG_MODE</name> 2029 <description>Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.</description> 2030 <bitOffset>14</bitOffset> 2031 <bitWidth>1</bitWidth> 2032 <enumeratedValues> 2033 <enumeratedValue> 2034 <name>unres_wr</name> 2035 <description>Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.</description> 2036 <value>0</value> 2037 </enumeratedValue> 2038 <enumeratedValue> 2039 <name>res_wr</name> 2040 <description>Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.</description> 2041 <value>1</value> 2042 </enumeratedValue> 2043 </enumeratedValues> 2044 </field> 2045 <field> 2046 <name>DMADNEMSK</name> 2047 <description>DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.</description> 2048 <bitOffset>15</bitOffset> 2049 <bitWidth>1</bitWidth> 2050 <enumeratedValues> 2051 <enumeratedValue> 2052 <name>not_used</name> 2053 <description>DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.</description> 2054 <value>0</value> 2055 </enumeratedValue> 2056 <enumeratedValue> 2057 <name>used</name> 2058 <description>DMA_DONE used in setting CRYPTO_CTRL.DONE bit.</description> 2059 <value>1</value> 2060 </enumeratedValue> 2061 </enumeratedValues> 2062 </field> 2063 <field> 2064 <name>DMA_DONE</name> 2065 <description>DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.</description> 2066 <bitOffset>24</bitOffset> 2067 <bitWidth>1</bitWidth> 2068 <enumeratedValues> 2069 <enumeratedValue> 2070 <name>notDone</name> 2071 <description>Not Done.</description> 2072 <value>0</value> 2073 </enumeratedValue> 2074 <enumeratedValue> 2075 <name>done</name> 2076 <description>Done.</description> 2077 <value>1</value> 2078 </enumeratedValue> 2079 </enumeratedValues> 2080 </field> 2081 <field derivedFrom="DMA_DONE"> 2082 <name>GLS_DONE</name> 2083 <description>Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.</description> 2084 <bitOffset>25</bitOffset> 2085 <bitWidth>1</bitWidth> 2086 </field> 2087 <field derivedFrom="DMA_DONE"> 2088 <name>HSH_DONE</name> 2089 <description>Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.</description> 2090 <bitOffset>26</bitOffset> 2091 <bitWidth>1</bitWidth> 2092 </field> 2093 <field derivedFrom="DMA_DONE"> 2094 <name>CPH_DONE</name> 2095 <description>Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.</description> 2096 <bitOffset>27</bitOffset> 2097 <bitWidth>1</bitWidth> 2098 </field> 2099 <field> 2100 <name>ERR</name> 2101 <description>AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.</description> 2102 <bitOffset>29</bitOffset> 2103 <bitWidth>1</bitWidth> 2104 <access>read-only</access> 2105 <enumeratedValues> 2106 <enumeratedValue> 2107 <name>noError</name> 2108 <description>No Error.</description> 2109 <value>0</value> 2110 </enumeratedValue> 2111 <enumeratedValue> 2112 <name>error</name> 2113 <description>Error.</description> 2114 <value>1</value> 2115 </enumeratedValue> 2116 </enumeratedValues> 2117 </field> 2118 <field> 2119 <name>RDY</name> 2120 <description>Ready. Crypto block ready for more data.</description> 2121 <bitOffset>30</bitOffset> 2122 <bitWidth>1</bitWidth> 2123 <access>read-only</access> 2124 <enumeratedValues> 2125 <enumeratedValue> 2126 <name>busy</name> 2127 <description>Busy.</description> 2128 <value>0</value> 2129 </enumeratedValue> 2130 <enumeratedValue> 2131 <name>ready</name> 2132 <description>Ready.</description> 2133 <value>1</value> 2134 </enumeratedValue> 2135 </enumeratedValues> 2136 </field> 2137 <field derivedFrom="DMA_DONE"> 2138 <name>DONE</name> 2139 <description>Done. One or more cryptographic calculations complete (logical OR of done flags).</description> 2140 <bitOffset>31</bitOffset> 2141 <bitWidth>1</bitWidth> 2142 <access>read-only</access> 2143 </field> 2144 </fields> 2145 </register> 2146 <register> 2147 <name>CIPHER_CTRL</name> 2148 <description>Cipher Control Register.</description> 2149 <addressOffset>0x04</addressOffset> 2150 <fields> 2151 <field> 2152 <name>ENC</name> 2153 <description>Encrypt. Select encryption or decryption of input data.</description> 2154 <bitOffset>0</bitOffset> 2155 <bitWidth>1</bitWidth> 2156 <enumeratedValues> 2157 <enumeratedValue> 2158 <name>encrypt</name> 2159 <description>Encrypt.</description> 2160 <value>0</value> 2161 </enumeratedValue> 2162 <enumeratedValue> 2163 <name>decrypt</name> 2164 <description>Decrypt.</description> 2165 <value>1</value> 2166 </enumeratedValue> 2167 </enumeratedValues> 2168 </field> 2169 <field> 2170 <name>KEY</name> 2171 <description>Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.</description> 2172 <bitOffset>1</bitOffset> 2173 <bitWidth>1</bitWidth> 2174 <enumeratedValues> 2175 <enumeratedValue> 2176 <name>complete</name> 2177 <description>No operation/complete.</description> 2178 <value>0</value> 2179 </enumeratedValue> 2180 <enumeratedValue> 2181 <name>start</name> 2182 <description>Start operation.</description> 2183 <value>1</value> 2184 </enumeratedValue> 2185 </enumeratedValues> 2186 </field> 2187 <field> 2188 <name>SRC</name> 2189 <description>Source of Random key.</description> 2190 <bitOffset>2</bitOffset> 2191 <bitWidth>2</bitWidth> 2192 <enumeratedValues> 2193 <enumeratedValue> 2194 <name>cipherKey</name> 2195 <description>User cipher key (0x4000_1060).</description> 2196 <value>0</value> 2197 </enumeratedValue> 2198 <enumeratedValue> 2199 <name>regFile</name> 2200 <description>Key from battery-backed register file (0x4000_5000 to 0x4000_501F).</description> 2201 <value>2</value> 2202 </enumeratedValue> 2203 <enumeratedValue> 2204 <name>qspiKey_regFile</name> 2205 <description>Key from battery-backed register file (0x4000_5020 to 0x4000_502F).</description> 2206 <value>3</value> 2207 </enumeratedValue> 2208 </enumeratedValues> 2209 </field> 2210 <field> 2211 <name>CIPHER</name> 2212 <description>Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.</description> 2213 <bitOffset>4</bitOffset> 2214 <bitWidth>3</bitWidth> 2215 <enumeratedValues> 2216 <enumeratedValue> 2217 <name>dis</name> 2218 <description>Disabled.</description> 2219 <value>0</value> 2220 </enumeratedValue> 2221 <enumeratedValue> 2222 <name>aes128</name> 2223 <description>AES 128.</description> 2224 <value>1</value> 2225 </enumeratedValue> 2226 <enumeratedValue> 2227 <name>aes192</name> 2228 <description>AES 192.</description> 2229 <value>2</value> 2230 </enumeratedValue> 2231 <enumeratedValue> 2232 <name>aes256</name> 2233 <description>AES 256.</description> 2234 <value>3</value> 2235 </enumeratedValue> 2236 <enumeratedValue> 2237 <name>des</name> 2238 <description>DES.</description> 2239 <value>4</value> 2240 </enumeratedValue> 2241 <enumeratedValue> 2242 <name>tdes</name> 2243 <description>Triple DES.</description> 2244 <value>5</value> 2245 </enumeratedValue> 2246 </enumeratedValues> 2247 </field> 2248 <field> 2249 <name>MODE</name> 2250 <description>Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.</description> 2251 <bitOffset>8</bitOffset> 2252 <bitWidth>3</bitWidth> 2253 <enumeratedValues> 2254 <enumeratedValue> 2255 <name>ECB</name> 2256 <description>ECB Mode.</description> 2257 <value>0</value> 2258 </enumeratedValue> 2259 <enumeratedValue> 2260 <name>CBC</name> 2261 <description>CBC Mode.</description> 2262 <value>1</value> 2263 </enumeratedValue> 2264 <enumeratedValue> 2265 <name>CFB</name> 2266 <description>CFB (AES only).</description> 2267 <value>2</value> 2268 </enumeratedValue> 2269 <enumeratedValue> 2270 <name>OFB</name> 2271 <description>OFB (AES only).</description> 2272 <value>3</value> 2273 </enumeratedValue> 2274 <enumeratedValue> 2275 <name>CTR</name> 2276 <description>CTR (AES only).</description> 2277 <value>4</value> 2278 </enumeratedValue> 2279 </enumeratedValues> 2280 </field> 2281 <field> 2282 <name>HVC</name> 2283 <description>H Vector Computation.</description> 2284 <bitOffset>11</bitOffset> 2285 <bitWidth>1</bitWidth> 2286 <access>read-only</access> 2287 </field> 2288 <field> 2289 <name>DTYPE</name> 2290 <description>GCM/CCM data type.</description> 2291 <bitOffset>12</bitOffset> 2292 <bitWidth>1</bitWidth> 2293 <access>read-only</access> 2294 </field> 2295 <field> 2296 <name>CCMM</name> 2297 <description>CCM M Parameter.</description> 2298 <bitOffset>13</bitOffset> 2299 <bitWidth>3</bitWidth> 2300 <access>read-only</access> 2301 </field> 2302 <field> 2303 <name>CCML</name> 2304 <description>CCM L Parameter.</description> 2305 <bitOffset>16</bitOffset> 2306 <bitWidth>3</bitWidth> 2307 <access>read-only</access> 2308 </field> 2309 </fields> 2310 </register> 2311 <register> 2312 <name>HASH_CTRL</name> 2313 <description>HASH Control Register.</description> 2314 <addressOffset>0x08</addressOffset> 2315 <fields> 2316 <field> 2317 <name>INIT</name> 2318 <description>Initialize. Initializes hash registers with standard constants.</description> 2319 <bitOffset>0</bitOffset> 2320 <bitWidth>1</bitWidth> 2321 <enumeratedValues> 2322 <enumeratedValue> 2323 <name>nop</name> 2324 <description>No operation/complete.</description> 2325 <value>0</value> 2326 </enumeratedValue> 2327 <enumeratedValue> 2328 <name>start</name> 2329 <description>Start operation.</description> 2330 <value>1</value> 2331 </enumeratedValue> 2332 </enumeratedValues> 2333 </field> 2334 <field> 2335 <name>XOR</name> 2336 <description>XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.</description> 2337 <bitOffset>1</bitOffset> 2338 <bitWidth>1</bitWidth> 2339 <enumeratedValues> 2340 <enumeratedValue> 2341 <name>dis</name> 2342 <description>Disable.</description> 2343 <value>0</value> 2344 </enumeratedValue> 2345 <enumeratedValue> 2346 <name>en</name> 2347 <description>Enable.</description> 2348 <value>1</value> 2349 </enumeratedValue> 2350 </enumeratedValues> 2351 </field> 2352 <field> 2353 <name>HASH</name> 2354 <description>Hash function selection.</description> 2355 <bitOffset>2</bitOffset> 2356 <bitWidth>3</bitWidth> 2357 <enumeratedValues> 2358 <enumeratedValue> 2359 <name>dis</name> 2360 <description>Disabled.</description> 2361 <value>0</value> 2362 </enumeratedValue> 2363 <enumeratedValue> 2364 <name>sha1</name> 2365 <description>SHA-1.</description> 2366 <value>1</value> 2367 </enumeratedValue> 2368 <enumeratedValue> 2369 <name>sha224</name> 2370 <description>SHA 224.</description> 2371 <value>2</value> 2372 </enumeratedValue> 2373 <enumeratedValue> 2374 <name>sha256</name> 2375 <description>SHA 256.</description> 2376 <value>3</value> 2377 </enumeratedValue> 2378 <enumeratedValue> 2379 <name>sha384</name> 2380 <description>SHA 384.</description> 2381 <value>4</value> 2382 </enumeratedValue> 2383 <enumeratedValue> 2384 <name>sha512</name> 2385 <description>SHA 512.</description> 2386 <value>5</value> 2387 </enumeratedValue> 2388 </enumeratedValues> 2389 </field> 2390 <field> 2391 <name>LAST</name> 2392 <description>Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.</description> 2393 <bitOffset>5</bitOffset> 2394 <bitWidth>1</bitWidth> 2395 <enumeratedValues> 2396 <enumeratedValue> 2397 <name>noEffect</name> 2398 <description>No Effect.</description> 2399 <value>0</value> 2400 </enumeratedValue> 2401 <enumeratedValue> 2402 <name>lastMsgData</name> 2403 <description>Last Message Data.</description> 2404 <value>1</value> 2405 </enumeratedValue> 2406 </enumeratedValues> 2407 </field> 2408 </fields> 2409 </register> 2410 <register> 2411 <name>CRC_CTRL</name> 2412 <description>CRC Control Register.</description> 2413 <addressOffset>0x0C</addressOffset> 2414 <fields> 2415 <field> 2416 <name>CRC</name> 2417 <description>Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.</description> 2418 <bitOffset>0</bitOffset> 2419 <bitWidth>1</bitWidth> 2420 <enumeratedValues> 2421 <enumeratedValue> 2422 <name>dis</name> 2423 <description>Disable.</description> 2424 <value>0</value> 2425 </enumeratedValue> 2426 <enumeratedValue> 2427 <name>en</name> 2428 <description>Enable.</description> 2429 <value>1</value> 2430 </enumeratedValue> 2431 </enumeratedValues> 2432 </field> 2433 <field> 2434 <name>MSB</name> 2435 <description>MSB select. This bit selects the order of calculating CRC on data.</description> 2436 <bitOffset>1</bitOffset> 2437 <bitWidth>1</bitWidth> 2438 <enumeratedValues> 2439 <enumeratedValue> 2440 <name>lsbFirst</name> 2441 <description>LSB First.</description> 2442 <value>0</value> 2443 </enumeratedValue> 2444 <enumeratedValue> 2445 <name>msbFirst</name> 2446 <description>MSB First.</description> 2447 <value>1</value> 2448 </enumeratedValue> 2449 </enumeratedValues> 2450 </field> 2451 <field derivedFrom="CRC"> 2452 <name>PRNG</name> 2453 <description>Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.</description> 2454 <bitOffset>2</bitOffset> 2455 <bitWidth>1</bitWidth> 2456 </field> 2457 <field derivedFrom="CRC"> 2458 <name>ENT</name> 2459 <description>Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.</description> 2460 <bitOffset>3</bitOffset> 2461 <bitWidth>1</bitWidth> 2462 </field> 2463 <field derivedFrom="CRC"> 2464 <name>HAM</name> 2465 <description>Hamming Code Enable. Enable hamming code calculation.</description> 2466 <bitOffset>4</bitOffset> 2467 <bitWidth>1</bitWidth> 2468 </field> 2469 <field> 2470 <name>HRST</name> 2471 <description>Hamming Reset. Reset Hamming code ECC generator for next block.</description> 2472 <bitOffset>5</bitOffset> 2473 <bitWidth>1</bitWidth> 2474 <access>write-only</access> 2475 <enumeratedValues> 2476 <usage>write</usage> 2477 <enumeratedValue> 2478 <name>reset</name> 2479 <description>Starts reset operation.</description> 2480 <value>1</value> 2481 </enumeratedValue> 2482 </enumeratedValues> 2483 </field> 2484 </fields> 2485 </register> 2486 <register> 2487 <name>DMA_SRC</name> 2488 <description>Crypto DMA Source Address.</description> 2489 <addressOffset>0x10</addressOffset> 2490 <fields> 2491 <field> 2492 <name>ADDR</name> 2493 <description>DMA Source Address.</description> 2494 <bitOffset>0</bitOffset> 2495 <bitWidth>32</bitWidth> 2496 </field> 2497 </fields> 2498 </register> 2499 <register> 2500 <name>DMA_DEST</name> 2501 <description>Crypto DMA Destination Address.</description> 2502 <addressOffset>0x14</addressOffset> 2503 <fields> 2504 <field> 2505 <name>ADDR</name> 2506 <description>DMA Destination Address.</description> 2507 <bitOffset>0</bitOffset> 2508 <bitWidth>32</bitWidth> 2509 </field> 2510 </fields> 2511 </register> 2512 <register> 2513 <name>DMA_CNT</name> 2514 <description>Crypto DMA Byte Count.</description> 2515 <addressOffset>0x18</addressOffset> 2516 <fields> 2517 <field> 2518 <name>COUNT</name> 2519 <description>DMA Byte Address.</description> 2520 <bitOffset>0</bitOffset> 2521 <bitWidth>32</bitWidth> 2522 </field> 2523 </fields> 2524 </register> 2525 <register> 2526 <dim>4</dim> 2527 <dimIncrement>4</dimIncrement> 2528 <name>CRYPTO_DIN[%s]</name> 2529 <description>Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.</description> 2530 <addressOffset>0x20</addressOffset> 2531 <access>write-only</access> 2532 <fields> 2533 <field> 2534 <name>DATA</name> 2535 <description>Crypto Data Input. Input can be written to this register instead of using DMA.</description> 2536 <bitOffset>0</bitOffset> 2537 <bitWidth>32</bitWidth> 2538 </field> 2539 </fields> 2540 </register> 2541 <register> 2542 <dim>4</dim> 2543 <dimIncrement>4</dimIncrement> 2544 <name>CRYPTO_DOUT[%s]</name> 2545 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.</description> 2546 <addressOffset>0x30</addressOffset> 2547 <access>read-only</access> 2548 <fields> 2549 <field> 2550 <name>DATA</name> 2551 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.</description> 2552 <bitOffset>0</bitOffset> 2553 <bitWidth>32</bitWidth> 2554 </field> 2555 </fields> 2556 </register> 2557 <register> 2558 <name>CRC_POLY</name> 2559 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 2560 <addressOffset>0x40</addressOffset> 2561 <resetValue>0xEDB88320</resetValue> 2562 <fields> 2563 <field> 2564 <name>DATA</name> 2565 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 2566 <bitOffset>0</bitOffset> 2567 <bitWidth>32</bitWidth> 2568 </field> 2569 </fields> 2570 </register> 2571 <register> 2572 <name>CRC_VAL</name> 2573 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.</description> 2574 <addressOffset>0x44</addressOffset> 2575 <resetValue>0xFFFFFFFF</resetValue> 2576 <fields> 2577 <field> 2578 <name>VAL</name> 2579 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.</description> 2580 <bitOffset>0</bitOffset> 2581 <bitWidth>32</bitWidth> 2582 </field> 2583 </fields> 2584 </register> 2585 <register> 2586 <name>HAM_ECC</name> 2587 <description>Hamming ECC Register.</description> 2588 <addressOffset>0x4C</addressOffset> 2589 <fields> 2590 <field> 2591 <name>ECC</name> 2592 <description>Hamming ECC Value. These bits are the even parity of their corresponding bit groups.</description> 2593 <bitOffset>0</bitOffset> 2594 <bitWidth>16</bitWidth> 2595 </field> 2596 <field> 2597 <name>PAR</name> 2598 <description>Parity. This is the parity of the entire array.</description> 2599 <bitOffset>16</bitOffset> 2600 <bitWidth>1</bitWidth> 2601 <enumeratedValues> 2602 <enumeratedValue> 2603 <name>even</name> 2604 <description>Even.</description> 2605 <value>0</value> 2606 </enumeratedValue> 2607 <enumeratedValue> 2608 <name>odd</name> 2609 <description>Odd.</description> 2610 <value>1</value> 2611 </enumeratedValue> 2612 </enumeratedValues> 2613 </field> 2614 </fields> 2615 </register> 2616 <register> 2617 <dim>4</dim> 2618 <dimIncrement>4</dimIncrement> 2619 <name>CIPHER_INIT[%s]</name> 2620 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 2621 <addressOffset>0x50</addressOffset> 2622 <fields> 2623 <field> 2624 <name>IVEC</name> 2625 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 2626 <bitOffset>0</bitOffset> 2627 <bitWidth>32</bitWidth> 2628 </field> 2629 </fields> 2630 </register> 2631 <register> 2632 <dim>8</dim> 2633 <dimIncrement>4</dimIncrement> 2634 <name>CIPHER_KEY[%s]</name> 2635 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.</description> 2636 <addressOffset>0x60</addressOffset> 2637 <access>write-only</access> 2638 <fields> 2639 <field> 2640 <name>KEY</name> 2641 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.</description> 2642 <bitOffset>0</bitOffset> 2643 <bitWidth>32</bitWidth> 2644 </field> 2645 </fields> 2646 </register> 2647 <register> 2648 <dim>16</dim> 2649 <dimIncrement>4</dimIncrement> 2650 <name>HASH_DIGEST[%s]</name> 2651 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 2652 <addressOffset>0x80</addressOffset> 2653 <fields> 2654 <field> 2655 <name>HASH</name> 2656 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 2657 <bitOffset>0</bitOffset> 2658 <bitWidth>32</bitWidth> 2659 </field> 2660 </fields> 2661 </register> 2662 <register> 2663 <dim>4</dim> 2664 <dimIncrement>4</dimIncrement> 2665 <name>HASH_MSG_SZ[%s]</name> 2666 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 2667 <addressOffset>0xC0</addressOffset> 2668 <fields> 2669 <field> 2670 <name>MSGSZ</name> 2671 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 2672 <bitOffset>0</bitOffset> 2673 <bitWidth>32</bitWidth> 2674 </field> 2675 </fields> 2676 </register> 2677 <register> 2678 <name>AAD_LENGTH_0</name> 2679 <description>.AAD Length Register 0.</description> 2680 <addressOffset>0xD0</addressOffset> 2681 <resetValue>0x0</resetValue> 2682 <fields> 2683 <field> 2684 <name>LENGTH</name> 2685 <description>AAD length in bytes for AES GCM and CCM operations.</description> 2686 <bitOffset>0</bitOffset> 2687 <bitWidth>32</bitWidth> 2688 </field> 2689 </fields> 2690 </register> 2691 <register> 2692 <name>AAD_LENGTH_1</name> 2693 <description>.AAD Length Register 1.</description> 2694 <addressOffset>0xD4</addressOffset> 2695 <resetValue>0x0</resetValue> 2696 <fields> 2697 <field> 2698 <name>LENGTH</name> 2699 <description>AAD length in bytes for AES GCM and CCM operations.</description> 2700 <bitOffset>0</bitOffset> 2701 <bitWidth>32</bitWidth> 2702 </field> 2703 </fields> 2704 </register> 2705 <register> 2706 <name>PLD_LENGTH_0</name> 2707 <description>.PLD Length Register 0.</description> 2708 <addressOffset>0xD8</addressOffset> 2709 <resetValue>0x0</resetValue> 2710 <fields> 2711 <field> 2712 <name>LENGTH</name> 2713 <description>PLD length in bytes for AES GCM and CCM operations.</description> 2714 <bitOffset>0</bitOffset> 2715 <bitWidth>32</bitWidth> 2716 </field> 2717 </fields> 2718 </register> 2719 <register> 2720 <name>PLD_LENGTH_1</name> 2721 <description>.LENGTH.</description> 2722 <addressOffset>0xDC</addressOffset> 2723 <resetValue>0x0</resetValue> 2724 <fields> 2725 <field> 2726 <name>LENGTH</name> 2727 <description>PLD length in bytes for AES GCM and CCM operations.</description> 2728 <bitOffset>0</bitOffset> 2729 <bitWidth>32</bitWidth> 2730 </field> 2731 </fields> 2732 </register> 2733 <register> 2734 <dim>4</dim> 2735 <dimIncrement>4</dimIncrement> 2736 <name>TAGMIC[%s]</name> 2737 <description>TAG/MIC Registers.</description> 2738 <addressOffset>0xE0</addressOffset> 2739 <fields> 2740 <field> 2741 <name>LENGTH</name> 2742 <description>TAG/MIC output for AES GCM and CCM operations.</description> 2743 <bitOffset>0</bitOffset> 2744 <bitWidth>32</bitWidth> 2745 </field> 2746 </fields> 2747 </register> 2748 <register> 2749 <name>SCA_CTRL0</name> 2750 <description>SCA Control 0 Register.</description> 2751 <addressOffset>0x100</addressOffset> 2752 <fields> 2753 <field> 2754 <name>STC</name> 2755 <description>Start Calculation.</description> 2756 <bitOffset>0</bitOffset> 2757 <bitWidth>1</bitWidth> 2758 </field> 2759 <field> 2760 <name>SCAIE</name> 2761 <description>SCA Interrupt Enable.</description> 2762 <bitOffset>1</bitOffset> 2763 <bitWidth>1</bitWidth> 2764 <enumeratedValues> 2765 <enumeratedValue> 2766 <name>disable</name> 2767 <description>Disable</description> 2768 <value>0</value> 2769 </enumeratedValue> 2770 <enumeratedValue> 2771 <name>enable</name> 2772 <description>Enable</description> 2773 <value>1</value> 2774 </enumeratedValue> 2775 </enumeratedValues> 2776 </field> 2777 <field> 2778 <name>ABORT</name> 2779 <description>Abort Operation.</description> 2780 <bitOffset>2</bitOffset> 2781 <bitWidth>1</bitWidth> 2782 </field> 2783 <field> 2784 <name>ERMEM</name> 2785 <description>Erase Cryptographic Memory.</description> 2786 <bitOffset>4</bitOffset> 2787 <bitWidth>1</bitWidth> 2788 </field> 2789 <field> 2790 <name>MANPARAM</name> 2791 <description>ECC Parameter Source.</description> 2792 <bitOffset>5</bitOffset> 2793 <bitWidth>1</bitWidth> 2794 </field> 2795 <field> 2796 <name>HWKEY</name> 2797 <description>Hardware Key Select.</description> 2798 <bitOffset>6</bitOffset> 2799 <bitWidth>1</bitWidth> 2800 </field> 2801 <field> 2802 <name>OPCODE</name> 2803 <description>SCA Opcode.</description> 2804 <bitOffset>8</bitOffset> 2805 <bitWidth>5</bitWidth> 2806 </field> 2807 <field> 2808 <name>MODADDR</name> 2809 <description>MODULO Address Offset.</description> 2810 <bitOffset>16</bitOffset> 2811 <bitWidth>5</bitWidth> 2812 </field> 2813 <field> 2814 <name>ECCSIZE</name> 2815 <description>ECC Size.</description> 2816 <bitOffset>24</bitOffset> 2817 <bitWidth>2</bitWidth> 2818 </field> 2819 </fields> 2820 </register> 2821 <register> 2822 <name>SCA_CTRL1</name> 2823 <description>SCA Advanced Control Register.</description> 2824 <addressOffset>0x104</addressOffset> 2825 <fields> 2826 <field> 2827 <name>MAN</name> 2828 <description>SCA Mode.</description> 2829 <bitOffset>0</bitOffset> 2830 <bitWidth>1</bitWidth> 2831 <enumeratedValues> 2832 <enumeratedValue> 2833 <name>auto</name> 2834 <description>Auto Mode</description> 2835 <value>0</value> 2836 </enumeratedValue> 2837 <enumeratedValue> 2838 <name>manual</name> 2839 <description>Manual Mode</description> 2840 <value>1</value> 2841 </enumeratedValue> 2842 </enumeratedValues> 2843 </field> 2844 <field> 2845 <name>AUTOCARRY</name> 2846 <description>Automatically propagate the carry for the next operation.</description> 2847 <bitOffset>1</bitOffset> 2848 <bitWidth>1</bitWidth> 2849 </field> 2850 <field> 2851 <name>PLUSONE</name> 2852 <description>Enable Carry propagation for the next operation.</description> 2853 <bitOffset>2</bitOffset> 2854 <bitWidth>1</bitWidth> 2855 </field> 2856 <field> 2857 <name>RESSELECT</name> 2858 <description>ALU Selection.</description> 2859 <bitOffset>3</bitOffset> 2860 <bitWidth>2</bitWidth> 2861 </field> 2862 <field> 2863 <name>CARRYPOS</name> 2864 <description>To set Carry location.</description> 2865 <bitOffset>8</bitOffset> 2866 <bitWidth>10</bitWidth> 2867 </field> 2868 </fields> 2869 </register> 2870 <register> 2871 <name>SCA_STAT</name> 2872 <description>SCA Status Register.</description> 2873 <addressOffset>0x108</addressOffset> 2874 <fields> 2875 <field> 2876 <name>BUSY</name> 2877 <description>SCA Busy.</description> 2878 <bitOffset>0</bitOffset> 2879 <bitWidth>1</bitWidth> 2880 </field> 2881 <field> 2882 <name>SCAIF</name> 2883 <description>SCA Interrupt Flag.</description> 2884 <bitOffset>1</bitOffset> 2885 <bitWidth>1</bitWidth> 2886 </field> 2887 <field> 2888 <name>PVF1</name> 2889 <description>Point 1 Verification Failed.</description> 2890 <bitOffset>2</bitOffset> 2891 <bitWidth>1</bitWidth> 2892 </field> 2893 <field> 2894 <name>PVF2</name> 2895 <description>Point 2 Verification Failed.</description> 2896 <bitOffset>3</bitOffset> 2897 <bitWidth>1</bitWidth> 2898 </field> 2899 <field> 2900 <name>FSMERR</name> 2901 <description>FSM Transition Error.</description> 2902 <bitOffset>4</bitOffset> 2903 <bitWidth>1</bitWidth> 2904 </field> 2905 <field> 2906 <name>COMPERR</name> 2907 <description>EC Computation Error.</description> 2908 <bitOffset>5</bitOffset> 2909 <bitWidth>1</bitWidth> 2910 </field> 2911 <field> 2912 <name>MEMERR</name> 2913 <description>SCA Memory Access Error.</description> 2914 <bitOffset>6</bitOffset> 2915 <bitWidth>1</bitWidth> 2916 </field> 2917 <field> 2918 <name>CARRY</name> 2919 <description>Carry on ongoing operation.</description> 2920 <bitOffset>8</bitOffset> 2921 <bitWidth>1</bitWidth> 2922 </field> 2923 <field> 2924 <name>GTE2I2</name> 2925 <description>Modulo 2x Result.</description> 2926 <bitOffset>9</bitOffset> 2927 <bitWidth>1</bitWidth> 2928 </field> 2929 <field> 2930 <name>ALUNEG1</name> 2931 <description>ALU 2 SubSign of the subtraction result for ALU_2.</description> 2932 <bitOffset>10</bitOffset> 2933 <bitWidth>1</bitWidth> 2934 </field> 2935 <field> 2936 <name>ALUNEG2</name> 2937 <description>ALU 2 SubSign of the subtraction result for ALU_2.</description> 2938 <bitOffset>11</bitOffset> 2939 <bitWidth>1</bitWidth> 2940 </field> 2941 </fields> 2942 </register> 2943 <register> 2944 <name>SCA_PPX_ADDR</name> 2945 <description>PPX Coordinate Data Pointer Register.</description> 2946 <addressOffset>0x10C</addressOffset> 2947 <resetValue>0x0</resetValue> 2948 <fields> 2949 <field> 2950 <name>ADDR</name> 2951 <description>Point P Coordinate Data Pointer.</description> 2952 <bitOffset>0</bitOffset> 2953 <bitWidth>32</bitWidth> 2954 </field> 2955 </fields> 2956 </register> 2957 <register> 2958 <name>SCA_PPY_ADDR</name> 2959 <description>PPY Coordinate Data Pointer Register.</description> 2960 <addressOffset>0x110</addressOffset> 2961 <resetValue>0x0</resetValue> 2962 <fields> 2963 <field> 2964 <name>ADDR</name> 2965 <description>Point P Coordinate Data Pointer.</description> 2966 <bitOffset>0</bitOffset> 2967 <bitWidth>32</bitWidth> 2968 </field> 2969 </fields> 2970 </register> 2971 <register> 2972 <name>SCA_PPZ_ADDR</name> 2973 <description>PPZ Coordinate Data Pointer Register.</description> 2974 <addressOffset>0x114</addressOffset> 2975 <resetValue>0x0</resetValue> 2976 <fields> 2977 <field> 2978 <name>ADDR</name> 2979 <description>Point P Coordinate Data Pointer.</description> 2980 <bitOffset>0</bitOffset> 2981 <bitWidth>32</bitWidth> 2982 </field> 2983 </fields> 2984 </register> 2985 <register> 2986 <name>SCA_PQX_ADDR</name> 2987 <description>PQX Coordinate Data Pointer Register.</description> 2988 <addressOffset>0x118</addressOffset> 2989 <resetValue>0x0</resetValue> 2990 <fields> 2991 <field> 2992 <name>ADDR</name> 2993 <description>Point Q Coordinate Data Pointer.</description> 2994 <bitOffset>0</bitOffset> 2995 <bitWidth>32</bitWidth> 2996 </field> 2997 </fields> 2998 </register> 2999 <register> 3000 <name>SCA_PQY_ADDR</name> 3001 <description>PQY Coordinate Data Pointer Register.</description> 3002 <addressOffset>0x11C</addressOffset> 3003 <resetValue>0x0</resetValue> 3004 <fields> 3005 <field> 3006 <name>ADDR</name> 3007 <description>Point Q Coordinate Data Pointer.</description> 3008 <bitOffset>0</bitOffset> 3009 <bitWidth>32</bitWidth> 3010 </field> 3011 </fields> 3012 </register> 3013 <register> 3014 <name>SCA_PQZ_ADDR</name> 3015 <description>PQZ Coordinate Data Pointer Register.</description> 3016 <addressOffset>0x120</addressOffset> 3017 <resetValue>0x0</resetValue> 3018 <fields> 3019 <field> 3020 <name>ADDR</name> 3021 <description>Point Q Coordinate Data Pointer.</description> 3022 <bitOffset>0</bitOffset> 3023 <bitWidth>32</bitWidth> 3024 </field> 3025 </fields> 3026 </register> 3027 <register> 3028 <name>SCA_RDSA_ADDR</name> 3029 <description>SCA RDSA Address Register.</description> 3030 <addressOffset>0x124</addressOffset> 3031 <resetValue>0x0</resetValue> 3032 <fields> 3033 <field> 3034 <name>ADDR</name> 3035 <description>The starting address of the R portion for R, S ECDSA signature.</description> 3036 <bitOffset>0</bitOffset> 3037 <bitWidth>32</bitWidth> 3038 </field> 3039 </fields> 3040 </register> 3041 <register> 3042 <name>SCA_RES_ADDR</name> 3043 <description>SCA Result Address Register.</description> 3044 <addressOffset>0x128</addressOffset> 3045 <resetValue>0x0</resetValue> 3046 <fields> 3047 <field> 3048 <name>ADDR</name> 3049 <description>Starting address of result storage.</description> 3050 <bitOffset>0</bitOffset> 3051 <bitWidth>32</bitWidth> 3052 </field> 3053 </fields> 3054 </register> 3055 <register> 3056 <name>SCA_OP_BUFF_ADDR</name> 3057 <description>SCA Operation Buffer Address Register.</description> 3058 <addressOffset>0x12C</addressOffset> 3059 <resetValue>0x0</resetValue> 3060 <fields> 3061 <field> 3062 <name>ADDR</name> 3063 <description>Starting address of operation buffer.</description> 3064 <bitOffset>0</bitOffset> 3065 <bitWidth>32</bitWidth> 3066 </field> 3067 </fields> 3068 </register> 3069 <register> 3070 <name>SCA_MODDATA</name> 3071 <description>SCA Modulo Data Input Register.</description> 3072 <addressOffset>0x130</addressOffset> 3073 <resetValue>0x0</resetValue> 3074 <fields> 3075 <field> 3076 <name>DATA</name> 3077 <description>Used to load the SCA modulo for modular operations.</description> 3078 <bitOffset>0</bitOffset> 3079 <bitWidth>32</bitWidth> 3080 </field> 3081 </fields> 3082 </register> 3083 </registers> 3084 </peripheral> 3085<!--CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.--> 3086 <peripheral> 3087 <name>DMA</name> 3088 <description>DMA Controller Fully programmable, chaining capable DMA channels.</description> 3089 <baseAddress>0x40028000</baseAddress> 3090 <size>32</size> 3091 <addressBlock> 3092 <offset>0x00</offset> 3093 <size>0x1000</size> 3094 <usage>registers</usage> 3095 </addressBlock> 3096 <interrupt> 3097 <name>DMA0</name> 3098 <value>28</value> 3099 </interrupt> 3100 <interrupt> 3101 <name>DMA1</name> 3102 <value>29</value> 3103 </interrupt> 3104 <interrupt> 3105 <name>DMA2</name> 3106 <value>30</value> 3107 </interrupt> 3108 <interrupt> 3109 <name>DMA3</name> 3110 <value>31</value> 3111 </interrupt> 3112 <interrupt> 3113 <name>DMA4</name> 3114 <value>68</value> 3115 </interrupt> 3116 <interrupt> 3117 <name>DMA5</name> 3118 <value>69</value> 3119 </interrupt> 3120 <interrupt> 3121 <name>DMA6</name> 3122 <value>70</value> 3123 </interrupt> 3124 <interrupt> 3125 <name>DMA7</name> 3126 <value>71</value> 3127 </interrupt> 3128 <interrupt> 3129 <name>DMA8</name> 3130 <value>72</value> 3131 </interrupt> 3132 <interrupt> 3133 <name>DMA9</name> 3134 <value>73</value> 3135 </interrupt> 3136 <interrupt> 3137 <name>DMA10</name> 3138 <value>74</value> 3139 </interrupt> 3140 <interrupt> 3141 <name>DMA11</name> 3142 <value>75</value> 3143 </interrupt> 3144 <interrupt> 3145 <name>DMA12</name> 3146 <value>76</value> 3147 </interrupt> 3148 <interrupt> 3149 <name>DMA13</name> 3150 <value>77</value> 3151 </interrupt> 3152 <interrupt> 3153 <name>DMA14</name> 3154 <value>78</value> 3155 </interrupt> 3156 <interrupt> 3157 <name>DMA15</name> 3158 <value>79</value> 3159 </interrupt> 3160 <registers> 3161 <register> 3162 <name>CN</name> 3163 <description>DMA Control Register.</description> 3164 <addressOffset>0x000</addressOffset> 3165 <fields> 3166 <field> 3167 <name>CH0_IEN</name> 3168 <description>Channel 0 Interrupt Enable.</description> 3169 <bitOffset>0</bitOffset> 3170 <bitWidth>1</bitWidth> 3171 <enumeratedValues> 3172 <enumeratedValue> 3173 <name>dis</name> 3174 <description>Disable.</description> 3175 <value>0</value> 3176 </enumeratedValue> 3177 <enumeratedValue> 3178 <name>en</name> 3179 <description>Enable.</description> 3180 <value>1</value> 3181 </enumeratedValue> 3182 </enumeratedValues> 3183 </field> 3184 <field derivedFrom="CH0_IEN"> 3185 <name>CH2_IEN</name> 3186 <description>Channel 2 Interrupt Enable.</description> 3187 <bitOffset>2</bitOffset> 3188 <bitWidth>1</bitWidth> 3189 </field> 3190 <field derivedFrom="CH0_IEN"> 3191 <name>CH3_IEN</name> 3192 <description>Channel 3 Interrupt Enable.</description> 3193 <bitOffset>3</bitOffset> 3194 <bitWidth>1</bitWidth> 3195 </field> 3196 <field derivedFrom="CH0_IEN"> 3197 <name>CH4_IEN</name> 3198 <description>Channel 4 Interrupt Enable.</description> 3199 <bitOffset>4</bitOffset> 3200 <bitWidth>1</bitWidth> 3201 </field> 3202 <field derivedFrom="CH0_IEN"> 3203 <name>CH5_IEN</name> 3204 <description>Channel 5 Interrupt Enable.</description> 3205 <bitOffset>5</bitOffset> 3206 <bitWidth>1</bitWidth> 3207 </field> 3208 <field derivedFrom="CH0_IEN"> 3209 <name>CH6_IEN</name> 3210 <description>Channel 6 Interrupt Enable.</description> 3211 <bitOffset>6</bitOffset> 3212 <bitWidth>1</bitWidth> 3213 </field> 3214 <field derivedFrom="CH0_IEN"> 3215 <name>CH7_IEN</name> 3216 <description>Channel 7 Interrupt Enable.</description> 3217 <bitOffset>7</bitOffset> 3218 <bitWidth>1</bitWidth> 3219 </field> 3220 </fields> 3221 </register> 3222 <register> 3223 <name>INTR</name> 3224 <description>DMA Interrupt Register.</description> 3225 <addressOffset>0x004</addressOffset> 3226 <access>read-only</access> 3227 <fields> 3228 <field> 3229 <name>CH0_IPEND</name> 3230 <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description> 3231 <bitOffset>0</bitOffset> 3232 <bitWidth>1</bitWidth> 3233 <enumeratedValues> 3234 <enumeratedValue> 3235 <name>inactive</name> 3236 <description>No interrupt is pending.</description> 3237 <value>0</value> 3238 </enumeratedValue> 3239 <enumeratedValue> 3240 <name>pending</name> 3241 <description>An interrupt is pending.</description> 3242 <value>1</value> 3243 </enumeratedValue> 3244 </enumeratedValues> 3245 </field> 3246 <field derivedFrom="CH0_IPEND"> 3247 <name>CH1_IPEND</name> 3248 <bitOffset>1</bitOffset> 3249 <bitWidth>1</bitWidth> 3250 </field> 3251 <field derivedFrom="CH0_IPEND"> 3252 <name>CH2_IPEND</name> 3253 <bitOffset>2</bitOffset> 3254 <bitWidth>1</bitWidth> 3255 </field> 3256 <field derivedFrom="CH0_IPEND"> 3257 <name>CH3_IPEND</name> 3258 <bitOffset>3</bitOffset> 3259 <bitWidth>1</bitWidth> 3260 </field> 3261 <field derivedFrom="CH0_IPEND"> 3262 <name>CH4_IPEND</name> 3263 <bitOffset>4</bitOffset> 3264 <bitWidth>1</bitWidth> 3265 </field> 3266 <field derivedFrom="CH0_IPEND"> 3267 <name>CH5_IPEND</name> 3268 <bitOffset>5</bitOffset> 3269 <bitWidth>1</bitWidth> 3270 </field> 3271 <field derivedFrom="CH0_IPEND"> 3272 <name>CH6_IPEND</name> 3273 <bitOffset>6</bitOffset> 3274 <bitWidth>1</bitWidth> 3275 </field> 3276 <field derivedFrom="CH0_IPEND"> 3277 <name>CH7_IPEND</name> 3278 <bitOffset>7</bitOffset> 3279 <bitWidth>1</bitWidth> 3280 </field> 3281 </fields> 3282 </register> 3283 <cluster> 3284 <dim>8</dim> 3285 <dimIncrement>0x20</dimIncrement> 3286 <name>CH[%s]</name> 3287 <description>DMA Channel registers.</description> 3288 <headerStructName>dma_ch</headerStructName> 3289 <addressOffset>0x100</addressOffset> 3290 <access>read-write</access> 3291 <register> 3292 <name>CFG</name> 3293 <description>DMA Channel Configuration Register.</description> 3294 <addressOffset>0x000</addressOffset> 3295 <fields> 3296 <field> 3297 <name>CHEN</name> 3298 <description>Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description> 3299 <bitOffset>0</bitOffset> 3300 <bitWidth>1</bitWidth> 3301 <enumeratedValues> 3302 <enumeratedValue> 3303 <name>dis</name> 3304 <description>Disable.</description> 3305 <value>0</value> 3306 </enumeratedValue> 3307 <enumeratedValue> 3308 <name>en</name> 3309 <description>Enable.</description> 3310 <value>1</value> 3311 </enumeratedValue> 3312 </enumeratedValues> 3313 </field> 3314 <field> 3315 <name>RLDEN</name> 3316 <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description> 3317 <bitOffset>1</bitOffset> 3318 <bitWidth>1</bitWidth> 3319 <enumeratedValues> 3320 <enumeratedValue> 3321 <name>dis</name> 3322 <description>Disable.</description> 3323 <value>0</value> 3324 </enumeratedValue> 3325 <enumeratedValue> 3326 <name>en</name> 3327 <description>Enable.</description> 3328 <value>1</value> 3329 </enumeratedValue> 3330 </enumeratedValues> 3331 </field> 3332 <field> 3333 <name>PRI</name> 3334 <description>DMA Priority.</description> 3335 <bitOffset>2</bitOffset> 3336 <bitWidth>2</bitWidth> 3337 <enumeratedValues> 3338 <enumeratedValue> 3339 <name>high</name> 3340 <description>Highest Priority.</description> 3341 <value>0</value> 3342 </enumeratedValue> 3343 <enumeratedValue> 3344 <name>medHigh</name> 3345 <description>Medium High Priority.</description> 3346 <value>1</value> 3347 </enumeratedValue> 3348 <enumeratedValue> 3349 <name>medLow</name> 3350 <description>Medium Low Priority.</description> 3351 <value>2</value> 3352 </enumeratedValue> 3353 <enumeratedValue> 3354 <name>low</name> 3355 <description>Lowest Priority.</description> 3356 <value>3</value> 3357 </enumeratedValue> 3358 </enumeratedValues> 3359 </field> 3360 <field> 3361 <name>REQSEL</name> 3362 <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description> 3363 <bitOffset>4</bitOffset> 3364 <bitWidth>6</bitWidth> 3365 <enumeratedValues> 3366 <enumeratedValue> 3367 <name>MEMTOMEM</name> 3368 <description>Memory To Memory</description> 3369 <value>0x00</value> 3370 </enumeratedValue> 3371 <enumeratedValue> 3372 <name>SPI0RX</name> 3373 <description>SPI0 RX</description> 3374 <value>0x01</value> 3375 </enumeratedValue> 3376 <enumeratedValue> 3377 <name>SPI1RX</name> 3378 <description>SPI1 RX</description> 3379 <value>0x02</value> 3380 </enumeratedValue> 3381 <enumeratedValue> 3382 <name>UART0RX</name> 3383 <description>UART0 RX</description> 3384 <value>0x04</value> 3385 </enumeratedValue> 3386 <enumeratedValue> 3387 <name>UART1RX</name> 3388 <description>UART1 RX</description> 3389 <value>0x05</value> 3390 </enumeratedValue> 3391 <enumeratedValue> 3392 <name>I2C0RX</name> 3393 <description>I2C0 RX</description> 3394 <value>0x07</value> 3395 </enumeratedValue> 3396 <enumeratedValue> 3397 <name>I2C1RX</name> 3398 <description>I2C1 RX</description> 3399 <value>0x08</value> 3400 </enumeratedValue> 3401 <enumeratedValue> 3402 <name>ADC</name> 3403 <description>Analog-to-Digital Converter Channel</description> 3404 <value>0x09</value> 3405 </enumeratedValue> 3406 <enumeratedValue> 3407 <name>I2C2RX</name> 3408 <description>I2C2 RX</description> 3409 <value>0x0A</value> 3410 </enumeratedValue> 3411 <enumeratedValue> 3412 <name>UART2RX</name> 3413 <description>UART2 RX</description> 3414 <value>0x0E</value> 3415 </enumeratedValue> 3416 <enumeratedValue> 3417 <name>SPI2RX</name> 3418 <description>SPI2 RX</description> 3419 <value>0x0F</value> 3420 </enumeratedValue> 3421 <enumeratedValue> 3422 <name>USBRXEP1</name> 3423 <description>USB Endpoint 1 RX</description> 3424 <value>0x11</value> 3425 </enumeratedValue> 3426 <enumeratedValue> 3427 <name>USBRXEP2</name> 3428 <description>USB Endpoint 2 RX</description> 3429 <value>0x12</value> 3430 </enumeratedValue> 3431 <enumeratedValue> 3432 <name>USBRXEP3</name> 3433 <description>USB Endpoint 3 RX</description> 3434 <value>0x13</value> 3435 </enumeratedValue> 3436 <enumeratedValue> 3437 <name>USBRXEP4</name> 3438 <description>USB Endpoint 4 RX</description> 3439 <value>0x14</value> 3440 </enumeratedValue> 3441 <enumeratedValue> 3442 <name>USBRXEP5</name> 3443 <description>USB Endpoint 5 RX</description> 3444 <value>0x15</value> 3445 </enumeratedValue> 3446 <enumeratedValue> 3447 <name>USBRXEP6</name> 3448 <description>USB Endpoint 6 RX</description> 3449 <value>0x16</value> 3450 </enumeratedValue> 3451 <enumeratedValue> 3452 <name>USBRXEP7</name> 3453 <description>USB Endpoint 7 RX</description> 3454 <value>0x17</value> 3455 </enumeratedValue> 3456 <enumeratedValue> 3457 <name>USBRXEP8</name> 3458 <description>USB Endpoint 8 RX</description> 3459 <value>0x18</value> 3460 </enumeratedValue> 3461 <enumeratedValue> 3462 <name>USBRXEP9</name> 3463 <description>USB Endpoint 9 RX</description> 3464 <value>0x19</value> 3465 </enumeratedValue> 3466 <enumeratedValue> 3467 <name>USBRXEP10</name> 3468 <description>USB Endpoint 10 RX</description> 3469 <value>0x1A</value> 3470 </enumeratedValue> 3471 <enumeratedValue> 3472 <name>USBRXEP11</name> 3473 <description>USB Endpoint 11 RX</description> 3474 <value>0x1B</value> 3475 </enumeratedValue> 3476 <enumeratedValue> 3477 <name>SPI0TX</name> 3478 <description>SPI0 TX</description> 3479 <value>0x21</value> 3480 </enumeratedValue> 3481 <enumeratedValue> 3482 <name>SPI1TX</name> 3483 <description>SPI1 TX</description> 3484 <value>0x22</value> 3485 </enumeratedValue> 3486 <enumeratedValue> 3487 <name>UART0TX</name> 3488 <description>UART0 TX</description> 3489 <value>0x24</value> 3490 </enumeratedValue> 3491 <enumeratedValue> 3492 <name>UART1TX</name> 3493 <description>UART1 TX</description> 3494 <value>0x25</value> 3495 </enumeratedValue> 3496 <enumeratedValue> 3497 <name>I2C0TX</name> 3498 <description>I2C0 TX</description> 3499 <value>0x27</value> 3500 </enumeratedValue> 3501 <enumeratedValue> 3502 <name>I2C1TX</name> 3503 <description>I2C1 TX</description> 3504 <value>0x28</value> 3505 </enumeratedValue> 3506 <enumeratedValue> 3507 <name>I2C2TX</name> 3508 <description>I2C2 TX</description> 3509 <value>0x2A</value> 3510 </enumeratedValue> 3511 <enumeratedValue> 3512 <name>UART2TX</name> 3513 <description>UART2 TX</description> 3514 <value>0x2E</value> 3515 </enumeratedValue> 3516 <enumeratedValue> 3517 <name>SPI2TX</name> 3518 <description>SPI3 TX</description> 3519 <value>0x2F</value> 3520 </enumeratedValue> 3521 <enumeratedValue> 3522 <name>USBTXEP1</name> 3523 <description>USB Endpoint 1 TX</description> 3524 <value>0x31</value> 3525 </enumeratedValue> 3526 <enumeratedValue> 3527 <name>USBTXEP2</name> 3528 <description>USB Endpoint 2 TX</description> 3529 <value>0x32</value> 3530 </enumeratedValue> 3531 <enumeratedValue> 3532 <name>USBTXEP3</name> 3533 <description>USB Endpoint 3 TX</description> 3534 <value>0x33</value> 3535 </enumeratedValue> 3536 <enumeratedValue> 3537 <name>USBTXEP4</name> 3538 <description>USB Endpoint 4 TX</description> 3539 <value>0x34</value> 3540 </enumeratedValue> 3541 <enumeratedValue> 3542 <name>USBTXEP5</name> 3543 <description>USB Endpoint 5 TX</description> 3544 <value>0x35</value> 3545 </enumeratedValue> 3546 <enumeratedValue> 3547 <name>USBTXEP6</name> 3548 <description>USB Endpoint 6 TX</description> 3549 <value>0x36</value> 3550 </enumeratedValue> 3551 <enumeratedValue> 3552 <name>USBTXEP7</name> 3553 <description>USB Endpoint 7 TX</description> 3554 <value>0x37</value> 3555 </enumeratedValue> 3556 <enumeratedValue> 3557 <name>USBTXEP8</name> 3558 <description>USB Endpoint 8 TX</description> 3559 <value>0x38</value> 3560 </enumeratedValue> 3561 <enumeratedValue> 3562 <name>USBTXEP9</name> 3563 <description>USB Endpoint 9 TX</description> 3564 <value>0x39</value> 3565 </enumeratedValue> 3566 <enumeratedValue> 3567 <name>USBTXEP10</name> 3568 <description>USB Endpoint 10 TX</description> 3569 <value>0x3A</value> 3570 </enumeratedValue> 3571 <enumeratedValue> 3572 <name>USBTXEP11</name> 3573 <description>USB Endpoint 11 TX</description> 3574 <value>0x3B</value> 3575 </enumeratedValue> 3576 </enumeratedValues> 3577 </field> 3578 <field> 3579 <name>REQWAIT</name> 3580 <description>Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.</description> 3581 <bitOffset>10</bitOffset> 3582 <bitWidth>1</bitWidth> 3583 <enumeratedValues> 3584 <enumeratedValue> 3585 <name>dis</name> 3586 <description>Disable.</description> 3587 <value>0</value> 3588 </enumeratedValue> 3589 <enumeratedValue> 3590 <name>en</name> 3591 <description>Enable.</description> 3592 <value>1</value> 3593 </enumeratedValue> 3594 </enumeratedValues> 3595 </field> 3596 <field> 3597 <name>TOSEL</name> 3598 <description>Timeout Period Select.</description> 3599 <bitOffset>11</bitOffset> 3600 <bitWidth>3</bitWidth> 3601 <enumeratedValues> 3602 <enumeratedValue> 3603 <name>to4</name> 3604 <description>Timeout of 3 to 4 prescale clocks.</description> 3605 <value>0</value> 3606 </enumeratedValue> 3607 <enumeratedValue> 3608 <name>to8</name> 3609 <description>Timeout of 7 to 8 prescale clocks.</description> 3610 <value>1</value> 3611 </enumeratedValue> 3612 <enumeratedValue> 3613 <name>to16</name> 3614 <description>Timeout of 15 to 16 prescale clocks.</description> 3615 <value>2</value> 3616 </enumeratedValue> 3617 <enumeratedValue> 3618 <name>to32</name> 3619 <description>Timeout of 31 to 32 prescale clocks.</description> 3620 <value>3</value> 3621 </enumeratedValue> 3622 <enumeratedValue> 3623 <name>to64</name> 3624 <description>Timeout of 63 to 64 prescale clocks.</description> 3625 <value>4</value> 3626 </enumeratedValue> 3627 <enumeratedValue> 3628 <name>to128</name> 3629 <description>Timeout of 127 to 128 prescale clocks.</description> 3630 <value>5</value> 3631 </enumeratedValue> 3632 <enumeratedValue> 3633 <name>to256</name> 3634 <description>Timeout of 255 to 256 prescale clocks.</description> 3635 <value>6</value> 3636 </enumeratedValue> 3637 <enumeratedValue> 3638 <name>to512</name> 3639 <description>Timeout of 511 to 512 prescale clocks.</description> 3640 <value>7</value> 3641 </enumeratedValue> 3642 </enumeratedValues> 3643 </field> 3644 <field> 3645 <name>PSSEL</name> 3646 <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description> 3647 <bitOffset>14</bitOffset> 3648 <bitWidth>2</bitWidth> 3649 <enumeratedValues> 3650 <enumeratedValue> 3651 <name>dis</name> 3652 <description>Disable timer.</description> 3653 <value>0</value> 3654 </enumeratedValue> 3655 <enumeratedValue> 3656 <name>div256</name> 3657 <description>hclk / 256.</description> 3658 <value>1</value> 3659 </enumeratedValue> 3660 <enumeratedValue> 3661 <name>div64k</name> 3662 <description>hclk / 64k.</description> 3663 <value>2</value> 3664 </enumeratedValue> 3665 <enumeratedValue> 3666 <name>div16M</name> 3667 <description>hclk / 16M.</description> 3668 <value>3</value> 3669 </enumeratedValue> 3670 </enumeratedValues> 3671 </field> 3672 <field> 3673 <name>SRCWD</name> 3674 <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description> 3675 <bitOffset>16</bitOffset> 3676 <bitWidth>2</bitWidth> 3677 <enumeratedValues> 3678 <enumeratedValue> 3679 <name>byte</name> 3680 <description>Byte.</description> 3681 <value>0</value> 3682 </enumeratedValue> 3683 <enumeratedValue> 3684 <name>halfWord</name> 3685 <description>Halfword.</description> 3686 <value>1</value> 3687 </enumeratedValue> 3688 <enumeratedValue> 3689 <name>word</name> 3690 <description>Word.</description> 3691 <value>2</value> 3692 </enumeratedValue> 3693 </enumeratedValues> 3694 </field> 3695 <field> 3696 <name>SRCINC</name> 3697 <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description> 3698 <bitOffset>18</bitOffset> 3699 <bitWidth>1</bitWidth> 3700 <enumeratedValues> 3701 <enumeratedValue> 3702 <name>dis</name> 3703 <description>Disable.</description> 3704 <value>0</value> 3705 </enumeratedValue> 3706 <enumeratedValue> 3707 <name>en</name> 3708 <description>Enable.</description> 3709 <value>1</value> 3710 </enumeratedValue> 3711 </enumeratedValues> 3712 </field> 3713 <field> 3714 <name>DSTWD</name> 3715 <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description> 3716 <bitOffset>20</bitOffset> 3717 <bitWidth>2</bitWidth> 3718 <enumeratedValues> 3719 <enumeratedValue> 3720 <name>byte</name> 3721 <description>Byte.</description> 3722 <value>0</value> 3723 </enumeratedValue> 3724 <enumeratedValue> 3725 <name>halfWord</name> 3726 <description>Halfword.</description> 3727 <value>1</value> 3728 </enumeratedValue> 3729 <enumeratedValue> 3730 <name>word</name> 3731 <description>Word.</description> 3732 <value>2</value> 3733 </enumeratedValue> 3734 </enumeratedValues> 3735 </field> 3736 <field> 3737 <name>DSTINC</name> 3738 <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description> 3739 <bitOffset>22</bitOffset> 3740 <bitWidth>1</bitWidth> 3741 <enumeratedValues> 3742 <enumeratedValue> 3743 <name>dis</name> 3744 <description>Disable.</description> 3745 <value>0</value> 3746 </enumeratedValue> 3747 <enumeratedValue> 3748 <name>en</name> 3749 <description>Enable.</description> 3750 <value>1</value> 3751 </enumeratedValue> 3752 </enumeratedValues> 3753 </field> 3754 <field> 3755 <name>BRST</name> 3756 <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.</description> 3757 <bitOffset>24</bitOffset> 3758 <bitWidth>5</bitWidth> 3759 </field> 3760 <field> 3761 <name>CHDIEN</name> 3762 <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description> 3763 <bitOffset>30</bitOffset> 3764 <bitWidth>1</bitWidth> 3765 <enumeratedValues> 3766 <enumeratedValue> 3767 <name>dis</name> 3768 <description>Disable.</description> 3769 <value>0</value> 3770 </enumeratedValue> 3771 <enumeratedValue> 3772 <name>en</name> 3773 <description>Enable.</description> 3774 <value>1</value> 3775 </enumeratedValue> 3776 </enumeratedValues> 3777 </field> 3778 <field> 3779 <name>CTZIEN</name> 3780 <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description> 3781 <bitOffset>31</bitOffset> 3782 <bitWidth>1</bitWidth> 3783 <enumeratedValues> 3784 <enumeratedValue> 3785 <name>dis</name> 3786 <description>Disable.</description> 3787 <value>0</value> 3788 </enumeratedValue> 3789 <enumeratedValue> 3790 <name>en</name> 3791 <description>Enable.</description> 3792 <value>1</value> 3793 </enumeratedValue> 3794 </enumeratedValues> 3795 </field> 3796 </fields> 3797 </register> 3798 <register> 3799 <name>ST</name> 3800 <description>DMA Channel Status Register.</description> 3801 <addressOffset>0x004</addressOffset> 3802 <fields> 3803 <field> 3804 <name>CH_ST</name> 3805 <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description> 3806 <bitOffset>0</bitOffset> 3807 <bitWidth>1</bitWidth> 3808 <access>read-only</access> 3809 <enumeratedValues> 3810 <enumeratedValue> 3811 <name>dis</name> 3812 <description>Disable.</description> 3813 <value>0</value> 3814 </enumeratedValue> 3815 <enumeratedValue> 3816 <name>en</name> 3817 <description>Enable.</description> 3818 <value>1</value> 3819 </enumeratedValue> 3820 </enumeratedValues> 3821 </field> 3822 <field> 3823 <name>IPEND</name> 3824 <description>Channel Interrupt.</description> 3825 <bitOffset>1</bitOffset> 3826 <bitWidth>1</bitWidth> 3827 <access>read-only</access> 3828 <enumeratedValues> 3829 <enumeratedValue> 3830 <name>inactive</name> 3831 <description>No interrupt is pending.</description> 3832 <value>0</value> 3833 </enumeratedValue> 3834 <enumeratedValue> 3835 <name>pending</name> 3836 <description>An interrupt is pending.</description> 3837 <value>1</value> 3838 </enumeratedValue> 3839 </enumeratedValues> 3840 </field> 3841 <field> 3842 <name>CTZ_ST</name> 3843 <description>Count-to-Zero (CTZ) Event Interrupt Flag</description> 3844 <bitOffset>2</bitOffset> 3845 <bitWidth>1</bitWidth> 3846 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3847 </field> 3848 <field> 3849 <name>RLD_ST</name> 3850 <description>Reload Event Interrupt Flag.</description> 3851 <bitOffset>3</bitOffset> 3852 <bitWidth>1</bitWidth> 3853 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3854 </field> 3855 <field> 3856 <name>BUS_ERR</name> 3857 <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description> 3858 <bitOffset>4</bitOffset> 3859 <bitWidth>1</bitWidth> 3860 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3861 </field> 3862 <field> 3863 <name>TO_ST</name> 3864 <description>Time-Out Event Interrupt Flag.</description> 3865 <bitOffset>6</bitOffset> 3866 <bitWidth>1</bitWidth> 3867 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3868 </field> 3869 </fields> 3870 </register> 3871 <register> 3872 <name>SRC</name> 3873 <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description> 3874 <addressOffset>0x008</addressOffset> 3875 <fields> 3876 <field> 3877 <name>SRC</name> 3878 <bitOffset>0</bitOffset> 3879 <bitWidth>32</bitWidth> 3880 </field> 3881 </fields> 3882 </register> 3883 <register> 3884 <name>DST</name> 3885 <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description> 3886 <addressOffset>0x00C</addressOffset> 3887 <fields> 3888 <field> 3889 <name>DST</name> 3890 <bitOffset>0</bitOffset> 3891 <bitWidth>32</bitWidth> 3892 </field> 3893 </fields> 3894 </register> 3895 <register> 3896 <name>CNT</name> 3897 <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description> 3898 <addressOffset>0x010</addressOffset> 3899 <fields> 3900 <field> 3901 <name>CNT</name> 3902 <description>DMA Counter.</description> 3903 <bitOffset>0</bitOffset> 3904 <bitWidth>24</bitWidth> 3905 </field> 3906 </fields> 3907 </register> 3908 <register> 3909 <name>SRC_RLD</name> 3910 <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description> 3911 <addressOffset>0x014</addressOffset> 3912 <fields> 3913 <field> 3914 <name>SRC_RLD</name> 3915 <description>Source Address Reload Value.</description> 3916 <bitOffset>0</bitOffset> 3917 <bitWidth>31</bitWidth> 3918 </field> 3919 </fields> 3920 </register> 3921 <register> 3922 <name>DST_RLD</name> 3923 <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description> 3924 <addressOffset>0x018</addressOffset> 3925 <fields> 3926 <field> 3927 <name>DST_RLD</name> 3928 <description>Destination Address Reload Value.</description> 3929 <bitOffset>0</bitOffset> 3930 <bitWidth>31</bitWidth> 3931 </field> 3932 </fields> 3933 </register> 3934 <register> 3935 <name>CNT_RLD</name> 3936 <description>DMA Channel Count Reload Register.</description> 3937 <addressOffset>0x01C</addressOffset> 3938 <fields> 3939 <field> 3940 <name>CNT_RLD</name> 3941 <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description> 3942 <bitOffset>0</bitOffset> 3943 <bitWidth>24</bitWidth> 3944 </field> 3945 <field> 3946 <name>RLDEN</name> 3947 <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description> 3948 <bitOffset>31</bitOffset> 3949 <bitWidth>1</bitWidth> 3950 <enumeratedValues> 3951 <enumeratedValue> 3952 <name>dis</name> 3953 <description>Disable.</description> 3954 <value>0</value> 3955 </enumeratedValue> 3956 <enumeratedValue> 3957 <name>en</name> 3958 <description>Enable.</description> 3959 <value>1</value> 3960 </enumeratedValue> 3961 </enumeratedValues> 3962 </field> 3963 </fields> 3964 </register> 3965 </cluster> 3966 </registers> 3967 </peripheral> 3968<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.--> 3969 <peripheral> 3970 <name>EMAC</name> 3971 <description>10/100 Ethernet MAC.</description> 3972 <baseAddress>0x4004F000</baseAddress> 3973 <addressBlock> 3974 <offset>0</offset> 3975 <size>0x1000</size> 3976 <usage>registers</usage> 3977 </addressBlock> 3978 <interrupt> 3979 <name>EMAC</name> 3980 <description>EMAC IRQ</description> 3981 <value>64</value> 3982 </interrupt> 3983 <registers> 3984 <register> 3985 <name>CN</name> 3986 <description>Network Control Register.</description> 3987 <addressOffset>0x00</addressOffset> 3988 <resetValue>0x00</resetValue> 3989 <fields> 3990 <field> 3991 <name>LB</name> 3992 <description>Loopback.</description> 3993 <bitOffset>0</bitOffset> 3994 <bitWidth>1</bitWidth> 3995 <access>read-write</access> 3996 </field> 3997 <field> 3998 <name>LBL</name> 3999 <description>Loopback local.</description> 4000 <bitOffset>1</bitOffset> 4001 <bitWidth>1</bitWidth> 4002 <access>read-write</access> 4003 </field> 4004 <field> 4005 <name>RXEN</name> 4006 <description>Receive Enable.</description> 4007 <bitOffset>2</bitOffset> 4008 <bitWidth>1</bitWidth> 4009 <access>read-write</access> 4010 </field> 4011 <field> 4012 <name>TXEN</name> 4013 <description>Transmit Enable.</description> 4014 <bitOffset>3</bitOffset> 4015 <bitWidth>1</bitWidth> 4016 <access>read-write</access> 4017 </field> 4018 <field> 4019 <name>MPEN</name> 4020 <description>Management Port Enable.</description> 4021 <bitOffset>4</bitOffset> 4022 <bitWidth>1</bitWidth> 4023 <access>read-write</access> 4024 </field> 4025 <field> 4026 <name>CLST</name> 4027 <description>Clear Statistics.</description> 4028 <bitOffset>5</bitOffset> 4029 <bitWidth>1</bitWidth> 4030 <access>write-only</access> 4031 </field> 4032 <field> 4033 <name>INCST</name> 4034 <description>Increment Statistics.</description> 4035 <bitOffset>6</bitOffset> 4036 <bitWidth>1</bitWidth> 4037 <access>write-only</access> 4038 </field> 4039 <field> 4040 <name>WREN</name> 4041 <description>Write enable for statistics registers.</description> 4042 <bitOffset>7</bitOffset> 4043 <bitWidth>1</bitWidth> 4044 <access>read-write</access> 4045 </field> 4046 <field> 4047 <name>BP</name> 4048 <description>Back pressure.</description> 4049 <bitOffset>8</bitOffset> 4050 <bitWidth>1</bitWidth> 4051 <access>read-write</access> 4052 </field> 4053 <field> 4054 <name>TXSTART</name> 4055 <description>Transmission start.</description> 4056 <bitOffset>9</bitOffset> 4057 <bitWidth>1</bitWidth> 4058 <access>write-only</access> 4059 </field> 4060 <field> 4061 <name>TXHALT</name> 4062 <description>Transmit halt.</description> 4063 <bitOffset>10</bitOffset> 4064 <bitWidth>1</bitWidth> 4065 <access>write-only</access> 4066 </field> 4067 <field> 4068 <name>TXPF</name> 4069 <description>Transmit pause frame.</description> 4070 <bitOffset>11</bitOffset> 4071 <bitWidth>1</bitWidth> 4072 <access>write-only</access> 4073 </field> 4074 <field> 4075 <name>TXZQPF</name> 4076 <description>Transmit zero quantum pause frame.</description> 4077 <bitOffset>12</bitOffset> 4078 <bitWidth>1</bitWidth> 4079 <access>write-only</access> 4080 </field> 4081 </fields> 4082 </register> 4083 <register> 4084 <name>CFG</name> 4085 <description>Network Configuration Register.</description> 4086 <addressOffset>0x04</addressOffset> 4087 <fields> 4088 <field> 4089 <name>SPEED</name> 4090 <description>Speed Select.</description> 4091 <bitOffset>0</bitOffset> 4092 <bitWidth>1</bitWidth> 4093 <access>read-write</access> 4094 </field> 4095 <field> 4096 <name>FULLDPLX</name> 4097 <description>Full Duplex. If set to 1 the transmit block ignores the state of collision and carrier sense and allows Rx while transmitting.</description> 4098 <bitOffset>1</bitOffset> 4099 <bitWidth>1</bitWidth> 4100 <access>read-write</access> 4101 </field> 4102 <field> 4103 <name>BITRATE</name> 4104 <description>Bit Rate. Writing 1 to this bit configures the interface for serial operation. </description> 4105 <bitOffset>2</bitOffset> 4106 <bitWidth>1</bitWidth> 4107 <access>read-write</access> 4108 </field> 4109 <field> 4110 <name>JUMBOFR</name> 4111 <description>Jumbo Frames. Writing 1 to this bit enables jumbo frames of up to 10,240 bytes to be accepted.</description> 4112 <bitOffset>3</bitOffset> 4113 <bitWidth>1</bitWidth> 4114 <access>read-write</access> 4115 </field> 4116 <field> 4117 <name>COPYAF</name> 4118 <description>Copy All Frames. If 1, all valid frames will be received.</description> 4119 <bitOffset>4</bitOffset> 4120 <bitWidth>1</bitWidth> 4121 <access>read-write</access> 4122 </field> 4123 <field> 4124 <name>NOBC</name> 4125 <description>No Broadcast. If 1, frames addressed to the broadcast address of all ones will not be received.</description> 4126 <bitOffset>5</bitOffset> 4127 <bitWidth>1</bitWidth> 4128 <access>write-only</access> 4129 </field> 4130 <field> 4131 <name>MHEN</name> 4132 <description>Multicast Hash Enable. If 1, multicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</description> 4133 <bitOffset>6</bitOffset> 4134 <bitWidth>1</bitWidth> 4135 <access>write-only</access> 4136 </field> 4137 <field> 4138 <name>UHEN</name> 4139 <description>Unicast Hash Enable. If 1, unicast frames will be received when the 6 bit hash function of the destination address points to a bit that is set in the hash register.</description> 4140 <bitOffset>7</bitOffset> 4141 <bitWidth>1</bitWidth> 4142 <access>read-write</access> 4143 </field> 4144 <field> 4145 <name>RXFR</name> 4146 <description>Receive 1536 Byte Frames. Writing 1 to this bit means the MAC receives packets up to 1536 bytes in length. Normally the MAC rejects any packet above 1518 bytes</description> 4147 <bitOffset>8</bitOffset> 4148 <bitWidth>1</bitWidth> 4149 <access>read-write</access> 4150 </field> 4151 <field> 4152 <name>MDCCLK</name> 4153 <description>MDC Frequency. Set according to PCLK speed. This field determines by what number PCLK is divided to generate MDC.</description> 4154 <bitOffset>10</bitOffset> 4155 <bitWidth>2</bitWidth> 4156 <access>write-only</access> 4157 <enumeratedValues> 4158 <enumeratedValue> 4159 <name>div8</name> 4160 <description>PCLK up to 20MHz</description> 4161 <value>0</value> 4162 </enumeratedValue> 4163 <enumeratedValue> 4164 <name>div16</name> 4165 <description>PCLK up to 40MHz</description> 4166 <value>1</value> 4167 </enumeratedValue> 4168 <enumeratedValue> 4169 <name>div32</name> 4170 <description>PCLK up to 80MHz</description> 4171 <value>2</value> 4172 </enumeratedValue> 4173 <enumeratedValue> 4174 <name>div64</name> 4175 <description>PCLK up to 160MHz</description> 4176 <value>3</value> 4177 </enumeratedValue> 4178 </enumeratedValues> 4179 </field> 4180 <field> 4181 <name>RTTST</name> 4182 <description>Retry Test. Must be set to zero for normal operation. If set to 1, the back-off between collisions is always one slot time.</description> 4183 <bitOffset>12</bitOffset> 4184 <bitWidth>1</bitWidth> 4185 <access>write-only</access> 4186 </field> 4187 <field> 4188 <name>PAUSEEN</name> 4189 <description>Pause Enable. If 1, Ethernet packet transmission pauses when a valid pause packet is received.</description> 4190 <bitOffset>13</bitOffset> 4191 <bitWidth>1</bitWidth> 4192 <access>write-only</access> 4193 </field> 4194 <field> 4195 <name>RXBUFFOFS</name> 4196 <description>Receive buffer offset. These bits indicate the number of bytes by which the received data is offset from the start of the first receive buffer.</description> 4197 <bitOffset>14</bitOffset> 4198 <bitWidth>2</bitWidth> 4199 <access>write-only</access> 4200 </field> 4201 <field> 4202 <name>RXLFCEN</name> 4203 <description>Receive length field checking enable. If 1, packets with measured lengths shorter than their length fields are discarded. Packets containing a type ID in bytes 13 and 14 (length/type field >=0600) are not counted as length errors.</description> 4204 <bitOffset>16</bitOffset> 4205 <bitWidth>1</bitWidth> 4206 <access>write-only</access> 4207 </field> 4208 <field> 4209 <name>DCRXFCS</name> 4210 <description>Discard receive FCS. If 1, the FCS field of received frames will not be copied to memory.</description> 4211 <bitOffset>17</bitOffset> 4212 <bitWidth>1</bitWidth> 4213 <access>write-only</access> 4214 </field> 4215 <field> 4216 <name>HDPLXRXEN</name> 4217 <description>Enable packets to be received in half-duplex mode while transmitting.</description> 4218 <bitOffset>18</bitOffset> 4219 <bitWidth>1</bitWidth> 4220 <access>write-only</access> 4221 </field> 4222 <field> 4223 <name>IGNRXFCS</name> 4224 <description>Ignore RX FCS. If 1, packets with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.</description> 4225 <bitOffset>19</bitOffset> 4226 <bitWidth>1</bitWidth> 4227 <access>write-only</access> 4228 </field> 4229 </fields> 4230 </register> 4231 <register> 4232 <name>STATUS</name> 4233 <description>Network Status Register.</description> 4234 <addressOffset>0x08</addressOffset> 4235 <access>read-only</access> 4236 <fields> 4237 <field> 4238 <name>LINK</name> 4239 <description>LINK pin status. Returns status of EMAC_LINK pin.</description> 4240 <bitOffset>0</bitOffset> 4241 <bitWidth>1</bitWidth> 4242 <access>read-only</access> 4243 </field> 4244 <field> 4245 <name>MDIO</name> 4246 <description>MDIO pin status. Returns status of the EMAC_MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit.</description> 4247 <bitOffset>1</bitOffset> 4248 <bitWidth>1</bitWidth> 4249 <access>read-only</access> 4250 </field> 4251 <field> 4252 <name>IDLE</name> 4253 <description>PHY management logic status.</description> 4254 <bitOffset>2</bitOffset> 4255 <bitWidth>1</bitWidth> 4256 <access>read-only</access> 4257 </field> 4258 </fields> 4259 </register> 4260 <register> 4261 <name>TX_ST</name> 4262 <description>Transmit Status Register.</description> 4263 <addressOffset>0x14</addressOffset> 4264 <fields> 4265 <field> 4266 <name>UBR</name> 4267 <description>Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Write 1 to clear this bit.</description> 4268 <bitOffset>0</bitOffset> 4269 <bitWidth>1</bitWidth> 4270 <access>read-write</access> 4271 </field> 4272 <field> 4273 <name>COLS</name> 4274 <description>Collision Occurred. Set when a collision occurs. Write 1 to clear this bit.</description> 4275 <bitOffset>1</bitOffset> 4276 <bitWidth>1</bitWidth> 4277 <access>read-write</access> 4278 </field> 4279 <field> 4280 <name>RTYLIM</name> 4281 <description>Retry Limit Exceeded. Set when the retry limit has been exceeded. Write 1 to clear this bit. </description> 4282 <bitOffset>2</bitOffset> 4283 <bitWidth>1</bitWidth> 4284 <access>read-write</access> 4285 </field> 4286 <field> 4287 <name>TXGO</name> 4288 <description>Transmit Go. If 1, transmit is active.</description> 4289 <bitOffset>3</bitOffset> 4290 <bitWidth>1</bitWidth> 4291 <access>read-write</access> 4292 </field> 4293 <field> 4294 <name>BEMF</name> 4295 <description>Buffers Exhausted Mid Frame. If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and EMAC_TXER asserted. Write 1 to clear this bit.</description> 4296 <bitOffset>4</bitOffset> 4297 <bitWidth>1</bitWidth> 4298 <access>read-write</access> 4299 </field> 4300 <field> 4301 <name>TXCMPL</name> 4302 <description>Transmit Complete. Set when a frame has been transmitted. Write 1 to clear this bit.</description> 4303 <bitOffset>5</bitOffset> 4304 <bitWidth>1</bitWidth> 4305 <access>read-write</access> 4306 </field> 4307 <field> 4308 <name>TXUR</name> 4309 <description>Transmit Underrun. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad. Write 1 to clear this bit.</description> 4310 <bitOffset>6</bitOffset> 4311 <bitWidth>1</bitWidth> 4312 <access>read-write</access> 4313 </field> 4314 </fields> 4315 </register> 4316 <register> 4317 <name>RXBUF_PTR</name> 4318 <description>Receive Buffer Queue Pointer Register.</description> 4319 <addressOffset>0x18</addressOffset> 4320 <fields> 4321 <field> 4322 <name>RXBUF</name> 4323 <description>Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.</description> 4324 <bitOffset>2</bitOffset> 4325 <bitWidth>30</bitWidth> 4326 <access>read-write</access> 4327 </field> 4328 </fields> 4329 </register> 4330 <register> 4331 <name>TXBUF_PTR</name> 4332 <description>Transmit Buffer Queue Pointer Register.</description> 4333 <addressOffset>0x1C</addressOffset> 4334 <fields> 4335 <field> 4336 <name>TXBUF</name> 4337 <description>Transmit buffer queue pointer. Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.</description> 4338 <bitOffset>2</bitOffset> 4339 <bitWidth>30</bitWidth> 4340 <access>read-write</access> 4341 </field> 4342 </fields> 4343 </register> 4344 <register> 4345 <name>RX_ST</name> 4346 <description>Receive Status Register.</description> 4347 <addressOffset>0x20</addressOffset> 4348 <fields> 4349 <field> 4350 <name>BNA</name> 4351 <description>Buffer Not Available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will reread the pointer each time a new frame starts until a valid pointer is found. This bit will be set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Write 1 to clear this bit.</description> 4352 <bitOffset>0</bitOffset> 4353 <bitWidth>1</bitWidth> 4354 <access>read-write</access> 4355 </field> 4356 <field> 4357 <name>FR</name> 4358 <description>Frame Received. One or more frames have been received and placed in memory. Write 1 to clear this bit.</description> 4359 <bitOffset>1</bitOffset> 4360 <bitWidth>1</bitWidth> 4361 <access>read-write</access> 4362 </field> 4363 <field> 4364 <name>RXOR</name> 4365 <description>Receive Overrun. The DMA block was unable to store the receive frame to memory. Either because the AHB bus was not granted in time or because a not OK hresp was returned. The buffer will be recovered if this happens. Write 1 to clear this bit.</description> 4366 <bitOffset>2</bitOffset> 4367 <bitWidth>1</bitWidth> 4368 <access>read-write</access> 4369 </field> 4370 </fields> 4371 </register> 4372 <register> 4373 <name>INT_ST</name> 4374 <description>Interrupt Status Register.</description> 4375 <addressOffset>0x24</addressOffset> 4376 <fields> 4377 <field> 4378 <name>MPS</name> 4379 <description>Management Packet Sent Interrupt Status. The PHY maintenance register has completed its operation. Cleared when read.</description> 4380 <bitOffset>0</bitOffset> 4381 <bitWidth>1</bitWidth> 4382 <access>read-write</access> 4383 </field> 4384 <field> 4385 <name>RXCMPL</name> 4386 <description>Receive Complete Interrupt Status. Set when a frame has been stored in memory. Cleared when read.</description> 4387 <bitOffset>1</bitOffset> 4388 <bitWidth>1</bitWidth> 4389 <access>read-write</access> 4390 </field> 4391 <field> 4392 <name>RXUBR</name> 4393 <description>RX Used Bit Read Interrupt Status. Set when a receive buffer descriptor is read with its used bit set. Cleared when read.</description> 4394 <bitOffset>2</bitOffset> 4395 <bitWidth>1</bitWidth> 4396 <access>read-write</access> 4397 </field> 4398 <field> 4399 <name>TXUBR</name> 4400 <description>TX Used Bit Read Interrupt Status. Set when a transmit buffer descriptor is read with its used bit set. Cleared when read</description> 4401 <bitOffset>3</bitOffset> 4402 <bitWidth>1</bitWidth> 4403 <access>read-write</access> 4404 </field> 4405 <field> 4406 <name>TXUR</name> 4407 <description>Ethernet Transmit Underrun Interrupt Status. Set when the MAC transmit FIFO was read while was empty. If this happens the transmitter forces bad CRC and forces EMAC_TXER high. Cleared when read.</description> 4408 <bitOffset>4</bitOffset> 4409 <bitWidth>1</bitWidth> 4410 <access>read-write</access> 4411 </field> 4412 <field> 4413 <name>RLE</name> 4414 <description>Retry Limit Exceeded Interrupt Status. Transmit error. Cleared when read.</description> 4415 <bitOffset>5</bitOffset> 4416 <bitWidth>1</bitWidth> 4417 <access>read-write</access> 4418 </field> 4419 <field> 4420 <name>TXERR</name> 4421 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Status. Transmit error. Cleared when read.</description> 4422 <bitOffset>6</bitOffset> 4423 <bitWidth>1</bitWidth> 4424 <access>read-write</access> 4425 </field> 4426 <field> 4427 <name>TXCMPL</name> 4428 <description>Transmit Complete Interrupt Status. Set when a frame has been transmitted. Cleared when read.</description> 4429 <bitOffset>7</bitOffset> 4430 <bitWidth>1</bitWidth> 4431 <access>read-write</access> 4432 </field> 4433 <field> 4434 <name>LC</name> 4435 <description>Link Change Interrupt Status. Set when the external link signal changes. Cleared when read.</description> 4436 <bitOffset>9</bitOffset> 4437 <bitWidth>1</bitWidth> 4438 <access>read-write</access> 4439 </field> 4440 <field> 4441 <name>RXOR</name> 4442 <description>Receive Overrun Interrupt Status. Set when the receive overrun status bit gets set. Cleared when read.</description> 4443 <bitOffset>10</bitOffset> 4444 <bitWidth>1</bitWidth> 4445 <access>read-write</access> 4446 </field> 4447 <field> 4448 <name>HRESPNO</name> 4449 <description>hresp not OK Interrupt Status. Set when the DMA block sees hresp not OK. Cleared when read.</description> 4450 <bitOffset>11</bitOffset> 4451 <bitWidth>1</bitWidth> 4452 <access>read-write</access> 4453 </field> 4454 <field> 4455 <name>PPR</name> 4456 <description>Pause Packet Received Interrupt Status. Indicates a valid pause packet has been received. Cleared when read.</description> 4457 <bitOffset>12</bitOffset> 4458 <bitWidth>1</bitWidth> 4459 <access>read-write</access> 4460 </field> 4461 <field> 4462 <name>PTZ</name> 4463 <description>Pause Time Zero Interrupt Status. Set when the MAC Pause Time register (MAC_PT) decrements to zero. Cleared when read.</description> 4464 <bitOffset>13</bitOffset> 4465 <bitWidth>1</bitWidth> 4466 <access>read-write</access> 4467 </field> 4468 </fields> 4469 </register> 4470 <register> 4471 <name>INT_EN</name> 4472 <description>Interrupt Enable Register.</description> 4473 <addressOffset>0x28</addressOffset> 4474 <access>write-only</access> 4475 <fields> 4476 <field> 4477 <name>MPS</name> 4478 <description>Management Packet Sent Interrupt Enable</description> 4479 <bitOffset>0</bitOffset> 4480 <bitWidth>1</bitWidth> 4481 <access>write-only</access> 4482 </field> 4483 <field> 4484 <name>RXCMPL</name> 4485 <description>Receive Complete Interrupt Enable</description> 4486 <bitOffset>1</bitOffset> 4487 <bitWidth>1</bitWidth> 4488 <access>write-only</access> 4489 </field> 4490 <field> 4491 <name>RXUBR</name> 4492 <description>RX Used Bit Read Interrupt Enable</description> 4493 <bitOffset>2</bitOffset> 4494 <bitWidth>1</bitWidth> 4495 <access>write-only</access> 4496 </field> 4497 <field> 4498 <name>TXUBR</name> 4499 <description>TX Used Bit Read Interrupt Enable</description> 4500 <bitOffset>3</bitOffset> 4501 <bitWidth>1</bitWidth> 4502 <access>write-only</access> 4503 </field> 4504 <field> 4505 <name>TXUR</name> 4506 <description>Ethernet Transmit Underrun Interrupt Enable</description> 4507 <bitOffset>4</bitOffset> 4508 <bitWidth>1</bitWidth> 4509 <access>write-only</access> 4510 </field> 4511 <field> 4512 <name>RLE</name> 4513 <description>Retry Limit Exceeded Interrupt Enable</description> 4514 <bitOffset>5</bitOffset> 4515 <bitWidth>1</bitWidth> 4516 <access>write-only</access> 4517 </field> 4518 <field> 4519 <name>TXERR</name> 4520 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Enable</description> 4521 <bitOffset>6</bitOffset> 4522 <bitWidth>1</bitWidth> 4523 <access>write-only</access> 4524 </field> 4525 <field> 4526 <name>TXCMPL</name> 4527 <description>Transmit Complete Interrupt Enable</description> 4528 <bitOffset>7</bitOffset> 4529 <bitWidth>1</bitWidth> 4530 <access>write-only</access> 4531 </field> 4532 <field> 4533 <name>LC</name> 4534 <description>Link Change Interrupt Enable</description> 4535 <bitOffset>9</bitOffset> 4536 <bitWidth>1</bitWidth> 4537 <access>write-only</access> 4538 </field> 4539 <field> 4540 <name>RXOR</name> 4541 <description>Receive Overrun Interrupt Enable</description> 4542 <bitOffset>10</bitOffset> 4543 <bitWidth>1</bitWidth> 4544 <access>write-only</access> 4545 </field> 4546 <field> 4547 <name>HRESPNO</name> 4548 <description>hresp not OK Interrupt Enable</description> 4549 <bitOffset>11</bitOffset> 4550 <bitWidth>1</bitWidth> 4551 <access>write-only</access> 4552 </field> 4553 <field> 4554 <name>PPR</name> 4555 <description>Pause Packet Received Interrupt Enable</description> 4556 <bitOffset>12</bitOffset> 4557 <bitWidth>1</bitWidth> 4558 <access>write-only</access> 4559 </field> 4560 <field> 4561 <name>PTZ</name> 4562 <description>Pause Time Zero Interrupt Enable</description> 4563 <bitOffset>13</bitOffset> 4564 <bitWidth>1</bitWidth> 4565 <access>write-only</access> 4566 </field> 4567 </fields> 4568 </register> 4569 <register> 4570 <name>INT_DIS</name> 4571 <description>Interrupt Disable Register.</description> 4572 <addressOffset>0x2C</addressOffset> 4573 <access>write-only</access> 4574 <fields> 4575 <field> 4576 <name>MPS</name> 4577 <description>Management Packet Sent Interrupt Disable</description> 4578 <bitOffset>0</bitOffset> 4579 <bitWidth>1</bitWidth> 4580 <access>write-only</access> 4581 </field> 4582 <field> 4583 <name>RXCMPL</name> 4584 <description>Receive Complete Interrupt Disable</description> 4585 <bitOffset>1</bitOffset> 4586 <bitWidth>1</bitWidth> 4587 <access>write-only</access> 4588 </field> 4589 <field> 4590 <name>RXUBR</name> 4591 <description>RX Used Bit Read Interrupt Disable</description> 4592 <bitOffset>2</bitOffset> 4593 <bitWidth>1</bitWidth> 4594 <access>write-only</access> 4595 </field> 4596 <field> 4597 <name>TXUBR</name> 4598 <description>TX Used Bit Read Interrupt Disable</description> 4599 <bitOffset>3</bitOffset> 4600 <bitWidth>1</bitWidth> 4601 <access>write-only</access> 4602 </field> 4603 <field> 4604 <name>TXUR</name> 4605 <description>Ethernet Transmit Underrun Interrupt Disable</description> 4606 <bitOffset>4</bitOffset> 4607 <bitWidth>1</bitWidth> 4608 <access>write-only</access> 4609 </field> 4610 <field> 4611 <name>RLE</name> 4612 <description>Retry Limit Exceeded Interrupt Disable</description> 4613 <bitOffset>5</bitOffset> 4614 <bitWidth>1</bitWidth> 4615 <access>write-only</access> 4616 </field> 4617 <field> 4618 <name>TXERR</name> 4619 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Disable</description> 4620 <bitOffset>6</bitOffset> 4621 <bitWidth>1</bitWidth> 4622 <access>write-only</access> 4623 </field> 4624 <field> 4625 <name>TXCMPL</name> 4626 <description>Transmit Complete Interrupt Disable</description> 4627 <bitOffset>7</bitOffset> 4628 <bitWidth>1</bitWidth> 4629 <access>write-only</access> 4630 </field> 4631 <field> 4632 <name>LC</name> 4633 <description>Link Change Interrupt Disable</description> 4634 <bitOffset>9</bitOffset> 4635 <bitWidth>1</bitWidth> 4636 <access>write-only</access> 4637 </field> 4638 <field> 4639 <name>RXOR</name> 4640 <description>Receive Overrun Interrupt Disable</description> 4641 <bitOffset>10</bitOffset> 4642 <bitWidth>1</bitWidth> 4643 <access>write-only</access> 4644 </field> 4645 <field> 4646 <name>HRESPNO</name> 4647 <description>hresp not OK Interrupt Disable</description> 4648 <bitOffset>11</bitOffset> 4649 <bitWidth>1</bitWidth> 4650 <access>write-only</access> 4651 </field> 4652 <field> 4653 <name>PPR</name> 4654 <description>Pause Packet Received Interrupt Disable</description> 4655 <bitOffset>12</bitOffset> 4656 <bitWidth>1</bitWidth> 4657 <access>write-only</access> 4658 </field> 4659 <field> 4660 <name>PTZ</name> 4661 <description>Pause Time Zero Interrupt Disable</description> 4662 <bitOffset>13</bitOffset> 4663 <bitWidth>1</bitWidth> 4664 <access>write-only</access> 4665 </field> 4666 </fields> 4667 </register> 4668 <register> 4669 <name>INT_MASK</name> 4670 <description>Interrupt Mask Register.</description> 4671 <addressOffset>0x30</addressOffset> 4672 <access>read-only</access> 4673 <fields> 4674 <field> 4675 <name>MPS</name> 4676 <description>Management Packet Sent Interrupt Mask</description> 4677 <bitOffset>0</bitOffset> 4678 <bitWidth>1</bitWidth> 4679 <access>read-only</access> 4680 </field> 4681 <field> 4682 <name>RXCMPL</name> 4683 <description>Receive Complete Interrupt Mask</description> 4684 <bitOffset>1</bitOffset> 4685 <bitWidth>1</bitWidth> 4686 <access>read-only</access> 4687 </field> 4688 <field> 4689 <name>RXUBR</name> 4690 <description>RX Used Bit Read Interrupt Mask</description> 4691 <bitOffset>2</bitOffset> 4692 <bitWidth>1</bitWidth> 4693 <access>read-only</access> 4694 </field> 4695 <field> 4696 <name>TXUBR</name> 4697 <description>TX Used Bit Read Interrupt Mask</description> 4698 <bitOffset>3</bitOffset> 4699 <bitWidth>1</bitWidth> 4700 <access>read-only</access> 4701 </field> 4702 <field> 4703 <name>TXUR</name> 4704 <description>Ethernet Transmit Underrun Interrupt Mask</description> 4705 <bitOffset>4</bitOffset> 4706 <bitWidth>1</bitWidth> 4707 <access>read-only</access> 4708 </field> 4709 <field> 4710 <name>RLE</name> 4711 <description>Retry Limit Exceeded Interrupt Mask</description> 4712 <bitOffset>5</bitOffset> 4713 <bitWidth>1</bitWidth> 4714 <access>read-only</access> 4715 </field> 4716 <field> 4717 <name>TXERR</name> 4718 <description>Transmit Buffers Exhausted In Mid-frame Interrupt Mask</description> 4719 <bitOffset>6</bitOffset> 4720 <bitWidth>1</bitWidth> 4721 <access>read-only</access> 4722 </field> 4723 <field> 4724 <name>TXCMPL</name> 4725 <description>Transmit Complete Interrupt Mask</description> 4726 <bitOffset>7</bitOffset> 4727 <bitWidth>1</bitWidth> 4728 <access>read-only</access> 4729 </field> 4730 <field> 4731 <name>LC</name> 4732 <description>Link Change Interrupt Mask</description> 4733 <bitOffset>9</bitOffset> 4734 <bitWidth>1</bitWidth> 4735 <access>read-only</access> 4736 </field> 4737 <field> 4738 <name>RXOR</name> 4739 <description>Receive Overrun Interrupt Mask</description> 4740 <bitOffset>10</bitOffset> 4741 <bitWidth>1</bitWidth> 4742 <access>read-only</access> 4743 </field> 4744 <field> 4745 <name>HRESPNO</name> 4746 <description>hresp not OK Interrupt Mask</description> 4747 <bitOffset>11</bitOffset> 4748 <bitWidth>1</bitWidth> 4749 <access>read-only</access> 4750 </field> 4751 <field> 4752 <name>PPR</name> 4753 <description>Pause Packet Received Interrupt Mask</description> 4754 <bitOffset>12</bitOffset> 4755 <bitWidth>1</bitWidth> 4756 <access>read-only</access> 4757 </field> 4758 <field> 4759 <name>PTZ</name> 4760 <description>Pause Time Zero Interrupt Mask</description> 4761 <bitOffset>13</bitOffset> 4762 <bitWidth>1</bitWidth> 4763 <access>read-only</access> 4764 </field> 4765 </fields> 4766 </register> 4767 <register> 4768 <name>PHY_MT</name> 4769 <description>PHY Maintenance Register.</description> 4770 <addressOffset>0x34</addressOffset> 4771 <fields> 4772 <field> 4773 <name>DATA</name> 4774 <description>PHY Data. For a write operation this field is the data to be written to the PHY. </description> 4775 <bitOffset>0</bitOffset> 4776 <bitWidth>16</bitWidth> 4777 <access>read-write</access> 4778 </field> 4779 <field> 4780 <name>REGADDR</name> 4781 <description>Register Address. Specifies the register in the PHY to access.</description> 4782 <bitOffset>18</bitOffset> 4783 <bitWidth>5</bitWidth> 4784 <access>read-write</access> 4785 </field> 4786 <field> 4787 <name>PHYADDR</name> 4788 <description>PHY Address. Specifies the PHY to access.</description> 4789 <bitOffset>23</bitOffset> 4790 <bitWidth>5</bitWidth> 4791 <access>read-write</access> 4792 </field> 4793 <field> 4794 <name>OP</name> 4795 <description>Operation</description> 4796 <bitOffset>28</bitOffset> 4797 <bitWidth>2</bitWidth> 4798 <access>read-write</access> 4799 <enumeratedValues> 4800 <enumeratedValue> 4801 <name>write</name> 4802 <description>Write</description> 4803 <value>1</value> 4804 </enumeratedValue> 4805 <enumeratedValue> 4806 <name>read</name> 4807 <description>Read</description> 4808 <value>2</value> 4809 </enumeratedValue> 4810 </enumeratedValues> 4811 </field> 4812 <field> 4813 <name>SOP</name> 4814 <description>TBD </description> 4815 <bitOffset>30</bitOffset> 4816 <bitWidth>2</bitWidth> 4817 <access>read-write</access> 4818 </field> 4819 </fields> 4820 </register> 4821 <register> 4822 <name>PT</name> 4823 <description>Pause Time Register.</description> 4824 <addressOffset>0x38</addressOffset> 4825 <access>read-only</access> 4826 <fields> 4827 <field> 4828 <name>TIME</name> 4829 <description>Pause Time. Stores the current value of the pause time register, which is decremented every 512 bit times.</description> 4830 <bitOffset>0</bitOffset> 4831 <bitWidth>16</bitWidth> 4832 <access>read-only</access> 4833 </field> 4834 </fields> 4835 </register> 4836 <register> 4837 <name>PFR</name> 4838 <description>Pause Frame Received OK.</description> 4839 <addressOffset>0x3C</addressOffset> 4840 <fields> 4841 <field> 4842 <name>PFR</name> 4843 <description>Pause Frames Received OK. A 16-bit register counting the number of good pause frames received. </description> 4844 <bitOffset>0</bitOffset> 4845 <bitWidth>16</bitWidth> 4846 <access>read-write</access> 4847 </field> 4848 </fields> 4849 </register> 4850 <register> 4851 <name>FTOK</name> 4852 <description>Frames Transmitted OK.</description> 4853 <addressOffset>0x40</addressOffset> 4854 <fields> 4855 <field> 4856 <name>FTOK</name> 4857 <description>Frames Transmitted OK. A 32-bit register counting the number of frames successfully transmitted, i.e. no underrun and not too many retries.</description> 4858 <bitOffset>0</bitOffset> 4859 <bitWidth>32</bitWidth> 4860 <access>read-write</access> 4861 </field> 4862 </fields> 4863 </register> 4864 <register> 4865 <name>SCF</name> 4866 <description>Single Collision Frames.</description> 4867 <addressOffset>0x44</addressOffset> 4868 <fields> 4869 <field> 4870 <name>SCF</name> 4871 <description>Single Collision Frames. A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e. no underrun.</description> 4872 <bitOffset>0</bitOffset> 4873 <bitWidth>16</bitWidth> 4874 <access>read-write</access> 4875 </field> 4876 </fields> 4877 </register> 4878 <register> 4879 <name>MCF</name> 4880 <description>Multiple Collision Frames.</description> 4881 <addressOffset>0x48</addressOffset> 4882 <fields> 4883 <field> 4884 <name>MCF</name> 4885 <description>Multiple Collision Frames. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e. no underrun and not too many retries.</description> 4886 <bitOffset>0</bitOffset> 4887 <bitWidth>16</bitWidth> 4888 <access>read-write</access> 4889 </field> 4890 </fields> 4891 </register> 4892 <register> 4893 <name>FROK</name> 4894 <description>Fames Received OK.</description> 4895 <addressOffset>0x4C</addressOffset> 4896 <fields> 4897 <field> 4898 <name>FROK</name> 4899 <description>Frames Received OK. A 24-bit register counting the number of good packets received</description> 4900 <bitOffset>0</bitOffset> 4901 <bitWidth>24</bitWidth> 4902 <access>read-write</access> 4903 </field> 4904 </fields> 4905 </register> 4906 <register> 4907 <name>FCS_ERR</name> 4908 <description>Frame Check Sequence Errors.</description> 4909 <addressOffset>0x50</addressOffset> 4910 <fields> 4911 <field> 4912 <name>FCSERR</name> 4913 <description>Frame Check Sequence Errors.</description> 4914 <bitOffset>0</bitOffset> 4915 <bitWidth>8</bitWidth> 4916 <access>read-write</access> 4917 </field> 4918 </fields> 4919 </register> 4920 <register> 4921 <name>ALGN_ERR</name> 4922 <description>Alignment Errors.</description> 4923 <addressOffset>0x54</addressOffset> 4924 <fields> 4925 <field> 4926 <name>ALGNERR</name> 4927 <description>Alignment Errors. </description> 4928 <bitOffset>0</bitOffset> 4929 <bitWidth>8</bitWidth> 4930 <access>read-write</access> 4931 </field> 4932 </fields> 4933 </register> 4934 <register> 4935 <name>DFTXF</name> 4936 <description>Deferred Transmission Frames.</description> 4937 <addressOffset>0x58</addressOffset> 4938 <fields> 4939 <field> 4940 <name>DFTXF</name> 4941 <description>Deferred Transmission Frames. A 16-bit register counting the number of packets experiencing deferral due to carrier sense being active on their first attempt at transmission</description> 4942 <bitOffset>0</bitOffset> 4943 <bitWidth>16</bitWidth> 4944 <access>read-write</access> 4945 </field> 4946 </fields> 4947 </register> 4948 <register> 4949 <name>LC</name> 4950 <description>Late Collisions.</description> 4951 <addressOffset>0x5C</addressOffset> 4952 <fields> 4953 <field> 4954 <name>LC</name> 4955 <description>Late Collisions. An 8-bit register counting the number of packets that experience a collision after the slot time (512 bits) has expired.</description> 4956 <bitOffset>0</bitOffset> 4957 <bitWidth>8</bitWidth> 4958 <access>read-write</access> 4959 </field> 4960 </fields> 4961 </register> 4962 <register> 4963 <name>EC</name> 4964 <description>Excessive Collisions.</description> 4965 <addressOffset>0x60</addressOffset> 4966 <fields> 4967 <field> 4968 <name>EC</name> 4969 <description>Excessive Collisions. An 8-bit register counting the number of packets that failed to be transmitted because they experienced 16 collisions.</description> 4970 <bitOffset>0</bitOffset> 4971 <bitWidth>8</bitWidth> 4972 <access>read-write</access> 4973 </field> 4974 </fields> 4975 </register> 4976 <register> 4977 <name>TUR_ERR</name> 4978 <description>Transmit Underrun Errors.</description> 4979 <addressOffset>0x64</addressOffset> 4980 <fields> 4981 <field> 4982 <name>TURERR</name> 4983 <description>Transmit Underrun Error. An 8-bit register counting the number of packets not transmitted due to a transmit FIFO underrun.</description> 4984 <bitOffset>0</bitOffset> 4985 <bitWidth>8</bitWidth> 4986 <access>read-write</access> 4987 </field> 4988 </fields> 4989 </register> 4990 <register> 4991 <name>CS_ERR</name> 4992 <description>Carrier Sense Errors.</description> 4993 <addressOffset>0x68</addressOffset> 4994 <fields> 4995 <field> 4996 <name>CSERR</name> 4997 <description>An 8-bit register counting the number of packets transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit packet without collision (no underrun).</description> 4998 <bitOffset>0</bitOffset> 4999 <bitWidth>8</bitWidth> 5000 <access>read-write</access> 5001 </field> 5002 </fields> 5003 </register> 5004 <register> 5005 <name>RR_ERR</name> 5006 <description>Receive Resource Errors.</description> 5007 <addressOffset>0x6C</addressOffset> 5008 <fields> 5009 <field> 5010 <name>RRERR</name> 5011 <description>Receive Resource Errors. A 16 bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.</description> 5012 <bitOffset>0</bitOffset> 5013 <bitWidth>16</bitWidth> 5014 <access>read-write</access> 5015 </field> 5016 </fields> 5017 </register> 5018 <register> 5019 <name>ROR_ERR</name> 5020 <description>Receive Overrun Errors.</description> 5021 <addressOffset>0x70</addressOffset> 5022 <fields> 5023 <field> 5024 <name>RORERR</name> 5025 <description>Receive Overruns. An 8 bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.</description> 5026 <bitOffset>0</bitOffset> 5027 <bitWidth>8</bitWidth> 5028 <access>read-write</access> 5029 </field> 5030 </fields> 5031 </register> 5032 <register> 5033 <name>RS_ERR</name> 5034 <description>Receive Symbol Errors.</description> 5035 <addressOffset>0x74</addressOffset> 5036 <fields> 5037 <field> 5038 <name>RSERR</name> 5039 <description>Receive Symbol Errors. An 8-bit register counting the number of packets that had EMAC_RXER asserted during reception.</description> 5040 <bitOffset>0</bitOffset> 5041 <bitWidth>8</bitWidth> 5042 <access>read-write</access> 5043 </field> 5044 </fields> 5045 </register> 5046 <register> 5047 <name>EL_ERR</name> 5048 <description>Excessive Length Errors.</description> 5049 <addressOffset>0x78</addressOffset> 5050 <fields> 5051 <field> 5052 <name>ELERR</name> 5053 <description>Excessive Length Errors. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register;</description> 5054 <bitOffset>0</bitOffset> 5055 <bitWidth>8</bitWidth> 5056 <access>read-write</access> 5057 </field> 5058 </fields> 5059 </register> 5060 <register> 5061 <name>RJ</name> 5062 <description>Receive Jabber.</description> 5063 <addressOffset>0x7C</addressOffset> 5064 <fields> 5065 <field> 5066 <name>RJERR</name> 5067 <description>Receive Jabbers. An 8-bit register counting the number of packets received exceeding 1518 bytes in length (1536 if RXFR is set in the MAC_CFG register; </description> 5068 <bitOffset>0</bitOffset> 5069 <bitWidth>8</bitWidth> 5070 <access>read-write</access> 5071 </field> 5072 </fields> 5073 </register> 5074 <register> 5075 <name>USF</name> 5076 <description>Undersize Frames.</description> 5077 <addressOffset>0x80</addressOffset> 5078 <fields> 5079 <field> 5080 <name>USF</name> 5081 <description>Undersize Frames. An 8-bit register counting the number of packets received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.</description> 5082 <bitOffset>0</bitOffset> 5083 <bitWidth>8</bitWidth> 5084 <access>read-write</access> 5085 </field> 5086 </fields> 5087 </register> 5088 <register> 5089 <name>SQE_ERR</name> 5090 <description>SQE Test Errors.</description> 5091 <addressOffset>0x84</addressOffset> 5092 <fields> 5093 <field> 5094 <name>SQEERR</name> 5095 <description>SQE Test Errors. An 8-bit register counting the number of packets where collision was not asserted within 96 bit times (an interframe gap) of EMAC_TXEN being deasserted in half duplex mode.</description> 5096 <bitOffset>0</bitOffset> 5097 <bitWidth>8</bitWidth> 5098 <access>read-write</access> 5099 </field> 5100 </fields> 5101 </register> 5102 <register> 5103 <name>RLFM</name> 5104 <description>Received Length Field Mismatch.</description> 5105 <addressOffset>0x88</addressOffset> 5106 <fields> 5107 <field> 5108 <name>RLFM</name> 5109 <description>Receive length field mismatch </description> 5110 <bitOffset>0</bitOffset> 5111 <bitWidth>8</bitWidth> 5112 <access>read-write</access> 5113 </field> 5114 </fields> 5115 </register> 5116 <register> 5117 <name>TPF</name> 5118 <description>Transmitted Pause Frames.</description> 5119 <addressOffset>0x8C</addressOffset> 5120 <fields> 5121 <field> 5122 <name>TPF</name> 5123 <description>Transmitted Pause Frames. A 16-bit register counting the number of pause packets transmitted.</description> 5124 <bitOffset>0</bitOffset> 5125 <bitWidth>16</bitWidth> 5126 <access>read-write</access> 5127 </field> 5128 </fields> 5129 </register> 5130 <register> 5131 <name>HASHL</name> 5132 <description>Hash Register Bottom [31:0].</description> 5133 <addressOffset>0x90</addressOffset> 5134 <fields> 5135 <field> 5136 <name>HASH</name> 5137 <description>Bits 31:0 of the hash address register. See Hash Addressing</description> 5138 <bitOffset>0</bitOffset> 5139 <bitWidth>32</bitWidth> 5140 <access>read-write</access> 5141 </field> 5142 </fields> 5143 </register> 5144 <register> 5145 <name>HASHH</name> 5146 <description>Hash Register top [63:32].</description> 5147 <addressOffset>0x94</addressOffset> 5148 <fields> 5149 <field> 5150 <name>HASH</name> 5151 <description>Bits 63:32 of the hash address register. See Hash Addressing</description> 5152 <bitOffset>0</bitOffset> 5153 <bitWidth>32</bitWidth> 5154 <access>read-write</access> 5155 </field> 5156 </fields> 5157 </register> 5158 <register> 5159 <name>SA1L</name> 5160 <description>Specific Address 1 Bottom.</description> 5161 <addressOffset>0x98</addressOffset> 5162 <fields> 5163 <field> 5164 <name>ADDR</name> 5165 <description>MAC Specific Address 1 [31:0]. Least significant bits of the MAC specific address 1, i.e. bits 31:0. This field is used for transmission of pause packets</description> 5166 <bitOffset>0</bitOffset> 5167 <bitWidth>32</bitWidth> 5168 <access>read-write</access> 5169 </field> 5170 </fields> 5171 </register> 5172 <register> 5173 <name>SA1H</name> 5174 <description>Specific Address 1 Top.</description> 5175 <addressOffset>0x9C</addressOffset> 5176 <fields> 5177 <field> 5178 <name>ADDR</name> 5179 <description>MAC Specific Address 1 [47:32]. Most significant bits of the MAC specific address 1, i.e. bits 47:32.</description> 5180 <bitOffset>0</bitOffset> 5181 <bitWidth>16</bitWidth> 5182 <access>read-write</access> 5183 </field> 5184 </fields> 5185 </register> 5186 <register> 5187 <name>SA2L</name> 5188 <description>Specific Address 2 Bottom.</description> 5189 <addressOffset>0xA0</addressOffset> 5190 <fields> 5191 <field> 5192 <name>ADDR</name> 5193 <description>MAC Specific Address 2 [31:0]. Least significant bits of the MAC specific address 2, i.e. bits 31:0. This field is used for transmission of pause packets</description> 5194 <bitOffset>0</bitOffset> 5195 <bitWidth>32</bitWidth> 5196 <access>read-write</access> 5197 </field> 5198 </fields> 5199 </register> 5200 <register> 5201 <name>SA2H</name> 5202 <description>Specific Address 2 Top.</description> 5203 <addressOffset>0xA4</addressOffset> 5204 <fields> 5205 <field> 5206 <name>ADDR</name> 5207 <description>MAC Specific Address 2 [47:32]. Most significant bits of the MAC specific address 2, i.e. bits 47:32.</description> 5208 <bitOffset>0</bitOffset> 5209 <bitWidth>16</bitWidth> 5210 <access>read-write</access> 5211 </field> 5212 </fields> 5213 </register> 5214 <register> 5215 <name>SA3L</name> 5216 <description>Specific Address 3 Bottom.</description> 5217 <addressOffset>0xA8</addressOffset> 5218 <fields> 5219 <field> 5220 <name>ADDR</name> 5221 <description>MAC Specific Address 3 [31:0]. Least significant bits of the MAC specific address 3, i.e. bits 31:0. This field is used for transmission of pause packets</description> 5222 <bitOffset>0</bitOffset> 5223 <bitWidth>32</bitWidth> 5224 <access>read-write</access> 5225 </field> 5226 </fields> 5227 </register> 5228 <register> 5229 <name>SA3H</name> 5230 <description>Specific Address 3 Top.</description> 5231 <addressOffset>0xAC</addressOffset> 5232 <fields> 5233 <field> 5234 <name>ADDR</name> 5235 <description>MAC Specific Address 3 [47:32]. Most significant bits of the MAC specific address 3, i.e. bits 47:32.</description> 5236 <bitOffset>0</bitOffset> 5237 <bitWidth>16</bitWidth> 5238 <access>read-write</access> 5239 </field> 5240 </fields> 5241 </register> 5242 <register> 5243 <name>SA4L</name> 5244 <description>Specific Address 4 Bottom.</description> 5245 <addressOffset>0xB0</addressOffset> 5246 <fields> 5247 <field> 5248 <name>ADDR</name> 5249 <description>MAC Specific Address 4 [31:0]. Least significant bits of the MAC specific address 4, i.e. bits 31:0. This field is used for transmission of pause packets</description> 5250 <bitOffset>0</bitOffset> 5251 <bitWidth>32</bitWidth> 5252 <access>read-write</access> 5253 </field> 5254 </fields> 5255 </register> 5256 <register> 5257 <name>SA4H</name> 5258 <description>Specific Address 4 Top.</description> 5259 <addressOffset>0xB4</addressOffset> 5260 <fields> 5261 <field> 5262 <name>ADDR</name> 5263 <description>MAC Specific Address 4 [47:32]. Most significant bits of the MAC specific address 4, i.e. bits 47:32.</description> 5264 <bitOffset>0</bitOffset> 5265 <bitWidth>16</bitWidth> 5266 <access>read-write</access> 5267 </field> 5268 </fields> 5269 </register> 5270 <register> 5271 <name>TID_CK</name> 5272 <description>Type ID Checking.</description> 5273 <addressOffset>0xB8</addressOffset> 5274 <fields> 5275 <field> 5276 <name>TID</name> 5277 <description>Type ID Checking. For use in comparisons with received frames TypeID/Length field.</description> 5278 <bitOffset>0</bitOffset> 5279 <bitWidth>16</bitWidth> 5280 <access>read-write</access> 5281 </field> 5282 </fields> 5283 </register> 5284 <register> 5285 <name>TPQ</name> 5286 <description>Transmit Pause Quantum.</description> 5287 <addressOffset>0xBC</addressOffset> 5288 <fields> 5289 <field> 5290 <name>TPQ</name> 5291 <description>Transmit Pause Quantum. Used in hardware generation of transmitted pause packets as value for pause quantum</description> 5292 <bitOffset>0</bitOffset> 5293 <bitWidth>16</bitWidth> 5294 <access>read-write</access> 5295 </field> 5296 </fields> 5297 </register> 5298 <register> 5299 <name>REV</name> 5300 <description>Revision register.</description> 5301 <addressOffset>0xFC</addressOffset> 5302 <access>read-only</access> 5303 <fields> 5304 <field> 5305 <name>REV</name> 5306 <description>Revision Reference. Fixed two byte value specific to revision of design.</description> 5307 <bitOffset>0</bitOffset> 5308 <bitWidth>16</bitWidth> 5309 <access>read-only</access> 5310 </field> 5311 <field> 5312 <name>PART</name> 5313 <description>Part Reference. For Ethernet MAC design, this is fixed at 0x01.</description> 5314 <bitOffset>16</bitOffset> 5315 <bitWidth>16</bitWidth> 5316 <access>read-only</access> 5317 </field> 5318 </fields> 5319 </register> 5320 </registers> 5321 </peripheral> 5322<!--EMAC 10/100 Ethernet MAC.--> 5323 <peripheral> 5324 <name>FCR</name> 5325 <description>Function Control Register.</description> 5326 <baseAddress>0x40000800</baseAddress> 5327 <addressBlock> 5328 <offset>0x00</offset> 5329 <size>0x400</size> 5330 <usage>registers</usage> 5331 </addressBlock> 5332 <registers> 5333 <register> 5334 <name>FCTRL0</name> 5335 <description>Register 0.</description> 5336 <addressOffset>0x00</addressOffset> 5337 <access>read-write</access> 5338 <fields> 5339 <field> 5340 <name>USB_EXTCLK_SEL</name> 5341 <description>USB External Core Clock Select.</description> 5342 <bitOffset>16</bitOffset> 5343 <bitWidth>1</bitWidth> 5344 <enumeratedValues> 5345 <enumeratedValue> 5346 <name>sys</name> 5347 <description>Generated clock from system clock.</description> 5348 <value>0</value> 5349 </enumeratedValue> 5350 <enumeratedValue> 5351 <name>dig</name> 5352 <description>Digital clock from a GPIO.</description> 5353 <value>1</value> 5354 </enumeratedValue> 5355 </enumeratedValues> 5356 </field> 5357 <field> 5358 <name>I2C0_SDA_FILTER_EN</name> 5359 <description>I2C0 SDA Glitch Filter Enable.</description> 5360 <bitOffset>20</bitOffset> 5361 <bitWidth>1</bitWidth> 5362 <enumeratedValues> 5363 <enumeratedValue> 5364 <name>dis</name> 5365 <description>Filter disabled.</description> 5366 <value>0</value> 5367 </enumeratedValue> 5368 <enumeratedValue> 5369 <name>en</name> 5370 <description>Filter enabled.</description> 5371 <value>1</value> 5372 </enumeratedValue> 5373 </enumeratedValues> 5374 </field> 5375 <field> 5376 <name>I2C0_SCL_FILTER_EN</name> 5377 <description>I2C0 SCL Glitch Filter Enable.</description> 5378 <bitOffset>21</bitOffset> 5379 <bitWidth>1</bitWidth> 5380 <enumeratedValues> 5381 <enumeratedValue> 5382 <name>dis</name> 5383 <description>Filter disabled.</description> 5384 <value>0</value> 5385 </enumeratedValue> 5386 <enumeratedValue> 5387 <name>en</name> 5388 <description>Filter enabled.</description> 5389 <value>1</value> 5390 </enumeratedValue> 5391 </enumeratedValues> 5392 </field> 5393 <field> 5394 <name>I2C1_SDA_FILTER_EN</name> 5395 <description>I2C1 SDA Glitch Filter Enable.</description> 5396 <bitOffset>22</bitOffset> 5397 <bitWidth>1</bitWidth> 5398 <enumeratedValues> 5399 <enumeratedValue> 5400 <name>dis</name> 5401 <description>Filter disabled.</description> 5402 <value>0</value> 5403 </enumeratedValue> 5404 <enumeratedValue> 5405 <name>en</name> 5406 <description>Filter enabled.</description> 5407 <value>1</value> 5408 </enumeratedValue> 5409 </enumeratedValues> 5410 </field> 5411 <field> 5412 <name>I2C1_SCL_FILTER_EN</name> 5413 <description>I2C1 SCL Glitch Filter Enable.</description> 5414 <bitOffset>23</bitOffset> 5415 <bitWidth>1</bitWidth> 5416 <enumeratedValues> 5417 <enumeratedValue> 5418 <name>dis</name> 5419 <description>Filter disabled.</description> 5420 <value>0</value> 5421 </enumeratedValue> 5422 <enumeratedValue> 5423 <name>en</name> 5424 <description>Filter enabled.</description> 5425 <value>1</value> 5426 </enumeratedValue> 5427 </enumeratedValues> 5428 </field> 5429 <field> 5430 <name>I2C2AF2_SDA_FILTER_EN</name> 5431 <description>I2C2 AF2 SDA Glitch Filter Enable.</description> 5432 <bitOffset>24</bitOffset> 5433 <bitWidth>1</bitWidth> 5434 <enumeratedValues> 5435 <enumeratedValue> 5436 <name>dis</name> 5437 <description>Filter disabled.</description> 5438 <value>0</value> 5439 </enumeratedValue> 5440 <enumeratedValue> 5441 <name>en</name> 5442 <description>Filter enabled.</description> 5443 <value>1</value> 5444 </enumeratedValue> 5445 </enumeratedValues> 5446 </field> 5447 <field> 5448 <name>I2C2AF2_SCL_FILTER_EN</name> 5449 <description>I2C2 AF2 SCL Glitch Filter Enable.</description> 5450 <bitOffset>25</bitOffset> 5451 <bitWidth>1</bitWidth> 5452 <enumeratedValues> 5453 <enumeratedValue> 5454 <name>dis</name> 5455 <description>Filter disabled.</description> 5456 <value>0</value> 5457 </enumeratedValue> 5458 <enumeratedValue> 5459 <name>en</name> 5460 <description>Filter enabled.</description> 5461 <value>1</value> 5462 </enumeratedValue> 5463 </enumeratedValues> 5464 </field> 5465 <field> 5466 <name>I2C2AF3_SDA_FILTER_EN</name> 5467 <description>I2C2 AF3 SDA Glitch Filter Enable.</description> 5468 <bitOffset>26</bitOffset> 5469 <bitWidth>1</bitWidth> 5470 <enumeratedValues> 5471 <enumeratedValue> 5472 <name>dis</name> 5473 <description>Filter disabled.</description> 5474 <value>0</value> 5475 </enumeratedValue> 5476 <enumeratedValue> 5477 <name>en</name> 5478 <description>Filter enabled.</description> 5479 <value>1</value> 5480 </enumeratedValue> 5481 </enumeratedValues> 5482 </field> 5483 <field> 5484 <name>I2C2AF3_SCL_FILTER_EN</name> 5485 <description>I2C2 AF3 SCL Glitch Filter Enable.</description> 5486 <bitOffset>27</bitOffset> 5487 <bitWidth>1</bitWidth> 5488 <enumeratedValues> 5489 <enumeratedValue> 5490 <name>dis</name> 5491 <description>Filter disabled.</description> 5492 <value>0</value> 5493 </enumeratedValue> 5494 <enumeratedValue> 5495 <name>en</name> 5496 <description>Filter enabled.</description> 5497 <value>1</value> 5498 </enumeratedValue> 5499 </enumeratedValues> 5500 </field> 5501 <field> 5502 <name>I2C2AF4_SDA_FILTER_EN</name> 5503 <description>I2C2 AF4 SDA Glitch Filter Enable</description> 5504 <bitOffset>28</bitOffset> 5505 <bitWidth>1</bitWidth> 5506 <enumeratedValues> 5507 <enumeratedValue> 5508 <name>dis</name> 5509 <description>Filter disabled.</description> 5510 <value>0</value> 5511 </enumeratedValue> 5512 <enumeratedValue> 5513 <name>en</name> 5514 <description>Filter enabled.</description> 5515 <value>1</value> 5516 </enumeratedValue> 5517 </enumeratedValues> 5518 </field> 5519 <field> 5520 <name>I2C2AF4_SCL_FILTER_EN</name> 5521 <description>I2C2 AF4 SCL Glitch Filter Enable</description> 5522 <bitOffset>29</bitOffset> 5523 <bitWidth>1</bitWidth> 5524 <enumeratedValues> 5525 <enumeratedValue> 5526 <name>dis</name> 5527 <description>Filter disabled.</description> 5528 <value>0</value> 5529 </enumeratedValue> 5530 <enumeratedValue> 5531 <name>en</name> 5532 <description>Filter enabled.</description> 5533 <value>1</value> 5534 </enumeratedValue> 5535 </enumeratedValues> 5536 </field> 5537 </fields> 5538 </register> 5539 <register> 5540 <name>AUTOCAL0</name> 5541 <description>Register 1.</description> 5542 <addressOffset>0x04</addressOffset> 5543 <access>read-write</access> 5544 <fields> 5545 <field> 5546 <name>SEL</name> 5547 <description>Auto-calibration Enable.</description> 5548 <bitOffset>0</bitOffset> 5549 <bitWidth>1</bitWidth> 5550 <enumeratedValues> 5551 <enumeratedValue> 5552 <name>dis</name> 5553 <description>Disabled.</description> 5554 <value>0</value> 5555 </enumeratedValue> 5556 <enumeratedValue> 5557 <name>en</name> 5558 <description>Enabled.</description> 5559 <value>1</value> 5560 </enumeratedValue> 5561 </enumeratedValues> 5562 </field> 5563 <field> 5564 <name>EN</name> 5565 <description>Autocalibration Run.</description> 5566 <bitOffset>1</bitOffset> 5567 <bitWidth>1</bitWidth> 5568 <enumeratedValues> 5569 <enumeratedValue> 5570 <name>not</name> 5571 <description>Not Running.</description> 5572 <value>0</value> 5573 </enumeratedValue> 5574 <enumeratedValue> 5575 <name>run</name> 5576 <description>Running.</description> 5577 <value>1</value> 5578 </enumeratedValue> 5579 </enumeratedValues> 5580 </field> 5581 <field> 5582 <name>LOAD</name> 5583 <description>Load Trim.</description> 5584 <bitOffset>2</bitOffset> 5585 <bitWidth>1</bitWidth> 5586 </field> 5587 <field> 5588 <name>INVERT</name> 5589 <description>Invert Gain.</description> 5590 <bitOffset>3</bitOffset> 5591 <bitWidth>1</bitWidth> 5592 <enumeratedValues> 5593 <enumeratedValue> 5594 <name>not</name> 5595 <description>Not Running.</description> 5596 <value>0</value> 5597 </enumeratedValue> 5598 <enumeratedValue> 5599 <name>run</name> 5600 <description>Running.</description> 5601 <value>1</value> 5602 </enumeratedValue> 5603 </enumeratedValues> 5604 </field> 5605 <field> 5606 <name>ATOMIC</name> 5607 <description>Atomic mode.</description> 5608 <bitOffset>4</bitOffset> 5609 <bitWidth>1</bitWidth> 5610 <enumeratedValues> 5611 <enumeratedValue> 5612 <name>not</name> 5613 <description>Not Running.</description> 5614 <value>0</value> 5615 </enumeratedValue> 5616 <enumeratedValue> 5617 <name>run</name> 5618 <description>Running.</description> 5619 <value>1</value> 5620 </enumeratedValue> 5621 </enumeratedValues> 5622 </field> 5623 <field> 5624 <name>GAIN</name> 5625 <description>MU value.</description> 5626 <bitOffset>8</bitOffset> 5627 <bitWidth>12</bitWidth> 5628 </field> 5629 <field> 5630 <name>TRIM</name> 5631 <description>150MHz HFIO Auto Calibration Trim</description> 5632 <bitOffset>23</bitOffset> 5633 <bitWidth>9</bitWidth> 5634 </field> 5635 </fields> 5636 </register> 5637 <register> 5638 <name>AUTOCAL1</name> 5639 <description>Register 2.</description> 5640 <addressOffset>0x08</addressOffset> 5641 <access>read-write</access> 5642 <fields> 5643 <field> 5644 <name>NFC_FWD_EN</name> 5645 <description>Enabled FWD mode for NFC block</description> 5646 <bitOffset>0</bitOffset> 5647 <bitWidth>1</bitWidth> 5648 </field> 5649 <field> 5650 <name>NFC_CLK_EN</name> 5651 <description>Enabled the NFC blocks clock divider in Analog</description> 5652 <bitOffset>1</bitOffset> 5653 <bitWidth>1</bitWidth> 5654 </field> 5655 <field> 5656 <name>NFC_FWD_TX_DATA_OVR</name> 5657 <description>FWD input for NFC block</description> 5658 <bitOffset>2</bitOffset> 5659 <bitWidth>1</bitWidth> 5660 </field> 5661 <field> 5662 <name>XO_EN_DGL</name> 5663 <description>TBD</description> 5664 <bitOffset>3</bitOffset> 5665 <bitWidth>1</bitWidth> 5666 </field> 5667 <field> 5668 <name>RX_BIAS_PD</name> 5669 <description>Power down enable for NFC receiver analog block</description> 5670 <bitOffset>4</bitOffset> 5671 <bitWidth>1</bitWidth> 5672 </field> 5673 <field> 5674 <name>RX_BIAS_EN</name> 5675 <description>Enable the NFC receiver analog blocks</description> 5676 <bitOffset>5</bitOffset> 5677 <bitWidth>1</bitWidth> 5678 </field> 5679 <field> 5680 <name>RX_TM_VBG_VABUS</name> 5681 <description>TBD</description> 5682 <bitOffset>6</bitOffset> 5683 <bitWidth>1</bitWidth> 5684 </field> 5685 <field> 5686 <name>RX_TM_BIAS</name> 5687 <description>TBD</description> 5688 <bitOffset>7</bitOffset> 5689 <bitWidth>1</bitWidth> 5690 </field> 5691 <field> 5692 <name>NFC_FWD_DOUT</name> 5693 <description>FWD output from FNC block</description> 5694 <bitOffset>8</bitOffset> 5695 <bitWidth>1</bitWidth> 5696 </field> 5697 </fields> 5698 </register> 5699 <register> 5700 <name>AUTOCAL2</name> 5701 <description>Register 3.</description> 5702 <addressOffset>0x0C</addressOffset> 5703 <access>read-write</access> 5704 <fields> 5705 <field> 5706 <name>RUNTIME</name> 5707 <description>Automatic Calibration Run Time.</description> 5708 <bitOffset>0</bitOffset> 5709 <bitWidth>8</bitWidth> 5710 </field> 5711 </fields> 5712 </register> 5713 </registers> 5714 </peripheral> 5715<!--FCR Function Control Register.--> 5716 <peripheral> 5717 <name>FLC</name> 5718 <description>Flash Memory Control.</description> 5719 <prependToName>FLSH_</prependToName> 5720 <baseAddress>0x40029000</baseAddress> 5721 <addressBlock> 5722 <offset>0x00</offset> 5723 <size>0x400</size> 5724 <usage>registers</usage> 5725 </addressBlock> 5726 <interrupt> 5727 <name>Flash_Controller</name> 5728 <description>Flash Controller interrupt.</description> 5729 <value>23</value> 5730 </interrupt> 5731 <registers> 5732 <register> 5733 <name>ADDR</name> 5734 <description>Flash Write Address.</description> 5735 <addressOffset>0x00</addressOffset> 5736 <fields> 5737 <field> 5738 <name>ADDR</name> 5739 <description>Address for next operation.</description> 5740 <bitOffset>0</bitOffset> 5741 <bitWidth>32</bitWidth> 5742 </field> 5743 </fields> 5744 </register> 5745 <register> 5746 <name>CLKDIV</name> 5747 <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description> 5748 <addressOffset>0x04</addressOffset> 5749 <resetValue>0x00000064</resetValue> 5750 <fields> 5751 <field> 5752 <name>CLKDIV</name> 5753 <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description> 5754 <bitOffset>0</bitOffset> 5755 <bitWidth>8</bitWidth> 5756 </field> 5757 </fields> 5758 </register> 5759 <register> 5760 <name>CN</name> 5761 <description>Flash Control Register.</description> 5762 <addressOffset>0x08</addressOffset> 5763 <fields> 5764 <field> 5765 <name>WR</name> 5766 <description>Write. This bit is automatically cleared after the operation.</description> 5767 <bitOffset>0</bitOffset> 5768 <bitWidth>1</bitWidth> 5769 <enumeratedValues> 5770 <enumeratedValue> 5771 <name>complete</name> 5772 <description>No operation/complete.</description> 5773 <value>0</value> 5774 </enumeratedValue> 5775 <enumeratedValue> 5776 <name>start</name> 5777 <description>Start operation.</description> 5778 <value>1</value> 5779 </enumeratedValue> 5780 </enumeratedValues> 5781 </field> 5782 <field derivedFrom="WR"> 5783 <name>ME</name> 5784 <description>Mass Erase. This bit is automatically cleared after the operation.</description> 5785 <bitOffset>1</bitOffset> 5786 <bitWidth>1</bitWidth> 5787 </field> 5788 <field derivedFrom="WR"> 5789 <name>PGE</name> 5790 <description>Page Erase. This bit is automatically cleared after the operation.</description> 5791 <bitOffset>2</bitOffset> 5792 <bitWidth>1</bitWidth> 5793 </field> 5794 <field> 5795 <name>ERASE_CODE</name> 5796 <description>Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description> 5797 <bitOffset>8</bitOffset> 5798 <bitWidth>8</bitWidth> 5799 <enumeratedValues> 5800 <enumeratedValue> 5801 <name>nop</name> 5802 <description>No operation.</description> 5803 <value>0</value> 5804 </enumeratedValue> 5805 <enumeratedValue> 5806 <name>erasePage</name> 5807 <description>Enable Page Erase.</description> 5808 <value>0x55</value> 5809 </enumeratedValue> 5810 <enumeratedValue> 5811 <name>eraseAll</name> 5812 <description>Enable Mass Erase. The debug port must be enabled.</description> 5813 <value>0xAA</value> 5814 </enumeratedValue> 5815 </enumeratedValues> 5816 </field> 5817 <field> 5818 <name>PEND</name> 5819 <description>Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description> 5820 <bitOffset>24</bitOffset> 5821 <bitWidth>1</bitWidth> 5822 <access>read-only</access> 5823 <enumeratedValues> 5824 <enumeratedValue> 5825 <name>idle</name> 5826 <description>Idle.</description> 5827 <value>0</value> 5828 </enumeratedValue> 5829 <enumeratedValue> 5830 <name>busy</name> 5831 <description>Busy.</description> 5832 <value>1</value> 5833 </enumeratedValue> 5834 </enumeratedValues> 5835 </field> 5836 <field> 5837 <name>UNLOCK</name> 5838 <description>Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description> 5839 <bitOffset>28</bitOffset> 5840 <bitWidth>4</bitWidth> 5841 <enumeratedValues> 5842 <enumeratedValue> 5843 <name>unlocked</name> 5844 <description>Flash Unlocked.</description> 5845 <value>2</value> 5846 </enumeratedValue> 5847 <enumeratedValue> 5848 <name>locked</name> 5849 <description>Flash Locked.</description> 5850 <value>3</value> 5851 </enumeratedValue> 5852 </enumeratedValues> 5853 </field> 5854 </fields> 5855 </register> 5856 <register> 5857 <name>INTR</name> 5858 <description>Flash Interrupt Register.</description> 5859 <addressOffset>0x24</addressOffset> 5860 <fields> 5861 <field> 5862 <name>DONE</name> 5863 <description>Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.</description> 5864 <bitOffset>0</bitOffset> 5865 <bitWidth>1</bitWidth> 5866 <enumeratedValues> 5867 <enumeratedValue> 5868 <name>inactive</name> 5869 <description>No interrupt is pending.</description> 5870 <value>0</value> 5871 </enumeratedValue> 5872 <enumeratedValue> 5873 <name>pending</name> 5874 <description>An interrupt is pending.</description> 5875 <value>1</value> 5876 </enumeratedValue> 5877 </enumeratedValues> 5878 </field> 5879 <field> 5880 <name>AF</name> 5881 <description>Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description> 5882 <bitOffset>1</bitOffset> 5883 <bitWidth>1</bitWidth> 5884 <enumeratedValues> 5885 <enumeratedValue> 5886 <name>noError</name> 5887 <description>No Failure.</description> 5888 <value>0</value> 5889 </enumeratedValue> 5890 <enumeratedValue> 5891 <name>error</name> 5892 <description>Failure occurs.</description> 5893 <value>1</value> 5894 </enumeratedValue> 5895 </enumeratedValues> 5896 </field> 5897 <field> 5898 <name>DONEIE</name> 5899 <description>Flash Done Interrupt Enable.</description> 5900 <bitOffset>8</bitOffset> 5901 <bitWidth>1</bitWidth> 5902 <enumeratedValues> 5903 <enumeratedValue> 5904 <name>disable</name> 5905 <description>Disable.</description> 5906 <value>0</value> 5907 </enumeratedValue> 5908 <enumeratedValue> 5909 <name>enable</name> 5910 <description>Enable.</description> 5911 <value>1</value> 5912 </enumeratedValue> 5913 </enumeratedValues> 5914 </field> 5915 <field derivedFrom="DONEIE"> 5916 <name>AFIE</name> 5917 <bitOffset>9</bitOffset> 5918 <bitWidth>1</bitWidth> 5919 </field> 5920 </fields> 5921 </register> 5922 <register> 5923 <name>ECC_DATA</name> 5924 <description>ECC Data Register.</description> 5925 <addressOffset>0x28</addressOffset> 5926 <fields> 5927 <field> 5928 <name>ECC_EVEN</name> 5929 <description>Error Correction Code Odd Data.</description> 5930 <bitOffset>0</bitOffset> 5931 <bitWidth>9</bitWidth> 5932 </field> 5933 <field> 5934 <name>ECC_ODD</name> 5935 <description>Error Correction Code Even Data.</description> 5936 <bitOffset>16</bitOffset> 5937 <bitWidth>9</bitWidth> 5938 </field> 5939 </fields> 5940 </register> 5941 <register> 5942 <dim>4</dim> 5943 <dimIncrement>4</dimIncrement> 5944 <name>DATA[%s]</name> 5945 <description>Flash Write Data.</description> 5946 <addressOffset>0x30</addressOffset> 5947 <fields> 5948 <field> 5949 <name>DATA</name> 5950 <description>Data next operation.</description> 5951 <bitOffset>0</bitOffset> 5952 <bitWidth>32</bitWidth> 5953 </field> 5954 </fields> 5955 </register> 5956 </registers> 5957 </peripheral> 5958<!--FLC Flash Memory Control.--> 5959 <peripheral derivedFrom="FLC"> 5960 <name>FLC1</name> 5961 <description>Flash Memory Control. 1</description> 5962 <baseAddress>0x40029400</baseAddress> 5963 <interrupt> 5964 <name>FLC1</name> 5965 <description>FLC1 IRQ</description> 5966 <value>87</value> 5967 </interrupt> 5968 </peripheral> 5969<!--FLC1 Flash Memory Control. 1--> 5970 <peripheral> 5971 <name>GCR</name> 5972 <description>Global Control Registers.</description> 5973 <baseAddress>0x40000000</baseAddress> 5974 <addressBlock> 5975 <offset>0</offset> 5976 <size>0x400</size> 5977 <usage>registers</usage> 5978 </addressBlock> 5979 <registers> 5980 <register> 5981 <name>SYSCTRL</name> 5982 <description>System Control.</description> 5983 <addressOffset>0x00</addressOffset> 5984 <resetMask>0xFFFFFFFE</resetMask> 5985 <fields> 5986 <field> 5987 <name>BSTAPEN</name> 5988 <description>Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.</description> 5989 <bitOffset>0</bitOffset> 5990 <bitWidth>1</bitWidth> 5991 <enumeratedValues> 5992 <enumeratedValue> 5993 <name>dis</name> 5994 <description>Boundary Scan TAP port disabled.</description> 5995 <value>0</value> 5996 </enumeratedValue> 5997 <enumeratedValue> 5998 <name>en</name> 5999 <description>Boundary Scan TAP port enabled.</description> 6000 <value>1</value> 6001 </enumeratedValue> 6002 </enumeratedValues> 6003 </field> 6004 <field> 6005 <name>SBUSARB</name> 6006 <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description> 6007 <bitOffset>1</bitOffset> 6008 <bitWidth>2</bitWidth> 6009 <enumeratedValues> 6010 <enumeratedValue> 6011 <name>fix</name> 6012 <description>Fixed Burst abritration.</description> 6013 <value>0</value> 6014 </enumeratedValue> 6015 <enumeratedValue> 6016 <name>round</name> 6017 <description>Round-robin scheme.</description> 6018 <value>1</value> 6019 </enumeratedValue> 6020 </enumeratedValues> 6021 </field> 6022 <field> 6023 <name>FLASH0_PAGE_FLIP</name> 6024 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 6025 <bitOffset>4</bitOffset> 6026 <bitWidth>1</bitWidth> 6027 <enumeratedValues> 6028 <enumeratedValue> 6029 <name>normal</name> 6030 <description>Physical layout matches logical layout.</description> 6031 <value>0</value> 6032 </enumeratedValue> 6033 <enumeratedValue> 6034 <name>swapped</name> 6035 <description>Bottom half mapped to logical top half and vice versa.</description> 6036 <value>1</value> 6037 </enumeratedValue> 6038 </enumeratedValues> 6039 </field> 6040 <field> 6041 <name>FPU_DIS</name> 6042 <description>Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4.</description> 6043 <bitOffset>5</bitOffset> 6044 <bitWidth>1</bitWidth> 6045 </field> 6046 <field> 6047 <name>ICC0_FLUSH</name> 6048 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 6049 <bitOffset>6</bitOffset> 6050 <bitWidth>1</bitWidth> 6051 <enumeratedValues> 6052 <enumeratedValue> 6053 <name>normal</name> 6054 <description>Normal Code Cache Operation</description> 6055 <value>0</value> 6056 </enumeratedValue> 6057 <enumeratedValue> 6058 <name>flush</name> 6059 <description>Code Caches and CPU instruction buffer are flushed </description> 6060 <value>1</value> 6061 </enumeratedValue> 6062 </enumeratedValues> 6063 </field> 6064 <field> 6065 <name>SRCC_FLUSH</name> 6066 <description>Data Cache Flush. The system cache (s) will be flushed when this bit is set. </description> 6067 <bitOffset>7</bitOffset> 6068 <bitWidth>1</bitWidth> 6069 <enumeratedValues> 6070 <enumeratedValue> 6071 <name>normal</name> 6072 <description>Normal System Cache Operation</description> 6073 <value>0</value> 6074 </enumeratedValue> 6075 <enumeratedValue> 6076 <name>flush</name> 6077 <description>System Cache is flushed </description> 6078 <value>1</value> 6079 </enumeratedValue> 6080 </enumeratedValues> 6081 </field> 6082 <field> 6083 <name>SRCC_DIS</name> 6084 <description>Data Cache Disable. The system cache (s) will be completely disabled when this bit is set.</description> 6085 <bitOffset>9</bitOffset> 6086 <bitWidth>1</bitWidth> 6087 <enumeratedValues> 6088 <enumeratedValue> 6089 <name>en</name> 6090 <description>Is enabled.</description> 6091 <value>0</value> 6092 </enumeratedValue> 6093 <enumeratedValue> 6094 <name>dis</name> 6095 <description>Is Disabled.</description> 6096 <value>1</value> 6097 </enumeratedValue> 6098 </enumeratedValues> 6099 </field> 6100 <field> 6101 <name>CCHK</name> 6102 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 6103 <bitOffset>13</bitOffset> 6104 <bitWidth>1</bitWidth> 6105 <enumeratedValues> 6106 <enumeratedValue> 6107 <name>complete</name> 6108 <description>No operation/complete.</description> 6109 <value>0</value> 6110 </enumeratedValue> 6111 <enumeratedValue> 6112 <name>start</name> 6113 <description>Start operation.</description> 6114 <value>1</value> 6115 </enumeratedValue> 6116 </enumeratedValues> 6117 </field> 6118 <field> 6119 <name>CHKRES</name> 6120 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 6121 <bitOffset>15</bitOffset> 6122 <bitWidth>1</bitWidth> 6123 <enumeratedValues> 6124 <enumeratedValue> 6125 <name>pass</name> 6126 <description>ROM Checksum Correct.</description> 6127 <value>0</value> 6128 </enumeratedValue> 6129 <enumeratedValue> 6130 <name>fail</name> 6131 <description>ROM Checksum Fail.</description> 6132 <value>1</value> 6133 </enumeratedValue> 6134 </enumeratedValues> 6135 </field> 6136 </fields> 6137 </register> 6138 <register> 6139 <name>RST0</name> 6140 <description>Reset.</description> 6141 <addressOffset>0x04</addressOffset> 6142 <fields> 6143 <field> 6144 <name>DMA</name> 6145 <description>DMA Reset.</description> 6146 <bitOffset>0</bitOffset> 6147 <bitWidth>1</bitWidth> 6148 </field> 6149 <field derivedFrom="DMA"> 6150 <name>WDT0</name> 6151 <description>Watchdog Timer Reset.</description> 6152 <bitOffset>1</bitOffset> 6153 <bitWidth>1</bitWidth> 6154 </field> 6155 <field derivedFrom="DMA"> 6156 <name>GPIO0</name> 6157 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 6158 <bitOffset>2</bitOffset> 6159 <bitWidth>1</bitWidth> 6160 </field> 6161 <field derivedFrom="DMA"> 6162 <name>GPIO1</name> 6163 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 6164 <bitOffset>3</bitOffset> 6165 <bitWidth>1</bitWidth> 6166 </field> 6167 <field derivedFrom="DMA"> 6168 <name>GPIO2</name> 6169 <description>GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states.</description> 6170 <bitOffset>4</bitOffset> 6171 <bitWidth>1</bitWidth> 6172 </field> 6173 <field derivedFrom="DMA"> 6174 <name>TMR0</name> 6175 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 6176 <bitOffset>5</bitOffset> 6177 <bitWidth>1</bitWidth> 6178 </field> 6179 <field derivedFrom="DMA"> 6180 <name>TMR1</name> 6181 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 6182 <bitOffset>6</bitOffset> 6183 <bitWidth>1</bitWidth> 6184 </field> 6185 <field derivedFrom="DMA"> 6186 <name>TMR2</name> 6187 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 6188 <bitOffset>7</bitOffset> 6189 <bitWidth>1</bitWidth> 6190 </field> 6191 <field derivedFrom="DMA"> 6192 <name>TMR3</name> 6193 <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 6194 <bitOffset>8</bitOffset> 6195 <bitWidth>1</bitWidth> 6196 </field> 6197 <field derivedFrom="DMA"> 6198 <name>TMR4</name> 6199 <description>Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks.</description> 6200 <bitOffset>9</bitOffset> 6201 <bitWidth>1</bitWidth> 6202 </field> 6203 <field derivedFrom="DMA"> 6204 <name>TMR5</name> 6205 <description>Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks.</description> 6206 <bitOffset>10</bitOffset> 6207 <bitWidth>1</bitWidth> 6208 </field> 6209 <field derivedFrom="DMA"> 6210 <name>UART0</name> 6211 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 6212 <bitOffset>11</bitOffset> 6213 <bitWidth>1</bitWidth> 6214 </field> 6215 <field derivedFrom="DMA"> 6216 <name>UART1</name> 6217 <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 6218 <bitOffset>12</bitOffset> 6219 <bitWidth>1</bitWidth> 6220 </field> 6221 <field derivedFrom="DMA"> 6222 <name>SPI0</name> 6223 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 6224 <bitOffset>13</bitOffset> 6225 <bitWidth>1</bitWidth> 6226 </field> 6227 <field derivedFrom="DMA"> 6228 <name>SPI1</name> 6229 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 6230 <bitOffset>14</bitOffset> 6231 <bitWidth>1</bitWidth> 6232 </field> 6233 <field derivedFrom="DMA"> 6234 <name>SPI2</name> 6235 <description>SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description> 6236 <bitOffset>15</bitOffset> 6237 <bitWidth>1</bitWidth> 6238 </field> 6239 <field derivedFrom="DMA"> 6240 <name>I2C0</name> 6241 <description>I2C0 Reset.</description> 6242 <bitOffset>16</bitOffset> 6243 <bitWidth>1</bitWidth> 6244 </field> 6245 <field derivedFrom="DMA"> 6246 <name>RTC</name> 6247 <description>Real Time Clock Reset.</description> 6248 <bitOffset>17</bitOffset> 6249 <bitWidth>1</bitWidth> 6250 </field> 6251 <field derivedFrom="DMA"> 6252 <name>CRYPTO</name> 6253 <description>Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.</description> 6254 <bitOffset>18</bitOffset> 6255 <bitWidth>1</bitWidth> 6256 </field> 6257 <field derivedFrom="DMA"> 6258 <name>TMR6</name> 6259 <description>Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks.</description> 6260 <bitOffset>20</bitOffset> 6261 <bitWidth>1</bitWidth> 6262 </field> 6263 <field derivedFrom="DMA"> 6264 <name>TMR7</name> 6265 <description>Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks.</description> 6266 <bitOffset>21</bitOffset> 6267 <bitWidth>1</bitWidth> 6268 </field> 6269 <field derivedFrom="DMA"> 6270 <name>CLCD</name> 6271 <description>CLCD Reset. Setting this bit to 1 resets the CLCD block.</description> 6272 <bitOffset>22</bitOffset> 6273 <bitWidth>1</bitWidth> 6274 </field> 6275 <field derivedFrom="DMA"> 6276 <name>USB</name> 6277 <description>USB Reset. Setting this bit resets both USB blocks.</description> 6278 <bitOffset>23</bitOffset> 6279 <bitWidth>1</bitWidth> 6280 </field> 6281 <field derivedFrom="DMA"> 6282 <name>ADC</name> 6283 <description>Analog to Digital Reset.</description> 6284 <bitOffset>26</bitOffset> 6285 <bitWidth>1</bitWidth> 6286 </field> 6287 <field derivedFrom="DMA"> 6288 <name>UART2</name> 6289 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 6290 <bitOffset>28</bitOffset> 6291 <bitWidth>1</bitWidth> 6292 </field> 6293 <field derivedFrom="DMA"> 6294 <name>SOFT</name> 6295 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 6296 <bitOffset>29</bitOffset> 6297 <bitWidth>1</bitWidth> 6298 </field> 6299 <field derivedFrom="DMA"> 6300 <name>PERIPH</name> 6301 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 6302 <bitOffset>30</bitOffset> 6303 <bitWidth>1</bitWidth> 6304 </field> 6305 <field derivedFrom="DMA"> 6306 <name>SYS</name> 6307 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 6308 <bitOffset>31</bitOffset> 6309 <bitWidth>1</bitWidth> 6310 </field> 6311 </fields> 6312 </register> 6313 <register> 6314 <name>CLKCTRL</name> 6315 <description>Clock Control.</description> 6316 <addressOffset>0x08</addressOffset> 6317 <resetValue>0x00000008</resetValue> 6318 <fields> 6319 <field> 6320 <name>SYSCLK_DIV</name> 6321 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 6322 <bitOffset>6</bitOffset> 6323 <bitWidth>3</bitWidth> 6324 <enumeratedValues> 6325 <enumeratedValue> 6326 <name>div1</name> 6327 <description>Divide by 1.</description> 6328 <value>0</value> 6329 </enumeratedValue> 6330 <enumeratedValue> 6331 <name>div2</name> 6332 <description>Divide by 2.</description> 6333 <value>1</value> 6334 </enumeratedValue> 6335 <enumeratedValue> 6336 <name>div4</name> 6337 <description>Divide by 4.</description> 6338 <value>2</value> 6339 </enumeratedValue> 6340 <enumeratedValue> 6341 <name>div8</name> 6342 <description>Divide by 8.</description> 6343 <value>3</value> 6344 </enumeratedValue> 6345 <enumeratedValue> 6346 <name>div16</name> 6347 <description>Divide by 16.</description> 6348 <value>4</value> 6349 </enumeratedValue> 6350 <enumeratedValue> 6351 <name>div32</name> 6352 <description>Divide by 32.</description> 6353 <value>5</value> 6354 </enumeratedValue> 6355 <enumeratedValue> 6356 <name>div64</name> 6357 <description>Divide by 64.</description> 6358 <value>6</value> 6359 </enumeratedValue> 6360 <enumeratedValue> 6361 <name>div128</name> 6362 <description>Divide by 128.</description> 6363 <value>7</value> 6364 </enumeratedValue> 6365 </enumeratedValues> 6366 </field> 6367 <field> 6368 <name>SYSCLK_SEL</name> 6369 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 6370 <bitOffset>9</bitOffset> 6371 <bitWidth>3</bitWidth> 6372 <enumeratedValues> 6373 <enumeratedValue> 6374 <name>ISO</name> 6375 <description>Internal Secondary Oscilatior Clock</description> 6376 <value>0</value> 6377 </enumeratedValue> 6378 <enumeratedValue> 6379 <name>ERFO</name> 6380 <description>27MHz Crystal is used for the system clock.</description> 6381 <value>2</value> 6382 </enumeratedValue> 6383 <enumeratedValue> 6384 <name>INRO</name> 6385 <description>8kHz Internal Nano Ring Oscillator is used for the system clock.</description> 6386 <value>3</value> 6387 </enumeratedValue> 6388 <enumeratedValue> 6389 <name>IPO</name> 6390 <description>The internal Primary oscillator is used for the system clock.</description> 6391 <value>4</value> 6392 </enumeratedValue> 6393 <enumeratedValue> 6394 <name>IBRO</name> 6395 <description>The internal Baud Rate oscillator is used for the system clock.</description> 6396 <value>5</value> 6397 </enumeratedValue> 6398 <enumeratedValue> 6399 <name>ERTCO</name> 6400 <description> 32kHz is used for the system clock.</description> 6401 <value>6</value> 6402 </enumeratedValue> 6403 </enumeratedValues> 6404 </field> 6405 <field> 6406 <name>SYSCLK_RDY</name> 6407 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 6408 <bitOffset>13</bitOffset> 6409 <bitWidth>1</bitWidth> 6410 <access>read-only</access> 6411 <enumeratedValues> 6412 <enumeratedValue> 6413 <name>busy</name> 6414 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 6415 <value>0</value> 6416 </enumeratedValue> 6417 <enumeratedValue> 6418 <name>ready</name> 6419 <description>System clock running from CLKSEL clock source.</description> 6420 <value>1</value> 6421 </enumeratedValue> 6422 </enumeratedValues> 6423 </field> 6424 <field> 6425 <name>CCD</name> 6426 <description>Cryptographic clock divider</description> 6427 <bitOffset>15</bitOffset> 6428 <bitWidth>1</bitWidth> 6429 <access>read-only</access> 6430 <enumeratedValues> 6431 <enumeratedValue> 6432 <name>non_div</name> 6433 <description>The cryptographic accelerator clock is running in non-divided mode.</description> 6434 <value>0</value> 6435 </enumeratedValue> 6436 <enumeratedValue> 6437 <name>div</name> 6438 <description>The cryptographic accelerator clock is running in divided mode.</description> 6439 <value>1</value> 6440 </enumeratedValue> 6441 </enumeratedValues> 6442 </field> 6443 <field> 6444 <name>ERFO_EN</name> 6445 <description>27MHz Crystal Oscillator Enable.</description> 6446 <bitOffset>16</bitOffset> 6447 <bitWidth>1</bitWidth> 6448 <enumeratedValues> 6449 <enumeratedValue> 6450 <name>dis</name> 6451 <description>Is Disabled.</description> 6452 <value>0</value> 6453 </enumeratedValue> 6454 <enumeratedValue> 6455 <name>en</name> 6456 <description>Is Enabled.</description> 6457 <value>1</value> 6458 </enumeratedValue> 6459 </enumeratedValues> 6460 </field> 6461 <field> 6462 <name>ERTCO_EN</name> 6463 <description>32kHz Crystal Oscillator Enable.</description> 6464 <bitOffset>17</bitOffset> 6465 <bitWidth>1</bitWidth> 6466 </field> 6467 <field derivedFrom="ERTCO_EN"> 6468 <name>ISO_EN</name> 6469 <description>60MHz High Frequency Internal Reference Clock Enable.</description> 6470 <bitOffset>18</bitOffset> 6471 <bitWidth>1</bitWidth> 6472 </field> 6473 <field derivedFrom="ERTCO_EN"> 6474 <name>IPO_EN</name> 6475 <description>96MHz High Frequency Internal Reference Clock Enable.</description> 6476 <bitOffset>19</bitOffset> 6477 <bitWidth>1</bitWidth> 6478 </field> 6479 <field derivedFrom="ERTCO_EN"> 6480 <name>IBRO_EN</name> 6481 <description>8MHz High Frequency Internal Reference Clock Enable.</description> 6482 <bitOffset>20</bitOffset> 6483 <bitWidth>1</bitWidth> 6484 </field> 6485 <field> 6486 <name>IBRO_VS</name> 6487 <description>7.3728MHz Internal Oscillator Voltage Source Select</description> 6488 <bitOffset>21</bitOffset> 6489 <bitWidth>1</bitWidth> 6490 </field> 6491 <field> 6492 <name>ERFO_RDY</name> 6493 <description>27MHz Crystal Oscillator Ready</description> 6494 <bitOffset>24</bitOffset> 6495 <bitWidth>1</bitWidth> 6496 <access>read-only</access> 6497 <enumeratedValues> 6498 <enumeratedValue> 6499 <name>not</name> 6500 <description>Is not Ready.</description> 6501 <value>0</value> 6502 </enumeratedValue> 6503 <enumeratedValue> 6504 <name>ready</name> 6505 <description>Is Ready.</description> 6506 <value>1</value> 6507 </enumeratedValue> 6508 </enumeratedValues> 6509 </field> 6510 <field> 6511 <name>ERTCO_RDY</name> 6512 <description>32kHz Crystal Oscillator Ready</description> 6513 <bitOffset>25</bitOffset> 6514 <bitWidth>1</bitWidth> 6515 <access>read-only</access> 6516 <enumeratedValues> 6517 <enumeratedValue> 6518 <name>not</name> 6519 <description>Is not Ready.</description> 6520 <value>0</value> 6521 </enumeratedValue> 6522 <enumeratedValue> 6523 <name>ready</name> 6524 <description>Is Ready.</description> 6525 <value>1</value> 6526 </enumeratedValue> 6527 </enumeratedValues> 6528 </field> 6529 <field derivedFrom="ERTCO_RDY"> 6530 <name>ISO_RDY</name> 6531 <description>60MHz ISO Ready.</description> 6532 <bitOffset>26</bitOffset> 6533 <bitWidth>1</bitWidth> 6534 </field> 6535 <field derivedFrom="ERTCO_RDY"> 6536 <name>IPO_RDY</name> 6537 <description>Internal Primary Oscillator Ready.</description> 6538 <bitOffset>27</bitOffset> 6539 <bitWidth>1</bitWidth> 6540 </field> 6541 <field derivedFrom="ERTCO_RDY"> 6542 <name>IBRO_RDY</name> 6543 <description>Internal Baud Rate Oscillator Ready.</description> 6544 <bitOffset>28</bitOffset> 6545 <bitWidth>1</bitWidth> 6546 </field> 6547 <field derivedFrom="ERTCO_RDY"> 6548 <name>INRO_RDY</name> 6549 <description>Internal Nano Ring Oscillator Low Frequency Reference Clock Ready.</description> 6550 <bitOffset>29</bitOffset> 6551 <bitWidth>1</bitWidth> 6552 </field> 6553 </fields> 6554 </register> 6555 <register> 6556 <name>PM</name> 6557 <description>Power Management.</description> 6558 <addressOffset>0x0C</addressOffset> 6559 <fields> 6560 <field> 6561 <name>MODE</name> 6562 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 6563 <bitOffset>0</bitOffset> 6564 <bitWidth>3</bitWidth> 6565 <enumeratedValues> 6566 <enumeratedValue> 6567 <name>active</name> 6568 <description>Active Mode.</description> 6569 <value>0</value> 6570 </enumeratedValue> 6571 <enumeratedValue> 6572 <name>deepsleep</name> 6573 <description>DeepSleep Mode.</description> 6574 <value>2</value> 6575 </enumeratedValue> 6576 <enumeratedValue> 6577 <name>shutdown</name> 6578 <description>Shutdown Mode.</description> 6579 <value>3</value> 6580 </enumeratedValue> 6581 <enumeratedValue> 6582 <name>backup</name> 6583 <description>Backup Mode.</description> 6584 <value>4</value> 6585 </enumeratedValue> 6586 </enumeratedValues> 6587 </field> 6588 <field> 6589 <name>GPIO_WE</name> 6590 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 6591 <bitOffset>4</bitOffset> 6592 <bitWidth>1</bitWidth> 6593 </field> 6594 <field derivedFrom="GPIO_WE"> 6595 <name>RTC_WE</name> 6596 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 6597 <bitOffset>5</bitOffset> 6598 <bitWidth>1</bitWidth> 6599 </field> 6600 <field derivedFrom="GPIO_WE"> 6601 <name>USB_WE</name> 6602 <description>USB Wake Up Enable. This bit enables USB activity as wakeup source.</description> 6603 <bitOffset>6</bitOffset> 6604 <bitWidth>1</bitWidth> 6605 </field> 6606 <field derivedFrom="GPIO_WE"> 6607 <name>HA0_WE</name> 6608 <description>Hardware Accelerator 0 Wake Up Enable. This bit enables USB activity as wakeup source.</description> 6609 <bitOffset>7</bitOffset> 6610 <bitWidth>1</bitWidth> 6611 </field> 6612 <field derivedFrom="GPIO_WE"> 6613 <name>HA1_WE</name> 6614 <description>Hardware Accelerator 1 Wake Up Enable. This bit enables USB activity as wakeup source.</description> 6615 <bitOffset>9</bitOffset> 6616 <bitWidth>1</bitWidth> 6617 </field> 6618 <field> 6619 <name>ERFO_PD</name> 6620 <description>Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. </description> 6621 <bitOffset>12</bitOffset> 6622 <bitWidth>1</bitWidth> 6623 <enumeratedValues> 6624 <enumeratedValue> 6625 <name>active</name> 6626 <description>Mode is Active.</description> 6627 <value>0</value> 6628 </enumeratedValue> 6629 <enumeratedValue> 6630 <name>deepsleep</name> 6631 <description>Powered down in DEEPSLEEP.</description> 6632 <value>1</value> 6633 </enumeratedValue> 6634 </enumeratedValues> 6635 </field> 6636 <field> 6637 <name>ISO_PD</name> 6638 <description>Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. </description> 6639 <bitOffset>15</bitOffset> 6640 <bitWidth>1</bitWidth> 6641 <enumeratedValues> 6642 <enumeratedValue> 6643 <name>active</name> 6644 <description>Mode is Active.</description> 6645 <value>0</value> 6646 </enumeratedValue> 6647 <enumeratedValue> 6648 <name>deepsleep</name> 6649 <description>Powered down in DEEPSLEEP.</description> 6650 <value>1</value> 6651 </enumeratedValue> 6652 </enumeratedValues> 6653 </field> 6654 <field> 6655 <name>IPO_PD</name> 6656 <description>Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. </description> 6657 <bitOffset>16</bitOffset> 6658 <bitWidth>1</bitWidth> 6659 <enumeratedValues> 6660 <enumeratedValue> 6661 <name>active</name> 6662 <description>Mode is Active.</description> 6663 <value>0</value> 6664 </enumeratedValue> 6665 <enumeratedValue> 6666 <name>deepsleep</name> 6667 <description>Powered down in DEEPSLEEP.</description> 6668 <value>1</value> 6669 </enumeratedValue> 6670 </enumeratedValues> 6671 </field> 6672 <field> 6673 <name>IBRO_PD</name> 6674 <description>Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. </description> 6675 <bitOffset>17</bitOffset> 6676 <bitWidth>1</bitWidth> 6677 <enumeratedValues> 6678 <enumeratedValue> 6679 <name>active</name> 6680 <description>Mode is Active.</description> 6681 <value>0</value> 6682 </enumeratedValue> 6683 <enumeratedValue> 6684 <name>deepsleep</name> 6685 <description>Powered down in DEEPSLEEP.</description> 6686 <value>1</value> 6687 </enumeratedValue> 6688 </enumeratedValues> 6689 </field> 6690 <field> 6691 <name>NFC_PD</name> 6692 <description>When set, the NFC radio becomes inactive when the upon entering DEEPSLEEP mode</description> 6693 <bitOffset>18</bitOffset> 6694 <bitWidth>1</bitWidth> 6695 <enumeratedValues> 6696 <enumeratedValue> 6697 <name>active</name> 6698 <description>Mode is Active.</description> 6699 <value>0</value> 6700 </enumeratedValue> 6701 <enumeratedValue> 6702 <name>deepsleep</name> 6703 <description>Powered down in DEEPSLEEP.</description> 6704 <value>1</value> 6705 </enumeratedValue> 6706 </enumeratedValues> 6707 </field> 6708 <field> 6709 <name>XTALBP</name> 6710 <description>XTAL Bypass </description> 6711 <bitOffset>20</bitOffset> 6712 <bitWidth>1</bitWidth> 6713 <enumeratedValues> 6714 <enumeratedValue> 6715 <name>normal</name> 6716 <description>Normal</description> 6717 <value>0</value> 6718 </enumeratedValue> 6719 <enumeratedValue> 6720 <name>bypass</name> 6721 <description>Bypass</description> 6722 <value>1</value> 6723 </enumeratedValue> 6724 </enumeratedValues> 6725 </field> 6726 </fields> 6727 </register> 6728 <register> 6729 <name>PCLKDIV</name> 6730 <description>Peripheral Clock Divider.</description> 6731 <addressOffset>0x18</addressOffset> 6732 <resetValue>0x00000001</resetValue> 6733 <fields> 6734 <field> 6735 <name>PCF</name> 6736 <description>These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware.</description> 6737 <bitOffset>0</bitOffset> 6738 <bitWidth>3</bitWidth> 6739 <enumeratedValues> 6740 <enumeratedValue> 6741 <name>96MHz</name> 6742 <value>2</value> 6743 </enumeratedValue> 6744 <enumeratedValue> 6745 <name>48MHz</name> 6746 <value>3</value> 6747 </enumeratedValue> 6748 <enumeratedValue> 6749 <name>24MHz</name> 6750 <value>4</value> 6751 </enumeratedValue> 6752 <enumeratedValue> 6753 <name>12MHz</name> 6754 <value>5</value> 6755 </enumeratedValue> 6756 <enumeratedValue> 6757 <name>6MHz</name> 6758 <value>6</value> 6759 </enumeratedValue> 6760 <enumeratedValue> 6761 <name>3MHz</name> 6762 <value>7</value> 6763 </enumeratedValue> 6764 </enumeratedValues> 6765 </field> 6766 <field> 6767 <name>PCFWEN</name> 6768 <description>PCF Write Enable. This bit allows the PCF Register bits to be updated by Software.</description> 6769 <bitOffset>3</bitOffset> 6770 <bitWidth>1</bitWidth> 6771 <enumeratedValues> 6772 <enumeratedValue> 6773 <name>blocked</name> 6774 <description>Writes to PCF are blocked.</description> 6775 <value>0</value> 6776 </enumeratedValue> 6777 <enumeratedValue> 6778 <name>allowed</name> 6779 <description>Writes to PCF are allowed</description> 6780 <value>1</value> 6781 </enumeratedValue> 6782 </enumeratedValues> 6783 </field> 6784 <field> 6785 <name>SDHCFRQ</name> 6786 <description>SDHC Clock Frequency. This bits defines the clock frequency of SDHC.</description> 6787 <bitOffset>7</bitOffset> 6788 <bitWidth>1</bitWidth> 6789 <enumeratedValues> 6790 <enumeratedValue> 6791 <name>48MHz</name> 6792 <value>0</value> 6793 </enumeratedValue> 6794 <enumeratedValue> 6795 <name>24MHz</name> 6796 <value>1</value> 6797 </enumeratedValue> 6798 </enumeratedValues> 6799 </field> 6800 <field> 6801 <name>ADCFRQ</name> 6802 <description>ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/ (ADCFRQ).</description> 6803 <bitOffset>10</bitOffset> 6804 <bitWidth>4</bitWidth> 6805 </field> 6806 <field> 6807 <name>AON_CLKDIV</name> 6808 <description>Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider.</description> 6809 <bitOffset>14</bitOffset> 6810 <bitWidth>2</bitWidth> 6811 <enumeratedValues> 6812 <enumeratedValue> 6813 <name>div_4</name> 6814 <description>PCLK divide by 4.</description> 6815 <value>0</value> 6816 </enumeratedValue> 6817 <enumeratedValue> 6818 <name>div_8</name> 6819 <description>PCLK divide by 8.</description> 6820 <value>1</value> 6821 </enumeratedValue> 6822 <enumeratedValue> 6823 <name>div_16</name> 6824 <description>PCLK divide by 16.</description> 6825 <value>2</value> 6826 </enumeratedValue> 6827 <enumeratedValue> 6828 <name>div_32</name> 6829 <description>PCLK divide by 32.</description> 6830 <value>3</value> 6831 </enumeratedValue> 6832 </enumeratedValues> 6833 </field> 6834 </fields> 6835 </register> 6836 <register> 6837 <name>PCLKDIS0</name> 6838 <description>Peripheral Clock Disable.</description> 6839 <addressOffset>0x24</addressOffset> 6840 <fields> 6841 <field> 6842 <name>GPIO0</name> 6843 <description>GPIO0 Clock Disable.</description> 6844 <bitOffset>0</bitOffset> 6845 <bitWidth>1</bitWidth> 6846 <enumeratedValues> 6847 <enumeratedValue> 6848 <name>en</name> 6849 <description>enable it.</description> 6850 <value>0</value> 6851 </enumeratedValue> 6852 <enumeratedValue> 6853 <name>dis</name> 6854 <description>disable it.</description> 6855 <value>1</value> 6856 </enumeratedValue> 6857 </enumeratedValues> 6858 </field> 6859 <field derivedFrom="GPIO0"> 6860 <name>GPIO1</name> 6861 <description>GPIO1 Disable.</description> 6862 <bitOffset>1</bitOffset> 6863 <bitWidth>1</bitWidth> 6864 </field> 6865 <field derivedFrom="GPIO0"> 6866 <name>GPIO2</name> 6867 <description>GPIO2 Disable.</description> 6868 <bitOffset>2</bitOffset> 6869 <bitWidth>1</bitWidth> 6870 </field> 6871 <field derivedFrom="GPIO0"> 6872 <name>USB</name> 6873 <description>USB Disable.</description> 6874 <bitOffset>3</bitOffset> 6875 <bitWidth>1</bitWidth> 6876 </field> 6877 <field derivedFrom="GPIO0"> 6878 <name>CLCD</name> 6879 <description>CLCD Disable.</description> 6880 <bitOffset>4</bitOffset> 6881 <bitWidth>1</bitWidth> 6882 </field> 6883 <field derivedFrom="GPIO0"> 6884 <name>DMA</name> 6885 <description>DMA Disable.</description> 6886 <bitOffset>5</bitOffset> 6887 <bitWidth>1</bitWidth> 6888 </field> 6889 <field derivedFrom="GPIO0"> 6890 <name>SPI0</name> 6891 <description>SPI 0 Disable.</description> 6892 <bitOffset>6</bitOffset> 6893 <bitWidth>1</bitWidth> 6894 </field> 6895 <field derivedFrom="GPIO0"> 6896 <name>SPI1</name> 6897 <description>SPI 1 Disable.</description> 6898 <bitOffset>7</bitOffset> 6899 <bitWidth>1</bitWidth> 6900 </field> 6901 <field derivedFrom="GPIO0"> 6902 <name>SPI2</name> 6903 <description>SPI 2 Disable.</description> 6904 <bitOffset>8</bitOffset> 6905 <bitWidth>1</bitWidth> 6906 </field> 6907 <field derivedFrom="GPIO0"> 6908 <name>UART0</name> 6909 <description>UART 0 Disable.</description> 6910 <bitOffset>9</bitOffset> 6911 <bitWidth>1</bitWidth> 6912 </field> 6913 <field derivedFrom="GPIO0"> 6914 <name>UART1</name> 6915 <description>UART 1 Disable.</description> 6916 <bitOffset>10</bitOffset> 6917 <bitWidth>1</bitWidth> 6918 </field> 6919 <field derivedFrom="GPIO0"> 6920 <name>I2C0</name> 6921 <description>I2C 0 Disable.</description> 6922 <bitOffset>13</bitOffset> 6923 <bitWidth>1</bitWidth> 6924 </field> 6925 <field derivedFrom="GPIO0"> 6926 <name>CRYPTO</name> 6927 <description>Crypto Disable.</description> 6928 <bitOffset>14</bitOffset> 6929 <bitWidth>1</bitWidth> 6930 </field> 6931 <field derivedFrom="GPIO0"> 6932 <name>TMR0</name> 6933 <description>Timer 0 Disable.</description> 6934 <bitOffset>15</bitOffset> 6935 <bitWidth>1</bitWidth> 6936 </field> 6937 <field derivedFrom="GPIO0"> 6938 <name>TMR1</name> 6939 <description>Timer 1 Disable.</description> 6940 <bitOffset>16</bitOffset> 6941 <bitWidth>1</bitWidth> 6942 </field> 6943 <field derivedFrom="GPIO0"> 6944 <name>TMR2</name> 6945 <description>Timer 2 Disable.</description> 6946 <bitOffset>17</bitOffset> 6947 <bitWidth>1</bitWidth> 6948 </field> 6949 <field derivedFrom="GPIO0"> 6950 <name>TMR3</name> 6951 <description>Timer 3 Disable.</description> 6952 <bitOffset>18</bitOffset> 6953 <bitWidth>1</bitWidth> 6954 </field> 6955 <field derivedFrom="GPIO0"> 6956 <name>TMR4</name> 6957 <description>Timer 4 Disable.</description> 6958 <bitOffset>19</bitOffset> 6959 <bitWidth>1</bitWidth> 6960 </field> 6961 <field derivedFrom="GPIO0"> 6962 <name>TMR5</name> 6963 <description>Timer 5 Disable.</description> 6964 <bitOffset>20</bitOffset> 6965 <bitWidth>1</bitWidth> 6966 </field> 6967 <field derivedFrom="GPIO0"> 6968 <name>KBD</name> 6969 <description>Secure Keyboard Disable.</description> 6970 <bitOffset>22</bitOffset> 6971 <bitWidth>1</bitWidth> 6972 </field> 6973 <field derivedFrom="GPIO0"> 6974 <name>ADC</name> 6975 <description>ADC Disable.</description> 6976 <bitOffset>23</bitOffset> 6977 <bitWidth>1</bitWidth> 6978 </field> 6979 <field derivedFrom="GPIO0"> 6980 <name>TMR6</name> 6981 <description>Timer 6 Disable.</description> 6982 <bitOffset>24</bitOffset> 6983 <bitWidth>1</bitWidth> 6984 </field> 6985 <field derivedFrom="GPIO0"> 6986 <name>TMR7</name> 6987 <description>Timer 7 Disable.</description> 6988 <bitOffset>25</bitOffset> 6989 <bitWidth>1</bitWidth> 6990 </field> 6991 <field derivedFrom="GPIO0"> 6992 <name>HTMR0</name> 6993 <description>HTimer 0 Disable.</description> 6994 <bitOffset>26</bitOffset> 6995 <bitWidth>1</bitWidth> 6996 </field> 6997 <field derivedFrom="GPIO0"> 6998 <name>HTMR1</name> 6999 <description>HTimer 1 Disable.</description> 7000 <bitOffset>27</bitOffset> 7001 <bitWidth>1</bitWidth> 7002 </field> 7003 <field derivedFrom="GPIO0"> 7004 <name>I2C1</name> 7005 <description>I2C 1 Disable.</description> 7006 <bitOffset>28</bitOffset> 7007 <bitWidth>1</bitWidth> 7008 </field> 7009 <field derivedFrom="GPIO0"> 7010 <name>PT</name> 7011 <description>PT Clock Disable.</description> 7012 <bitOffset>29</bitOffset> 7013 <bitWidth>1</bitWidth> 7014 </field> 7015 <field derivedFrom="GPIO0"> 7016 <name>SPIXIP</name> 7017 <description>SPI XiP Disable.</description> 7018 <bitOffset>30</bitOffset> 7019 <bitWidth>1</bitWidth> 7020 </field> 7021 <field derivedFrom="GPIO0"> 7022 <name>SPIM</name> 7023 <description>SPI XiP Master Controller Disable.</description> 7024 <bitOffset>31</bitOffset> 7025 <bitWidth>1</bitWidth> 7026 </field> 7027 </fields> 7028 </register> 7029 <register> 7030 <name>MEMCTRL</name> 7031 <description>Memory Clock Control Register.</description> 7032 <addressOffset>0x28</addressOffset> 7033 <fields> 7034 <field> 7035 <name>FWS</name> 7036 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 7037 <bitOffset>0</bitOffset> 7038 <bitWidth>3</bitWidth> 7039 </field> 7040 <field> 7041 <name>RAMWS_EN</name> 7042 <description>SRAM Wait State Enable</description> 7043 <bitOffset>4</bitOffset> 7044 <bitWidth>1</bitWidth> 7045 </field> 7046 <field> 7047 <name>RAM0LS_EN</name> 7048 <description>System RAM 0 Light Sleep Mode.</description> 7049 <bitOffset>16</bitOffset> 7050 <bitWidth>1</bitWidth> 7051 <enumeratedValues> 7052 <enumeratedValue> 7053 <name>active</name> 7054 <description>RAM is active.</description> 7055 <value>0</value> 7056 </enumeratedValue> 7057 <enumeratedValue> 7058 <name>light_sleep</name> 7059 <description>RAM is in Light Sleep mode.</description> 7060 <value>1</value> 7061 </enumeratedValue> 7062 </enumeratedValues> 7063 </field> 7064 <field derivedFrom="RAM0LS_EN"> 7065 <name>RAM1LS_EN</name> 7066 <description>System RAM 1 Light Sleep Mode.</description> 7067 <bitOffset>17</bitOffset> 7068 <bitWidth>1</bitWidth> 7069 </field> 7070 <field derivedFrom="RAM0LS_EN"> 7071 <name>RAM2LS_EN</name> 7072 <description>System RAM 2 Light Sleep Mode.</description> 7073 <bitOffset>18</bitOffset> 7074 <bitWidth>1</bitWidth> 7075 </field> 7076 <field derivedFrom="RAM0LS_EN"> 7077 <name>RAM3LS_EN</name> 7078 <description>System RAM 3 Light Sleep Mode.</description> 7079 <bitOffset>19</bitOffset> 7080 <bitWidth>1</bitWidth> 7081 </field> 7082 <field derivedFrom="RAM0LS_EN"> 7083 <name>RAM4LS_EN</name> 7084 <description>System RAM 4 Light Sleep Mode.</description> 7085 <bitOffset>20</bitOffset> 7086 <bitWidth>1</bitWidth> 7087 </field> 7088 <field derivedFrom="RAM0LS_EN"> 7089 <name>RAM5LS_EN</name> 7090 <description>System RAM 5 Light Sleep Mode.</description> 7091 <bitOffset>21</bitOffset> 7092 <bitWidth>1</bitWidth> 7093 </field> 7094 <field derivedFrom="RAM0LS_EN"> 7095 <name>ICC0LS_EN</name> 7096 <description>ICache RAM Light Sleep Mode.</description> 7097 <bitOffset>24</bitOffset> 7098 <bitWidth>1</bitWidth> 7099 </field> 7100 <field derivedFrom="RAM0LS_EN"> 7101 <name>ICCXIPLS_EN</name> 7102 <description>ICACHE-XIP RAM Light Sleep Mode.</description> 7103 <bitOffset>25</bitOffset> 7104 <bitWidth>1</bitWidth> 7105 </field> 7106 <field derivedFrom="RAM0LS_EN"> 7107 <name>SRCCLS_EN</name> 7108 <description>SysCache RAM Light Sleep Mode.</description> 7109 <bitOffset>26</bitOffset> 7110 <bitWidth>1</bitWidth> 7111 </field> 7112 <field derivedFrom="RAM0LS_EN"> 7113 <name>CRYPTOLS_EN</name> 7114 <description>CRYPTO RAM Light Sleep Mode.</description> 7115 <bitOffset>27</bitOffset> 7116 <bitWidth>1</bitWidth> 7117 </field> 7118 <field derivedFrom="RAM0LS_EN"> 7119 <name>USBLS_EN</name> 7120 <description>USB FIFO Light Sleep Mode.</description> 7121 <bitOffset>28</bitOffset> 7122 <bitWidth>1</bitWidth> 7123 </field> 7124 <field derivedFrom="RAM0LS_EN"> 7125 <name>ROMLS_EN</name> 7126 <description>ROM Light Sleep Mode.</description> 7127 <bitOffset>29</bitOffset> 7128 <bitWidth>1</bitWidth> 7129 </field> 7130 </fields> 7131 </register> 7132 <register> 7133 <name>MEMZ</name> 7134 <description>Memory Zeroize Control.</description> 7135 <addressOffset>0x2C</addressOffset> 7136 <fields> 7137 <field> 7138 <name>RAM0</name> 7139 <description>System RAM Block 0.</description> 7140 <bitOffset>0</bitOffset> 7141 <bitWidth>1</bitWidth> 7142 <enumeratedValues> 7143 <enumeratedValue> 7144 <name>nop</name> 7145 <description>No operation/complete.</description> 7146 <value>0</value> 7147 </enumeratedValue> 7148 <enumeratedValue> 7149 <name>start</name> 7150 <description>Start operation.</description> 7151 <value>1</value> 7152 </enumeratedValue> 7153 </enumeratedValues> 7154 </field> 7155 <field derivedFrom="RAM0"> 7156 <name>RAM1</name> 7157 <description>System RAM Block 1.</description> 7158 <bitOffset>1</bitOffset> 7159 <bitWidth>1</bitWidth> 7160 </field> 7161 <field derivedFrom="RAM0"> 7162 <name>RAM2</name> 7163 <description>System RAM Block 2.</description> 7164 <bitOffset>2</bitOffset> 7165 <bitWidth>1</bitWidth> 7166 </field> 7167 <field derivedFrom="RAM0"> 7168 <name>RAM3</name> 7169 <description>System RAM Block 3.</description> 7170 <bitOffset>3</bitOffset> 7171 <bitWidth>1</bitWidth> 7172 </field> 7173 <field derivedFrom="RAM0"> 7174 <name>RAM4</name> 7175 <description>System RAM Block 4.</description> 7176 <bitOffset>4</bitOffset> 7177 <bitWidth>1</bitWidth> 7178 </field> 7179 <field derivedFrom="RAM0"> 7180 <name>RAM5</name> 7181 <description>System RAM Block 5.</description> 7182 <bitOffset>5</bitOffset> 7183 <bitWidth>1</bitWidth> 7184 </field> 7185 <field derivedFrom="RAM0"> 7186 <name>RAM6</name> 7187 <description>System RAM Block 6.</description> 7188 <bitOffset>6</bitOffset> 7189 <bitWidth>1</bitWidth> 7190 </field> 7191 <field derivedFrom="RAM0"> 7192 <name>ICC0</name> 7193 <description>Instruction Cache.</description> 7194 <bitOffset>8</bitOffset> 7195 <bitWidth>1</bitWidth> 7196 </field> 7197 <field derivedFrom="RAM0"> 7198 <name>ICCXIP</name> 7199 <description>Instruction Cache XIP Data and Tag Ram zeroizatoin.</description> 7200 <bitOffset>9</bitOffset> 7201 <bitWidth>1</bitWidth> 7202 </field> 7203 <field derivedFrom="RAM0"> 7204 <name>SCACHEDATA</name> 7205 <description>System Cache Data Ram Zeroization.</description> 7206 <bitOffset>10</bitOffset> 7207 <bitWidth>1</bitWidth> 7208 </field> 7209 <field derivedFrom="RAM0"> 7210 <name>SCACHETAG</name> 7211 <description>System Cache Tag Zeroization.</description> 7212 <bitOffset>11</bitOffset> 7213 <bitWidth>1</bitWidth> 7214 </field> 7215 <field derivedFrom="RAM0"> 7216 <name>CRYPTO</name> 7217 <description>Crypto (MAA) Memory.</description> 7218 <bitOffset>12</bitOffset> 7219 <bitWidth>1</bitWidth> 7220 </field> 7221 <field derivedFrom="RAM0"> 7222 <name>USBFIFO</name> 7223 <description>USB FIFO Zeroization.</description> 7224 <bitOffset>13</bitOffset> 7225 <bitWidth>1</bitWidth> 7226 </field> 7227 </fields> 7228 </register> 7229 <register> 7230 <name>SCCK</name> 7231 <description>Smart Card Clock Control.</description> 7232 <addressOffset>0x34</addressOffset> 7233 <resetValue>0x00000000</resetValue> 7234 <fields> 7235 <field> 7236 <name>SC0CD</name> 7237 <description>Smart Card0 Clock Divider</description> 7238 <bitOffset>0</bitOffset> 7239 <bitWidth>6</bitWidth> 7240 </field> 7241 <field> 7242 <name>SC1CD</name> 7243 <description>Smart Card1 Clock Divider</description> 7244 <bitOffset>8</bitOffset> 7245 <bitWidth>6</bitWidth> 7246 </field> 7247 </fields> 7248 </register> 7249 <register> 7250 <name>SYSST</name> 7251 <description>System Status Register.</description> 7252 <addressOffset>0x40</addressOffset> 7253 <fields> 7254 <field> 7255 <name>ICELOCK</name> 7256 <description>ARM ICE Lock Status.</description> 7257 <bitOffset>0</bitOffset> 7258 <bitWidth>1</bitWidth> 7259 <enumeratedValues> 7260 <enumeratedValue> 7261 <name>unlocked</name> 7262 <description>ICE is unlocked.</description> 7263 <value>0</value> 7264 </enumeratedValue> 7265 <enumeratedValue> 7266 <name>locked</name> 7267 <description>ICE is locked.</description> 7268 <value>1</value> 7269 </enumeratedValue> 7270 </enumeratedValues> 7271 </field> 7272 <field> 7273 <name>CODEINTERR</name> 7274 <description>Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. </description> 7275 <bitOffset>1</bitOffset> 7276 <bitWidth>1</bitWidth> 7277 <enumeratedValues> 7278 <enumeratedValue> 7279 <name>norm</name> 7280 <description>Normal Operating Condition.</description> 7281 <value>0</value> 7282 </enumeratedValue> 7283 <enumeratedValue> 7284 <name>code</name> 7285 <description>Code Integrity Error.</description> 7286 <value>1</value> 7287 </enumeratedValue> 7288 </enumeratedValues> 7289 </field> 7290 <field> 7291 <name>SCMEMF</name> 7292 <description>System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.</description> 7293 <bitOffset>5</bitOffset> 7294 <bitWidth>1</bitWidth> 7295 <enumeratedValues> 7296 <enumeratedValue> 7297 <name>norm</name> 7298 <description>Normal Operating Condition.</description> 7299 <value>0</value> 7300 </enumeratedValue> 7301 <enumeratedValue> 7302 <name>memory</name> 7303 <description>Memory Fault.</description> 7304 <value>1</value> 7305 </enumeratedValue> 7306 </enumeratedValues> 7307 </field> 7308 </fields> 7309 </register> 7310 <register> 7311 <name>RST1</name> 7312 <description>Reset 1.</description> 7313 <addressOffset>0x44</addressOffset> 7314 <fields> 7315 <field> 7316 <name>I2C1</name> 7317 <description>I2C1 Reset.</description> 7318 <bitOffset>0</bitOffset> 7319 <bitWidth>1</bitWidth> 7320 </field> 7321 <field derivedFrom="I2C1"> 7322 <name>PT</name> 7323 <description>PT Reset.</description> 7324 <bitOffset>1</bitOffset> 7325 <bitWidth>1</bitWidth> 7326 </field> 7327 <field derivedFrom="I2C1"> 7328 <name>SPIXIP</name> 7329 <description>SPI XiP Master Reset.</description> 7330 <bitOffset>3</bitOffset> 7331 <bitWidth>1</bitWidth> 7332 </field> 7333 <field derivedFrom="I2C1"> 7334 <name>XSPIM</name> 7335 <description>GSPI XiP Master Controller Reset.</description> 7336 <bitOffset>4</bitOffset> 7337 <bitWidth>1</bitWidth> 7338 </field> 7339 <field derivedFrom="I2C1"> 7340 <name>GPIO3</name> 7341 <description>GPIO3 Reset.</description> 7342 <bitOffset>5</bitOffset> 7343 <bitWidth>1</bitWidth> 7344 </field> 7345 <field derivedFrom="I2C1"> 7346 <name>SDHC</name> 7347 <description>SDHC/SDIO Reset.</description> 7348 <bitOffset>6</bitOffset> 7349 <bitWidth>1</bitWidth> 7350 </field> 7351 <field derivedFrom="I2C1"> 7352 <name>OWIRE</name> 7353 <description>OWIRE Reset.</description> 7354 <bitOffset>7</bitOffset> 7355 <bitWidth>1</bitWidth> 7356 </field> 7357 <field derivedFrom="I2C1"> 7358 <name>WDT1</name> 7359 <description>WDT1 Reset.</description> 7360 <bitOffset>8</bitOffset> 7361 <bitWidth>1</bitWidth> 7362 </field> 7363 <field derivedFrom="I2C1"> 7364 <name>SPI3</name> 7365 <description>SPI3 Reset.</description> 7366 <bitOffset>9</bitOffset> 7367 <bitWidth>1</bitWidth> 7368 </field> 7369 <field derivedFrom="I2C1"> 7370 <name>AC</name> 7371 <description>AC Reset.</description> 7372 <bitOffset>14</bitOffset> 7373 <bitWidth>1</bitWidth> 7374 </field> 7375 <field derivedFrom="I2C1"> 7376 <name>SPIXMEM</name> 7377 <description>SPIXMEM Reset.</description> 7378 <bitOffset>15</bitOffset> 7379 <bitWidth>1</bitWidth> 7380 </field> 7381 <field derivedFrom="I2C1"> 7382 <name>I2C2</name> 7383 <description>I2C2 Reset.</description> 7384 <bitOffset>17</bitOffset> 7385 <bitWidth>1</bitWidth> 7386 </field> 7387 <field derivedFrom="I2C1"> 7388 <name>UART3</name> 7389 <description>UART3 Reset.</description> 7390 <bitOffset>18</bitOffset> 7391 <bitWidth>1</bitWidth> 7392 </field> 7393 <field derivedFrom="I2C1"> 7394 <name>UART4</name> 7395 <description>UART4 Reset.</description> 7396 <bitOffset>19</bitOffset> 7397 <bitWidth>1</bitWidth> 7398 </field> 7399 <field derivedFrom="I2C1"> 7400 <name>UART5</name> 7401 <description>UART5 Reset.</description> 7402 <bitOffset>20</bitOffset> 7403 <bitWidth>1</bitWidth> 7404 </field> 7405 <field derivedFrom="I2C1"> 7406 <name>KBD</name> 7407 <description>KBD Reset.</description> 7408 <bitOffset>21</bitOffset> 7409 <bitWidth>1</bitWidth> 7410 </field> 7411 <field derivedFrom="I2C1"> 7412 <name>ADC9</name> 7413 <description>ADC9 Reset.</description> 7414 <bitOffset>22</bitOffset> 7415 <bitWidth>1</bitWidth> 7416 </field> 7417 <field derivedFrom="I2C1"> 7418 <name>SC0</name> 7419 <description>SC0 Reset.</description> 7420 <bitOffset>23</bitOffset> 7421 <bitWidth>1</bitWidth> 7422 </field> 7423 <field derivedFrom="I2C1"> 7424 <name>SC1</name> 7425 <description>SC1 Reset.</description> 7426 <bitOffset>24</bitOffset> 7427 <bitWidth>1</bitWidth> 7428 </field> 7429 <field derivedFrom="I2C1"> 7430 <name>NFC</name> 7431 <description>NFC Reset.</description> 7432 <bitOffset>25</bitOffset> 7433 <bitWidth>1</bitWidth> 7434 </field> 7435 <field derivedFrom="I2C1"> 7436 <name>EMAC</name> 7437 <description>EMAC Reset.</description> 7438 <bitOffset>26</bitOffset> 7439 <bitWidth>1</bitWidth> 7440 </field> 7441 <field derivedFrom="I2C1"> 7442 <name>PCIF</name> 7443 <description>PCIF Reset.</description> 7444 <bitOffset>27</bitOffset> 7445 <bitWidth>1</bitWidth> 7446 </field> 7447 <field derivedFrom="I2C1"> 7448 <name>HTMR0</name> 7449 <description>HTIMER0 Reset.</description> 7450 <bitOffset>28</bitOffset> 7451 <bitWidth>1</bitWidth> 7452 </field> 7453 <field derivedFrom="I2C1"> 7454 <name>HTMR1</name> 7455 <description>HTIMER1 Reset.</description> 7456 <bitOffset>29</bitOffset> 7457 <bitWidth>1</bitWidth> 7458 </field> 7459 </fields> 7460 </register> 7461 <register> 7462 <name>PCLKDIS1</name> 7463 <description>Peripheral Clock Disable.</description> 7464 <addressOffset>0x48</addressOffset> 7465 <fields> 7466 <field> 7467 <name>UART2</name> 7468 <description>UART2 Disable.</description> 7469 <bitOffset>1</bitOffset> 7470 <bitWidth>1</bitWidth> 7471 <enumeratedValues> 7472 <enumeratedValue> 7473 <name>en</name> 7474 <description>Enable.</description> 7475 <value>0</value> 7476 </enumeratedValue> 7477 <enumeratedValue> 7478 <name>dis</name> 7479 <description>Disable.</description> 7480 <value>1</value> 7481 </enumeratedValue> 7482 </enumeratedValues> 7483 </field> 7484 <field derivedFrom="UART2"> 7485 <name>TRNG</name> 7486 <description>TRNG Disable.</description> 7487 <bitOffset>2</bitOffset> 7488 <bitWidth>1</bitWidth> 7489 </field> 7490 <field derivedFrom="UART2"> 7491 <name>WDT0</name> 7492 <description>WDT0 Clock Disable</description> 7493 <bitOffset>4</bitOffset> 7494 <bitWidth>1</bitWidth> 7495 </field> 7496 <field derivedFrom="UART2"> 7497 <name>WDT1</name> 7498 <description>WDT1 Clock Disable</description> 7499 <bitOffset>5</bitOffset> 7500 <bitWidth>1</bitWidth> 7501 </field> 7502 <field derivedFrom="UART2"> 7503 <name>GPIO3</name> 7504 <description>GPIO3 Disable</description> 7505 <bitOffset>6</bitOffset> 7506 <bitWidth>1</bitWidth> 7507 </field> 7508 <field derivedFrom="UART2"> 7509 <name>SCACHE</name> 7510 <description>System Cache Clock Disable.</description> 7511 <bitOffset>7</bitOffset> 7512 <bitWidth>1</bitWidth> 7513 </field> 7514 <field derivedFrom="UART2"> 7515 <name>HA0</name> 7516 <description>Hardware Accelerator 0 Clock Disable.</description> 7517 <bitOffset>8</bitOffset> 7518 <bitWidth>1</bitWidth> 7519 </field> 7520 <field derivedFrom="UART2"> 7521 <name>SDHC</name> 7522 <description>SDHC/SDIO Clock Disable.</description> 7523 <bitOffset>10</bitOffset> 7524 <bitWidth>1</bitWidth> 7525 </field> 7526 <field derivedFrom="UART2"> 7527 <name>ICC0</name> 7528 <description>ICache Clock Disable. </description> 7529 <bitOffset>11</bitOffset> 7530 <bitWidth>1</bitWidth> 7531 </field> 7532 <field derivedFrom="UART2"> 7533 <name>ICCXIP</name> 7534 <description>ICache XIP Clock Disable.</description> 7535 <bitOffset>12</bitOffset> 7536 <bitWidth>1</bitWidth> 7537 </field> 7538 <field derivedFrom="UART2"> 7539 <name>OWIRE</name> 7540 <description>One-Wire Clock Disable.</description> 7541 <bitOffset>13</bitOffset> 7542 <bitWidth>1</bitWidth> 7543 </field> 7544 <field derivedFrom="UART2"> 7545 <name>SPI3</name> 7546 <description>SPI3 Clock Disable.</description> 7547 <bitOffset>14</bitOffset> 7548 <bitWidth>1</bitWidth> 7549 </field> 7550 <field derivedFrom="UART2"> 7551 <name>SPIXIP</name> 7552 <description>SPI-XIP Data Clock Disable</description> 7553 <bitOffset>20</bitOffset> 7554 <bitWidth>1</bitWidth> 7555 </field> 7556 <field derivedFrom="UART2"> 7557 <name>I2C2</name> 7558 <description>I2C2 Clock Disable</description> 7559 <bitOffset>21</bitOffset> 7560 <bitWidth>1</bitWidth> 7561 </field> 7562 <field derivedFrom="UART2"> 7563 <name>UART3</name> 7564 <description>UART3 Clock Disable</description> 7565 <bitOffset>22</bitOffset> 7566 <bitWidth>1</bitWidth> 7567 </field> 7568 <field derivedFrom="UART2"> 7569 <name>UART4</name> 7570 <description>UART4 Clock Disable</description> 7571 <bitOffset>23</bitOffset> 7572 <bitWidth>1</bitWidth> 7573 </field> 7574 <field derivedFrom="UART2"> 7575 <name>UART5</name> 7576 <description>UART5 Clock Disable</description> 7577 <bitOffset>24</bitOffset> 7578 <bitWidth>1</bitWidth> 7579 </field> 7580 <field derivedFrom="UART2"> 7581 <name>ADC9</name> 7582 <description>ADC9 Clock Disable</description> 7583 <bitOffset>25</bitOffset> 7584 <bitWidth>1</bitWidth> 7585 </field> 7586 <field derivedFrom="UART2"> 7587 <name>SC0</name> 7588 <description>SC0 Clock Disable</description> 7589 <bitOffset>26</bitOffset> 7590 <bitWidth>1</bitWidth> 7591 </field> 7592 <field derivedFrom="UART2"> 7593 <name>SC1</name> 7594 <description>SC1 Clock Disable</description> 7595 <bitOffset>27</bitOffset> 7596 <bitWidth>1</bitWidth> 7597 </field> 7598 <field derivedFrom="UART2"> 7599 <name>NFC</name> 7600 <description>NFC Clock Disable</description> 7601 <bitOffset>28</bitOffset> 7602 <bitWidth>1</bitWidth> 7603 </field> 7604 <field derivedFrom="UART2"> 7605 <name>EMAC</name> 7606 <description>EMAC Clock Disable</description> 7607 <bitOffset>29</bitOffset> 7608 <bitWidth>1</bitWidth> 7609 </field> 7610 <field derivedFrom="UART2"> 7611 <name>HA1</name> 7612 <description>Hardware Accelerator 1 Clock Disable</description> 7613 <bitOffset>30</bitOffset> 7614 <bitWidth>1</bitWidth> 7615 </field> 7616 <field derivedFrom="UART2"> 7617 <name>PCIF</name> 7618 <description>PCIF Clock Disable</description> 7619 <bitOffset>31</bitOffset> 7620 <bitWidth>1</bitWidth> 7621 </field> 7622 </fields> 7623 </register> 7624 <register> 7625 <name>EVENTEN</name> 7626 <description>Event Enable Register.</description> 7627 <addressOffset>0x4C</addressOffset> 7628 <fields> 7629 <field> 7630 <name>DMA</name> 7631 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 7632 <bitOffset>0</bitOffset> 7633 <bitWidth>1</bitWidth> 7634 </field> 7635 <field> 7636 <name>RX</name> 7637 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 7638 <bitOffset>1</bitOffset> 7639 <bitWidth>1</bitWidth> 7640 </field> 7641 <field> 7642 <name>TX</name> 7643 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].</description> 7644 <bitOffset>2</bitOffset> 7645 <bitWidth>1</bitWidth> 7646 </field> 7647 </fields> 7648 </register> 7649 <register> 7650 <name>REVISION</name> 7651 <description>Revision Register.</description> 7652 <addressOffset>0x50</addressOffset> 7653 <access>read-only</access> 7654 <fields> 7655 <field> 7656 <name>REVISION</name> 7657 <description>Manufacturer Chip Revision. </description> 7658 <bitOffset>0</bitOffset> 7659 <bitWidth>16</bitWidth> 7660 </field> 7661 </fields> 7662 </register> 7663 <register> 7664 <name>SYSIE</name> 7665 <description>System Status Interrupt Enable Register.</description> 7666 <addressOffset>0x54</addressOffset> 7667 <fields> 7668 <field> 7669 <name>ICEUNLOCK</name> 7670 <description>ARM ICE Unlock Interrupt Enable.</description> 7671 <bitOffset>0</bitOffset> 7672 <bitWidth>1</bitWidth> 7673 <enumeratedValues> 7674 <enumeratedValue> 7675 <name>dis</name> 7676 <description>disabled.</description> 7677 <value>0</value> 7678 </enumeratedValue> 7679 <enumeratedValue> 7680 <name>en</name> 7681 <description>enabled.</description> 7682 <value>1</value> 7683 </enumeratedValue> 7684 </enumeratedValues> 7685 </field> 7686 <field derivedFrom="ICEUNLOCK"> 7687 <name>CIE</name> 7688 <description>Code Integrity Error Interrupt Enable.</description> 7689 <bitOffset>1</bitOffset> 7690 <bitWidth>1</bitWidth> 7691 </field> 7692 <field derivedFrom="ICEUNLOCK"> 7693 <name>SCMF</name> 7694 <description>System Cache Memory Fault Interrupt Enable.</description> 7695 <bitOffset>5</bitOffset> 7696 <bitWidth>1</bitWidth> 7697 </field> 7698 </fields> 7699 </register> 7700 <register> 7701 <name>IPOCNT</name> 7702 <description>IPO Warmup Count Register.</description> 7703 <addressOffset>0x58</addressOffset> 7704 <fields> 7705 <field> 7706 <name>WMUPCNT</name> 7707 <description>TBD</description> 7708 <bitOffset>0</bitOffset> 7709 <bitWidth>10</bitWidth> 7710 </field> 7711 </fields> 7712 </register> 7713 <register> 7714 <name>ECCERR</name> 7715 <description>ECC Error Register</description> 7716 <addressOffset>0x64</addressOffset> 7717 <fields> 7718 <field> 7719 <name>RAM0</name> 7720 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 7721 <bitOffset>0</bitOffset> 7722 <bitWidth>1</bitWidth> 7723 </field> 7724 <field> 7725 <name>RAM1</name> 7726 <description>ECC System RAM1 Error Flag. Write 1 to clear.</description> 7727 <bitOffset>1</bitOffset> 7728 <bitWidth>1</bitWidth> 7729 </field> 7730 <field> 7731 <name>RAM2</name> 7732 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 7733 <bitOffset>2</bitOffset> 7734 <bitWidth>1</bitWidth> 7735 </field> 7736 <field> 7737 <name>RAM3</name> 7738 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 7739 <bitOffset>3</bitOffset> 7740 <bitWidth>1</bitWidth> 7741 </field> 7742 <field> 7743 <name>RAM4</name> 7744 <description>ECC System RAM4 Error Flag. Write 1 to clear.</description> 7745 <bitOffset>4</bitOffset> 7746 <bitWidth>1</bitWidth> 7747 </field> 7748 <field> 7749 <name>RAM5</name> 7750 <description>ECC System RAM5 Error Flag. Write 1 to clear.</description> 7751 <bitOffset>5</bitOffset> 7752 <bitWidth>1</bitWidth> 7753 </field> 7754 <field> 7755 <name>ICC0</name> 7756 <description>ECC Icache0 Error Flag. Write 1 to clear.</description> 7757 <bitOffset>8</bitOffset> 7758 <bitWidth>1</bitWidth> 7759 </field> 7760 <field> 7761 <name>ICSPIXF</name> 7762 <description>ECC SFCC Instruction Cache Error Flag. Write 1 to clear.</description> 7763 <bitOffset>10</bitOffset> 7764 <bitWidth>1</bitWidth> 7765 </field> 7766 <field> 7767 <name>FLASH0</name> 7768 <description>ECC Flash0 Error Flag. Write 1 to clear.</description> 7769 <bitOffset>11</bitOffset> 7770 <bitWidth>1</bitWidth> 7771 </field> 7772 <field> 7773 <name>FLASH1</name> 7774 <description>ECC Flash1 Error Flag. Write 1 to clear.</description> 7775 <bitOffset>12</bitOffset> 7776 <bitWidth>1</bitWidth> 7777 </field> 7778 </fields> 7779 </register> 7780 <register> 7781 <name>ECCCED</name> 7782 <description>ECC Not Double Error Detect Register</description> 7783 <addressOffset>0x68</addressOffset> 7784 <fields> 7785 <field> 7786 <name>RAM0</name> 7787 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 7788 <bitOffset>0</bitOffset> 7789 <bitWidth>1</bitWidth> 7790 </field> 7791 <field> 7792 <name>RAM1</name> 7793 <description>ECC System RAM1 Not Double Error Detect. Write 1 to clear.</description> 7794 <bitOffset>1</bitOffset> 7795 <bitWidth>1</bitWidth> 7796 </field> 7797 <field> 7798 <name>RAM2</name> 7799 <description>ECC System RAM2 Not Double Error Detect. Write 1 to clear.</description> 7800 <bitOffset>2</bitOffset> 7801 <bitWidth>1</bitWidth> 7802 </field> 7803 <field> 7804 <name>RAM3</name> 7805 <description>ECC System RAM3 Not Double Error Detect. Write 1 to clear.</description> 7806 <bitOffset>3</bitOffset> 7807 <bitWidth>1</bitWidth> 7808 </field> 7809 <field> 7810 <name>RAM4</name> 7811 <description>ECC System RAM4 Not Double Error Detect. Write 1 to clear.</description> 7812 <bitOffset>4</bitOffset> 7813 <bitWidth>1</bitWidth> 7814 </field> 7815 <field> 7816 <name>RAM5</name> 7817 <description>ECC System RAM5 Not Double Error Detect. Write 1 to clear.</description> 7818 <bitOffset>5</bitOffset> 7819 <bitWidth>1</bitWidth> 7820 </field> 7821 <field> 7822 <name>ICC0</name> 7823 <description>ECC Icache0 Not Double Error Detect. Write 1 to clear.</description> 7824 <bitOffset>8</bitOffset> 7825 <bitWidth>1</bitWidth> 7826 </field> 7827 <field> 7828 <name>ICSPIXF</name> 7829 <description>ECC IcacheXIP Not Double Error Detect. Write 1 to clear.</description> 7830 <bitOffset>10</bitOffset> 7831 <bitWidth>1</bitWidth> 7832 </field> 7833 <field> 7834 <name>FLASH0</name> 7835 <description>ECC Flash0 Not Double Error Detect. Write 1 to clear.</description> 7836 <bitOffset>11</bitOffset> 7837 <bitWidth>1</bitWidth> 7838 </field> 7839 <field> 7840 <name>FLASH1</name> 7841 <description>ECC Flash1 Not Double Error Detect. Write 1 to clear.</description> 7842 <bitOffset>12</bitOffset> 7843 <bitWidth>1</bitWidth> 7844 </field> 7845 </fields> 7846 </register> 7847 <register> 7848 <name>ECCIE</name> 7849 <description>ECC IRQ Enable Register</description> 7850 <addressOffset>0x6C</addressOffset> 7851 <fields> 7852 <field> 7853 <name>RAM0</name> 7854 <description>ECC System RAM0 Interrupt Enable.</description> 7855 <bitOffset>0</bitOffset> 7856 <bitWidth>1</bitWidth> 7857 </field> 7858 <field> 7859 <name>RAM1</name> 7860 <description>ECC System RAM1 Interrupt Enable.</description> 7861 <bitOffset>1</bitOffset> 7862 <bitWidth>1</bitWidth> 7863 </field> 7864 <field> 7865 <name>RAM2</name> 7866 <description>ECC System RAM2 Interrupt Enable.</description> 7867 <bitOffset>2</bitOffset> 7868 <bitWidth>1</bitWidth> 7869 </field> 7870 <field> 7871 <name>RAM3</name> 7872 <description>ECC System RAM3 Interrupt Enable.</description> 7873 <bitOffset>3</bitOffset> 7874 <bitWidth>1</bitWidth> 7875 </field> 7876 <field> 7877 <name>RAM4</name> 7878 <description>ECC System RAM4 Interrupt Enable.</description> 7879 <bitOffset>4</bitOffset> 7880 <bitWidth>1</bitWidth> 7881 </field> 7882 <field> 7883 <name>RAM5</name> 7884 <description>ECC System RAM5 Interrupt Enable.</description> 7885 <bitOffset>5</bitOffset> 7886 <bitWidth>1</bitWidth> 7887 </field> 7888 <field> 7889 <name>ICC0</name> 7890 <description>ECC Icache0 Interrupt Enable.</description> 7891 <bitOffset>8</bitOffset> 7892 <bitWidth>1</bitWidth> 7893 </field> 7894 <field> 7895 <name>ICSPIXF</name> 7896 <description>ECC IcacheXIP Interrupt Enable.</description> 7897 <bitOffset>10</bitOffset> 7898 <bitWidth>1</bitWidth> 7899 </field> 7900 <field> 7901 <name>FLASH0</name> 7902 <description>ECC Flash0 Interrupt Enable.</description> 7903 <bitOffset>11</bitOffset> 7904 <bitWidth>1</bitWidth> 7905 </field> 7906 <field> 7907 <name>FLASH1</name> 7908 <description>ECC Flash1 Interrupt Enable.</description> 7909 <bitOffset>12</bitOffset> 7910 <bitWidth>1</bitWidth> 7911 </field> 7912 </fields> 7913 </register> 7914 <register> 7915 <name>ECCADDR</name> 7916 <description>ECC Error Address Register</description> 7917 <addressOffset>0x70</addressOffset> 7918 <fields> 7919 <field> 7920 <name>DATARAMADDR</name> 7921 <description>ECC Error Address/DATA RAM Error Address</description> 7922 <bitOffset>0</bitOffset> 7923 <bitWidth>14</bitWidth> 7924 </field> 7925 <field> 7926 <name>DATARAMBANK</name> 7927 <description>ECC Error Address/DATA RAM Error Bank</description> 7928 <bitOffset>14</bitOffset> 7929 <bitWidth>1</bitWidth> 7930 </field> 7931 <field> 7932 <name>DATARAMERR</name> 7933 <description>DATA RAM ERROR</description> 7934 <bitOffset>15</bitOffset> 7935 <bitWidth>1</bitWidth> 7936 </field> 7937 <field> 7938 <name>TAGRAMADDR</name> 7939 <description>ECC Error Address/TAG RAM Error Address</description> 7940 <bitOffset>16</bitOffset> 7941 <bitWidth>14</bitWidth> 7942 </field> 7943 <field> 7944 <name>TAGRAMBANK</name> 7945 <description>ECC Error Address/TAG RAM Error Bank</description> 7946 <bitOffset>30</bitOffset> 7947 <bitWidth>1</bitWidth> 7948 </field> 7949 <field> 7950 <name>TAGRAMERR</name> 7951 <description>TAG RAM ERROR</description> 7952 <bitOffset>31</bitOffset> 7953 <bitWidth>1</bitWidth> 7954 </field> 7955 </fields> 7956 </register> 7957 <register> 7958 <name>NFC_LDOCR</name> 7959 <description>NFC LDO Control Register</description> 7960 <addressOffset>0x74</addressOffset> 7961 <fields> 7962 <field> 7963 <name>EN</name> 7964 <description>Enabled the dedicated NFC LDO</description> 7965 <bitOffset>4</bitOffset> 7966 <bitWidth>1</bitWidth> 7967 </field> 7968 <field> 7969 <name>PULLD</name> 7970 <description>Enabled the dedicated NFC LDO pin pulldown</description> 7971 <bitOffset>5</bitOffset> 7972 <bitWidth>1</bitWidth> 7973 </field> 7974 <field> 7975 <name>VSEL</name> 7976 <description>Voltage Selection for NFC LDO</description> 7977 <bitOffset>6</bitOffset> 7978 <bitWidth>2</bitWidth> 7979 </field> 7980 <field> 7981 <name>BYPEN</name> 7982 <description>Bypass enable</description> 7983 <bitOffset>8</bitOffset> 7984 <bitWidth>1</bitWidth> 7985 </field> 7986 <field> 7987 <name>DISCH</name> 7988 <description>TBD</description> 7989 <bitOffset>9</bitOffset> 7990 <bitWidth>1</bitWidth> 7991 </field> 7992 <field> 7993 <name>EN_DLY</name> 7994 <description>TBD</description> 7995 <bitOffset>15</bitOffset> 7996 <bitWidth>1</bitWidth> 7997 </field> 7998 <field> 7999 <name>BYP_EN_DLY</name> 8000 <description>TBD</description> 8001 <bitOffset>14</bitOffset> 8002 <bitWidth>1</bitWidth> 8003 </field> 8004 </fields> 8005 </register> 8006 <register> 8007 <name>NFCLDO_DLY</name> 8008 <description>NFC LDO Delay Register</description> 8009 <addressOffset>0x78</addressOffset> 8010 <fields> 8011 <field> 8012 <name>BYPCNT</name> 8013 <description>TBD</description> 8014 <bitOffset>0</bitOffset> 8015 <bitWidth>8</bitWidth> 8016 </field> 8017 <field> 8018 <name>ENCNT</name> 8019 <description>TBD</description> 8020 <bitOffset>8</bitOffset> 8021 <bitWidth>8</bitWidth> 8022 </field> 8023 </fields> 8024 </register> 8025 </registers> 8026 </peripheral> 8027<!--GCR Global Control Registers.--> 8028 <peripheral> 8029 <name>GPIO0</name> 8030 <description>Individual I/O for each GPIO</description> 8031 <groupName>GPIO</groupName> 8032 <baseAddress>0x40008000</baseAddress> 8033 <addressBlock> 8034 <offset>0x00</offset> 8035 <size>0x1000</size> 8036 <usage>registers</usage> 8037 </addressBlock> 8038 <interrupt> 8039 <name>GPIO0</name> 8040 <description>GPIO0 interrupt.</description> 8041 <value>24</value> 8042 </interrupt> 8043 <registers> 8044 <register> 8045 <name>EN0</name> 8046 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 8047 <addressOffset>0x00</addressOffset> 8048 <fields> 8049 <field> 8050 <name>GPIO_EN</name> 8051 <description>Mask of all of the pins on the port.</description> 8052 <bitOffset>0</bitOffset> 8053 <bitWidth>32</bitWidth> 8054 <enumeratedValues> 8055 <enumeratedValue> 8056 <name>ALTERNATE</name> 8057 <description>Alternate function enabled.</description> 8058 <value>0</value> 8059 </enumeratedValue> 8060 <enumeratedValue> 8061 <name>GPIO</name> 8062 <description>GPIO function is enabled.</description> 8063 <value>1</value> 8064 </enumeratedValue> 8065 </enumeratedValues> 8066 </field> 8067 </fields> 8068 </register> 8069 <register> 8070 <name>EN0_SET</name> 8071 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 8072 <addressOffset>0x04</addressOffset> 8073 <fields> 8074 <field> 8075 <name>ALL</name> 8076 <description>Mask of all of the pins on the port.</description> 8077 <bitOffset>0</bitOffset> 8078 <bitWidth>32</bitWidth> 8079 </field> 8080 </fields> 8081 </register> 8082 <register> 8083 <name>EN0_CLR</name> 8084 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 8085 <addressOffset>0x08</addressOffset> 8086 <fields> 8087 <field> 8088 <name>ALL</name> 8089 <description>Mask of all of the pins on the port.</description> 8090 <bitOffset>0</bitOffset> 8091 <bitWidth>32</bitWidth> 8092 </field> 8093 </fields> 8094 </register> 8095 <register> 8096 <name>OUT_EN</name> 8097 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 8098 <addressOffset>0x0C</addressOffset> 8099 <fields> 8100 <field> 8101 <name>GPIO_OUT_EN</name> 8102 <description>Mask of all of the pins on the port.</description> 8103 <bitOffset>0</bitOffset> 8104 <bitWidth>32</bitWidth> 8105 <enumeratedValues> 8106 <enumeratedValue> 8107 <name>dis</name> 8108 <description>GPIO Output Disable</description> 8109 <value>0</value> 8110 </enumeratedValue> 8111 <enumeratedValue> 8112 <name>en</name> 8113 <description>GPIO Output Enable</description> 8114 <value>1</value> 8115 </enumeratedValue> 8116 </enumeratedValues> 8117 </field> 8118 </fields> 8119 </register> 8120 <register> 8121 <name>OUT_EN_SET</name> 8122 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 8123 <addressOffset>0x10</addressOffset> 8124 <fields> 8125 <field> 8126 <name>ALL</name> 8127 <description>Mask of all of the pins on the port.</description> 8128 <bitOffset>0</bitOffset> 8129 <bitWidth>32</bitWidth> 8130 </field> 8131 </fields> 8132 </register> 8133 <register> 8134 <name>OUT_EN_CLR</name> 8135 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 8136 <addressOffset>0x14</addressOffset> 8137 <fields> 8138 <field> 8139 <name>ALL</name> 8140 <description>Mask of all of the pins on the port.</description> 8141 <bitOffset>0</bitOffset> 8142 <bitWidth>32</bitWidth> 8143 </field> 8144 </fields> 8145 </register> 8146 <register> 8147 <name>OUT</name> 8148 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 8149 <addressOffset>0x18</addressOffset> 8150 <fields> 8151 <field> 8152 <name>GPIO_OUT</name> 8153 <description>Mask of all of the pins on the port.</description> 8154 <bitOffset>0</bitOffset> 8155 <bitWidth>32</bitWidth> 8156 <enumeratedValues> 8157 <enumeratedValue> 8158 <name>low</name> 8159 <description>Drive Logic 0 (low) on GPIO output.</description> 8160 <value>0</value> 8161 </enumeratedValue> 8162 <enumeratedValue> 8163 <name>high</name> 8164 <description>Drive logic 1 (high) on GPIO output.</description> 8165 <value>1</value> 8166 </enumeratedValue> 8167 </enumeratedValues> 8168 </field> 8169 </fields> 8170 </register> 8171 <register> 8172 <name>OUT_SET</name> 8173 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 8174 <addressOffset>0x1C</addressOffset> 8175 <access>write-only</access> 8176 <fields> 8177 <field> 8178 <name>GPIO_OUT_SET</name> 8179 <description>Mask of all of the pins on the port.</description> 8180 <bitOffset>0</bitOffset> 8181 <bitWidth>32</bitWidth> 8182 <enumeratedValues> 8183 <enumeratedValue> 8184 <name>no</name> 8185 <description>No Effect.</description> 8186 <value>0</value> 8187 </enumeratedValue> 8188 <enumeratedValue> 8189 <name>set</name> 8190 <description>Set GPIO_OUT bit in this position to '1'</description> 8191 <value>1</value> 8192 </enumeratedValue> 8193 </enumeratedValues> 8194 </field> 8195 </fields> 8196 </register> 8197 <register> 8198 <name>OUT_CLR</name> 8199 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 8200 <addressOffset>0x20</addressOffset> 8201 <access>write-only</access> 8202 <fields> 8203 <field> 8204 <name>GPIO_OUT_CLR</name> 8205 <description>Mask of all of the pins on the port.</description> 8206 <bitOffset>0</bitOffset> 8207 <bitWidth>32</bitWidth> 8208 </field> 8209 </fields> 8210 </register> 8211 <register> 8212 <name>IN</name> 8213 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 8214 <addressOffset>0x24</addressOffset> 8215 <access>read-only</access> 8216 <fields> 8217 <field> 8218 <name>GPIO_IN</name> 8219 <description>Mask of all of the pins on the port.</description> 8220 <bitOffset>0</bitOffset> 8221 <bitWidth>32</bitWidth> 8222 </field> 8223 </fields> 8224 </register> 8225 <register> 8226 <name>INT_MODE</name> 8227 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 8228 <addressOffset>0x28</addressOffset> 8229 <fields> 8230 <field> 8231 <name>GPIO_INT_MODE</name> 8232 <description>Mask of all of the pins on the port.</description> 8233 <bitOffset>0</bitOffset> 8234 <bitWidth>32</bitWidth> 8235 <enumeratedValues> 8236 <enumeratedValue> 8237 <name>level</name> 8238 <description>Interrupts for this pin are level triggered.</description> 8239 <value>0</value> 8240 </enumeratedValue> 8241 <enumeratedValue> 8242 <name>edge</name> 8243 <description>Interrupts for this pin are edge triggered.</description> 8244 <value>1</value> 8245 </enumeratedValue> 8246 </enumeratedValues> 8247 </field> 8248 </fields> 8249 </register> 8250 <register> 8251 <name>INT_POL</name> 8252 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 8253 <addressOffset>0x2C</addressOffset> 8254 <fields> 8255 <field> 8256 <name>GPIO_INT_POL</name> 8257 <description>Mask of all of the pins on the port.</description> 8258 <bitOffset>0</bitOffset> 8259 <bitWidth>32</bitWidth> 8260 <enumeratedValues> 8261 <enumeratedValue> 8262 <name>falling</name> 8263 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 8264 <value>0</value> 8265 </enumeratedValue> 8266 <enumeratedValue> 8267 <name>rising</name> 8268 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 8269 <value>1</value> 8270 </enumeratedValue> 8271 </enumeratedValues> 8272 </field> 8273 </fields> 8274 </register> 8275 <register> 8276 <name>IN_EN</name> 8277 <description>GPIO Input Enable</description> 8278 <addressOffset>0x30</addressOffset> 8279 </register> 8280 <register> 8281 <name>INT_EN</name> 8282 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 8283 <addressOffset>0x34</addressOffset> 8284 <fields> 8285 <field> 8286 <name>GPIO_INT_EN</name> 8287 <description>Mask of all of the pins on the port.</description> 8288 <bitOffset>0</bitOffset> 8289 <bitWidth>32</bitWidth> 8290 <enumeratedValues> 8291 <enumeratedValue> 8292 <name>dis</name> 8293 <description>Interrupts are disabled for this GPIO pin.</description> 8294 <value>0</value> 8295 </enumeratedValue> 8296 <enumeratedValue> 8297 <name>en</name> 8298 <description>Interrupts are enabled for this GPIO pin.</description> 8299 <value>1</value> 8300 </enumeratedValue> 8301 </enumeratedValues> 8302 </field> 8303 </fields> 8304 </register> 8305 <register> 8306 <name>INT_EN_SET</name> 8307 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 8308 <addressOffset>0x38</addressOffset> 8309 <fields> 8310 <field> 8311 <name>GPIO_INT_EN_SET</name> 8312 <description>Mask of all of the pins on the port.</description> 8313 <bitOffset>0</bitOffset> 8314 <bitWidth>32</bitWidth> 8315 <enumeratedValues> 8316 <enumeratedValue> 8317 <name>no</name> 8318 <description>No effect.</description> 8319 <value>0</value> 8320 </enumeratedValue> 8321 <enumeratedValue> 8322 <name>set</name> 8323 <description>Set GPIO_INT_EN bit in this position to '1'</description> 8324 <value>1</value> 8325 </enumeratedValue> 8326 </enumeratedValues> 8327 </field> 8328 </fields> 8329 </register> 8330 <register> 8331 <name>INT_EN_CLR</name> 8332 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 8333 <addressOffset>0x3C</addressOffset> 8334 <fields> 8335 <field> 8336 <name>GPIO_INT_EN_CLR</name> 8337 <description>Mask of all of the pins on the port.</description> 8338 <bitOffset>0</bitOffset> 8339 <bitWidth>32</bitWidth> 8340 <enumeratedValues> 8341 <enumeratedValue> 8342 <name>no</name> 8343 <description>No Effect.</description> 8344 <value>0</value> 8345 </enumeratedValue> 8346 <enumeratedValue> 8347 <name>clear</name> 8348 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 8349 <value>1</value> 8350 </enumeratedValue> 8351 </enumeratedValues> 8352 </field> 8353 </fields> 8354 </register> 8355 <register> 8356 <name>INT_STAT</name> 8357 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 8358 <addressOffset>0x40</addressOffset> 8359 <access>read-only</access> 8360 <fields> 8361 <field> 8362 <name>GPIO_INT_STAT</name> 8363 <description>Mask of all of the pins on the port.</description> 8364 <bitOffset>0</bitOffset> 8365 <bitWidth>32</bitWidth> 8366 <enumeratedValues> 8367 <enumeratedValue> 8368 <name>no</name> 8369 <description>No Interrupt is pending on this GPIO pin.</description> 8370 <value>0</value> 8371 </enumeratedValue> 8372 <enumeratedValue> 8373 <name>pending</name> 8374 <description>An Interrupt is pending on this GPIO pin.</description> 8375 <value>1</value> 8376 </enumeratedValue> 8377 </enumeratedValues> 8378 </field> 8379 </fields> 8380 </register> 8381 <register> 8382 <name>INT_CLR</name> 8383 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 8384 <addressOffset>0x48</addressOffset> 8385 <fields> 8386 <field> 8387 <name>ALL</name> 8388 <description>Mask of all of the pins on the port.</description> 8389 <bitOffset>0</bitOffset> 8390 <bitWidth>32</bitWidth> 8391 </field> 8392 </fields> 8393 </register> 8394 <register> 8395 <name>WAKE_EN</name> 8396 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 8397 <addressOffset>0x4C</addressOffset> 8398 <fields> 8399 <field> 8400 <name>GPIO_WAKE_EN</name> 8401 <description>Mask of all of the pins on the port.</description> 8402 <bitOffset>0</bitOffset> 8403 <bitWidth>32</bitWidth> 8404 <enumeratedValues> 8405 <enumeratedValue> 8406 <name>dis</name> 8407 <description>PMU wakeup for this GPIO is disabled.</description> 8408 <value>0</value> 8409 </enumeratedValue> 8410 <enumeratedValue> 8411 <name>en</name> 8412 <description>PMU wakeup for this GPIO is enabled.</description> 8413 <value>1</value> 8414 </enumeratedValue> 8415 </enumeratedValues> 8416 </field> 8417 </fields> 8418 </register> 8419 <register> 8420 <name>WAKE_EN_SET</name> 8421 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 8422 <addressOffset>0x50</addressOffset> 8423 <fields> 8424 <field> 8425 <name>ALL</name> 8426 <description>Mask of all of the pins on the port.</description> 8427 <bitOffset>0</bitOffset> 8428 <bitWidth>32</bitWidth> 8429 </field> 8430 </fields> 8431 </register> 8432 <register> 8433 <name>WAKE_EN_CLR</name> 8434 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 8435 <addressOffset>0x54</addressOffset> 8436 <fields> 8437 <field> 8438 <name>ALL</name> 8439 <description>Mask of all of the pins on the port.</description> 8440 <bitOffset>0</bitOffset> 8441 <bitWidth>32</bitWidth> 8442 </field> 8443 </fields> 8444 </register> 8445 <register> 8446 <name>INT_DUAL_EDGE</name> 8447 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 8448 <addressOffset>0x5C</addressOffset> 8449 <fields> 8450 <field> 8451 <name>GPIO_INT_DUAL_EDGE</name> 8452 <description>Mask of all of the pins on the port.</description> 8453 <bitOffset>0</bitOffset> 8454 <bitWidth>32</bitWidth> 8455 <enumeratedValues> 8456 <enumeratedValue> 8457 <name>no</name> 8458 <description>No Effect.</description> 8459 <value>0</value> 8460 </enumeratedValue> 8461 <enumeratedValue> 8462 <name>en</name> 8463 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 8464 <value>1</value> 8465 </enumeratedValue> 8466 </enumeratedValues> 8467 </field> 8468 </fields> 8469 </register> 8470 <register> 8471 <name>PAD_CFG1</name> 8472 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 8473 <addressOffset>0x60</addressOffset> 8474 <fields> 8475 <field> 8476 <name>GPIO_PAD_CFG1</name> 8477 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 8478 <bitOffset>0</bitOffset> 8479 <bitWidth>32</bitWidth> 8480 <enumeratedValues> 8481 <enumeratedValue> 8482 <name>impedance</name> 8483 <description>High Impedance.</description> 8484 <value>0</value> 8485 </enumeratedValue> 8486 <enumeratedValue> 8487 <name>pu</name> 8488 <description>Weak pull-up mode.</description> 8489 <value>1</value> 8490 </enumeratedValue> 8491 <enumeratedValue> 8492 <name>pd</name> 8493 <description>weak pull-down mode.</description> 8494 <value>2</value> 8495 </enumeratedValue> 8496 </enumeratedValues> 8497 </field> 8498 </fields> 8499 </register> 8500 <register> 8501 <name>PAD_CFG2</name> 8502 <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 8503 <addressOffset>0x64</addressOffset> 8504 <fields> 8505 <field> 8506 <name>GPIO_PAD_CFG2</name> 8507 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 8508 <bitOffset>0</bitOffset> 8509 <bitWidth>32</bitWidth> 8510 <enumeratedValues> 8511 <enumeratedValue> 8512 <name>impedance</name> 8513 <description>High Impedance.</description> 8514 <value>0</value> 8515 </enumeratedValue> 8516 <enumeratedValue> 8517 <name>pu</name> 8518 <description>Weak pull-up mode.</description> 8519 <value>1</value> 8520 </enumeratedValue> 8521 <enumeratedValue> 8522 <name>pd</name> 8523 <description>weak pull-down mode.</description> 8524 <value>2</value> 8525 </enumeratedValue> 8526 </enumeratedValues> 8527 </field> 8528 </fields> 8529 </register> 8530 <register> 8531 <name>EN1</name> 8532 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 8533 <addressOffset>0x68</addressOffset> 8534 <fields> 8535 <field> 8536 <name>GPIO_EN1</name> 8537 <description>Mask of all of the pins on the port.</description> 8538 <bitOffset>0</bitOffset> 8539 <bitWidth>32</bitWidth> 8540 <enumeratedValues> 8541 <enumeratedValue> 8542 <name>primary</name> 8543 <description>Primary function selected.</description> 8544 <value>0</value> 8545 </enumeratedValue> 8546 <enumeratedValue> 8547 <name>secondary</name> 8548 <description>Secondary function selected.</description> 8549 <value>1</value> 8550 </enumeratedValue> 8551 </enumeratedValues> 8552 </field> 8553 </fields> 8554 </register> 8555 <register> 8556 <name>EN1_SET</name> 8557 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 8558 <addressOffset>0x6C</addressOffset> 8559 <fields> 8560 <field> 8561 <name>ALL</name> 8562 <description>Mask of all of the pins on the port.</description> 8563 <bitOffset>0</bitOffset> 8564 <bitWidth>32</bitWidth> 8565 </field> 8566 </fields> 8567 </register> 8568 <register> 8569 <name>EN1_CLR</name> 8570 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 8571 <addressOffset>0x70</addressOffset> 8572 <fields> 8573 <field> 8574 <name>ALL</name> 8575 <description>Mask of all of the pins on the port.</description> 8576 <bitOffset>0</bitOffset> 8577 <bitWidth>32</bitWidth> 8578 </field> 8579 </fields> 8580 </register> 8581 <register> 8582 <name>EN2</name> 8583 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 8584 <addressOffset>0x74</addressOffset> 8585 <fields> 8586 <field> 8587 <name>GPIO_EN2</name> 8588 <description>Mask of all of the pins on the port.</description> 8589 <bitOffset>0</bitOffset> 8590 <bitWidth>32</bitWidth> 8591 <enumeratedValues> 8592 <enumeratedValue> 8593 <name>primary</name> 8594 <description>Primary function selected.</description> 8595 <value>0</value> 8596 </enumeratedValue> 8597 <enumeratedValue> 8598 <name>secondary</name> 8599 <description>Secondary function selected.</description> 8600 <value>1</value> 8601 </enumeratedValue> 8602 </enumeratedValues> 8603 </field> 8604 </fields> 8605 </register> 8606 <register> 8607 <name>EN2_SET</name> 8608 <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description> 8609 <addressOffset>0x78</addressOffset> 8610 <fields> 8611 <field> 8612 <name>ALL</name> 8613 <description>Mask of all of the pins on the port.</description> 8614 <bitOffset>0</bitOffset> 8615 <bitWidth>32</bitWidth> 8616 </field> 8617 </fields> 8618 </register> 8619 <register> 8620 <name>EN2_CLR</name> 8621 <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description> 8622 <addressOffset>0x7C</addressOffset> 8623 <fields> 8624 <field> 8625 <name>ALL</name> 8626 <description>Mask of all of the pins on the port.</description> 8627 <bitOffset>0</bitOffset> 8628 <bitWidth>32</bitWidth> 8629 </field> 8630 </fields> 8631 </register> 8632 <register> 8633 <name>DS</name> 8634 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 8635 <addressOffset>0xB0</addressOffset> 8636 <fields> 8637 <field> 8638 <name>GPIO_DS</name> 8639 <description>Mask of all of the pins on the port.</description> 8640 <bitOffset>0</bitOffset> 8641 <bitWidth>32</bitWidth> 8642 <enumeratedValues> 8643 <enumeratedValue> 8644 <name>ld</name> 8645 <description>GPIO port pin is in low-drive mode.</description> 8646 <value>0</value> 8647 </enumeratedValue> 8648 <enumeratedValue> 8649 <name>hd</name> 8650 <description>GPIO port pin is in high-drive mode.</description> 8651 <value>1</value> 8652 </enumeratedValue> 8653 </enumeratedValues> 8654 </field> 8655 </fields> 8656 </register> 8657 <register> 8658 <name>DS1</name> 8659 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 8660 <addressOffset>0xB4</addressOffset> 8661 <fields> 8662 <field> 8663 <name>GPIO_DS1</name> 8664 <description>Mask of all of the pins on the port.</description> 8665 <bitOffset>0</bitOffset> 8666 <bitWidth>32</bitWidth> 8667 </field> 8668 </fields> 8669 </register> 8670 <register> 8671 <name>PS</name> 8672 <description>GPIO Pull Select Mode.</description> 8673 <addressOffset>0xB8</addressOffset> 8674 <fields> 8675 <field> 8676 <name>ALL</name> 8677 <description>Mask of all of the pins on the port.</description> 8678 <bitOffset>0</bitOffset> 8679 <bitWidth>32</bitWidth> 8680 </field> 8681 </fields> 8682 </register> 8683 <register> 8684 <name>VSSEL</name> 8685 <description>GPIO Voltage Select.</description> 8686 <addressOffset>0xC0</addressOffset> 8687 <fields> 8688 <field> 8689 <name>ALL</name> 8690 <description>Mask of all of the pins on the port.</description> 8691 <bitOffset>0</bitOffset> 8692 <bitWidth>32</bitWidth> 8693 </field> 8694 </fields> 8695 </register> 8696 </registers> 8697 </peripheral> 8698<!--GPIO0 Individual I/O for each GPIO--> 8699 <peripheral derivedFrom="GPIO0"> 8700 <name>GPIO1</name> 8701 <description>Individual I/O for each GPIO 1</description> 8702 <baseAddress>0x40009000</baseAddress> 8703 <interrupt> 8704 <name>GPIO1</name> 8705 <description>GPIO1 IRQ</description> 8706 <value>25</value> 8707 </interrupt> 8708 </peripheral> 8709<!--GPIO1 Individual I/O for each GPIO 1--> 8710 <peripheral derivedFrom="GPIO0"> 8711 <name>GPIO2</name> 8712 <description>Individual I/O for each GPIO 2</description> 8713 <baseAddress>0x4000A000</baseAddress> 8714 <interrupt> 8715 <name>GPIO2</name> 8716 <description>GPIO2 IRQ</description> 8717 <value>26</value> 8718 </interrupt> 8719 </peripheral> 8720<!--GPIO2 Individual I/O for each GPIO 2--> 8721 <peripheral derivedFrom="GPIO0"> 8722 <name>GPIO3</name> 8723 <description>Individual I/O for each GPIO 3</description> 8724 <baseAddress>0x4000B000</baseAddress> 8725 <interrupt> 8726 <name>GPIO3</name> 8727 <description>GPIO3 IRQ</description> 8728 <value>58</value> 8729 </interrupt> 8730 </peripheral> 8731<!--GPIO3 Individual I/O for each GPIO 3--> 8732 <peripheral> 8733 <name>HA</name> 8734 <description>Hardware Accelerator</description> 8735 <baseAddress>0x40036000</baseAddress> 8736 <addressBlock> 8737 <offset>0x00</offset> 8738 <size>0x1000</size> 8739 <usage>registers</usage> 8740 </addressBlock> 8741 <interrupt> 8742 <name>HA</name> 8743 <description>Smart DMA interrupt.</description> 8744 <value>60</value> 8745 </interrupt> 8746 <registers> 8747 <register> 8748 <name>IP</name> 8749 <description>Q30E Instruction Pointer.</description> 8750 <addressOffset>0x00</addressOffset> 8751 <access>read-only</access> 8752 </register> 8753 <register> 8754 <name>SP</name> 8755 <description>Q30E Stack Pointer.</description> 8756 <addressOffset>0x04</addressOffset> 8757 <access>read-only</access> 8758 </register> 8759 <register> 8760 <name>DP0</name> 8761 <description>Q30E Data Pointer 0.</description> 8762 <addressOffset>0x08</addressOffset> 8763 <access>read-only</access> 8764 </register> 8765 <register> 8766 <name>DP1</name> 8767 <description>Q30E Data Pointer 1.</description> 8768 <addressOffset>0x0C</addressOffset> 8769 <access>read-only</access> 8770 </register> 8771 <register> 8772 <name>BP</name> 8773 <description>Q30E Frame Pointer Base.</description> 8774 <addressOffset>0x10</addressOffset> 8775 <access>read-only</access> 8776 </register> 8777 <register> 8778 <name>OFFS</name> 8779 <description>Q30E Frame Pointer Offset.</description> 8780 <addressOffset>0x14</addressOffset> 8781 <access>read-only</access> 8782 </register> 8783 <register> 8784 <name>LC0</name> 8785 <description>Q30E Loop Counter 0.</description> 8786 <addressOffset>0x18</addressOffset> 8787 <access>read-only</access> 8788 </register> 8789 <register> 8790 <name>LC1</name> 8791 <description>Q30E Loop Counter 1.</description> 8792 <addressOffset>0x1C</addressOffset> 8793 <access>read-only</access> 8794 </register> 8795 <register> 8796 <name>A0</name> 8797 <description>Q30E Accumulator 0.</description> 8798 <addressOffset>0x20</addressOffset> 8799 <access>read-only</access> 8800 </register> 8801 <register> 8802 <name>A1</name> 8803 <description>Q30E Accumulator 1.</description> 8804 <addressOffset>0x24</addressOffset> 8805 <access>read-only</access> 8806 </register> 8807 <register> 8808 <name>A2</name> 8809 <description>Q30E Accumulator 2.</description> 8810 <addressOffset>0x28</addressOffset> 8811 <access>read-only</access> 8812 </register> 8813 <register> 8814 <name>A3</name> 8815 <description>Q30E Accumulator 3.</description> 8816 <addressOffset>0x2C</addressOffset> 8817 <access>read-only</access> 8818 </register> 8819 <register> 8820 <name>WDCN</name> 8821 <description>Q30E Watchdog Control.</description> 8822 <addressOffset>0x30</addressOffset> 8823 <access>read-only</access> 8824 </register> 8825 <register> 8826 <name>INT_MUX_CTRL0</name> 8827 <description>Interrupt Mux Control 0.</description> 8828 <addressOffset>0x80</addressOffset> 8829 <access>read-write</access> 8830 <fields> 8831 <field> 8832 <name>INTSEL16</name> 8833 <description>Interrupt Selection For 16th Interrupt.</description> 8834 <bitOffset>0</bitOffset> 8835 <bitWidth>8</bitWidth> 8836 </field> 8837 <field> 8838 <name>INTSEL17</name> 8839 <description>Interrupt Selection For 17th Interrupt.</description> 8840 <bitOffset>8</bitOffset> 8841 <bitWidth>8</bitWidth> 8842 </field> 8843 <field> 8844 <name>INTSEL18</name> 8845 <description>Interrupt Selection For 18th Interrupt.</description> 8846 <bitOffset>16</bitOffset> 8847 <bitWidth>8</bitWidth> 8848 </field> 8849 <field> 8850 <name>INTSEL19</name> 8851 <description>Interrupt Selection For 19th Interrupt.</description> 8852 <bitOffset>24</bitOffset> 8853 <bitWidth>8</bitWidth> 8854 </field> 8855 </fields> 8856 </register> 8857 <register> 8858 <name>INT_MUX_CTRL1</name> 8859 <description>Interrupt Mux Control 1.</description> 8860 <addressOffset>0x84</addressOffset> 8861 <access>read-write</access> 8862 <fields> 8863 <field> 8864 <name>INTSEL20</name> 8865 <description>Interrupt Selection For 20th Interrupt.</description> 8866 <bitOffset>0</bitOffset> 8867 <bitWidth>8</bitWidth> 8868 </field> 8869 <field> 8870 <name>INTSEL21</name> 8871 <description>Interrupt Selection For 21st Interrupt.</description> 8872 <bitOffset>8</bitOffset> 8873 <bitWidth>8</bitWidth> 8874 </field> 8875 <field> 8876 <name>INTSEL22</name> 8877 <description>Interrupt Selection For 22nd Interrupt.</description> 8878 <bitOffset>16</bitOffset> 8879 <bitWidth>8</bitWidth> 8880 </field> 8881 <field> 8882 <name>INTSEL23</name> 8883 <description>Interrupt Selection For 23rd Interrupt.</description> 8884 <bitOffset>24</bitOffset> 8885 <bitWidth>8</bitWidth> 8886 </field> 8887 </fields> 8888 </register> 8889 <register> 8890 <name>INT_MUX_CTRL2</name> 8891 <description>Interrupt Mux Control 2.</description> 8892 <addressOffset>0x88</addressOffset> 8893 <access>read-write</access> 8894 <fields> 8895 <field> 8896 <name>INTSEL24</name> 8897 <description>Interrupt Selection For 24th Interrupt.</description> 8898 <bitOffset>0</bitOffset> 8899 <bitWidth>8</bitWidth> 8900 </field> 8901 <field> 8902 <name>INTSEL25</name> 8903 <description>Interrupt Selection For 25th Interrupt.</description> 8904 <bitOffset>8</bitOffset> 8905 <bitWidth>8</bitWidth> 8906 </field> 8907 <field> 8908 <name>INTSEL26</name> 8909 <description>Interrupt Selection For 26th Interrupt.</description> 8910 <bitOffset>16</bitOffset> 8911 <bitWidth>8</bitWidth> 8912 </field> 8913 <field> 8914 <name>INTSEL27</name> 8915 <description>Interrupt Selection For 27th Interrupt.</description> 8916 <bitOffset>24</bitOffset> 8917 <bitWidth>8</bitWidth> 8918 </field> 8919 </fields> 8920 </register> 8921 <register> 8922 <name>INT_MUX_CTRL3</name> 8923 <description>Interrupt Mux Control 3.</description> 8924 <addressOffset>0x8C</addressOffset> 8925 <access>read-write</access> 8926 <fields> 8927 <field> 8928 <name>INTSEL28</name> 8929 <description>Interrupt Selection For 28th Interrupt.</description> 8930 <bitOffset>0</bitOffset> 8931 <bitWidth>8</bitWidth> 8932 </field> 8933 <field> 8934 <name>INTSEL29</name> 8935 <description>Interrupt Selection For 29th Interrupt.</description> 8936 <bitOffset>8</bitOffset> 8937 <bitWidth>8</bitWidth> 8938 </field> 8939 <field> 8940 <name>INTSEL30</name> 8941 <description>Interrupt Selection For 30th Interrupt.</description> 8942 <bitOffset>16</bitOffset> 8943 <bitWidth>8</bitWidth> 8944 </field> 8945 <field> 8946 <name>INTSEL31</name> 8947 <description>Interrupt Selection For 31st Interrupt.</description> 8948 <bitOffset>24</bitOffset> 8949 <bitWidth>8</bitWidth> 8950 </field> 8951 </fields> 8952 </register> 8953 <register> 8954 <name>IP_ADDR</name> 8955 <description>Configurable starting IP address for Q30E.</description> 8956 <addressOffset>0x90</addressOffset> 8957 <access>read-write</access> 8958 <fields> 8959 <field> 8960 <name>START_IP_ADDR</name> 8961 <description>Starting IP address for Q30E</description> 8962 <bitOffset>0</bitOffset> 8963 <bitWidth>32</bitWidth> 8964 </field> 8965 </fields> 8966 </register> 8967 <register> 8968 <name>CTRL</name> 8969 <description>Control Register.</description> 8970 <addressOffset>0x94</addressOffset> 8971 <access>read-write</access> 8972 <fields> 8973 <field> 8974 <name>EN</name> 8975 <description>Enable SDMA.</description> 8976 <bitOffset>0</bitOffset> 8977 <bitWidth>1</bitWidth> 8978 <enumeratedValues> 8979 <enumeratedValue> 8980 <name>dis</name> 8981 <description>Disable SDMA.</description> 8982 <value>0</value> 8983 </enumeratedValue> 8984 <enumeratedValue> 8985 <name>en</name> 8986 <description>Enable SDMA.</description> 8987 <value>1</value> 8988 </enumeratedValue> 8989 </enumeratedValues> 8990 </field> 8991 </fields> 8992 </register> 8993 <register> 8994 <name>INT_IN_CTRL</name> 8995 <description>Interrupt Input From CPU Control Register.</description> 8996 <addressOffset>0xA0</addressOffset> 8997 <access>read-write</access> 8998 <fields> 8999 <field> 9000 <name>INTSET</name> 9001 <description>Set Interrupt Flag.</description> 9002 <bitOffset>0</bitOffset> 9003 <bitWidth>1</bitWidth> 9004 <enumeratedValues> 9005 <enumeratedValue> 9006 <name>dis</name> 9007 <description>Set interrupt Flag to 0.</description> 9008 <value>0</value> 9009 </enumeratedValue> 9010 <enumeratedValue> 9011 <name>set</name> 9012 <description>Set Interrupt Flag to 1.</description> 9013 <value>1</value> 9014 </enumeratedValue> 9015 </enumeratedValues> 9016 </field> 9017 </fields> 9018 </register> 9019 <register> 9020 <name>INT_IN_FLAG</name> 9021 <description>Interrupt Input From CPU Flag.</description> 9022 <addressOffset>0xA4</addressOffset> 9023 <access>read-write</access> 9024 <fields> 9025 <field> 9026 <name>INTFLAG</name> 9027 <description>Interrupt Flag.</description> 9028 <bitOffset>0</bitOffset> 9029 <bitWidth>1</bitWidth> 9030 <enumeratedValues> 9031 <enumeratedValue> 9032 <name>no_eff</name> 9033 <description>No Effect.</description> 9034 <value>0</value> 9035 </enumeratedValue> 9036 <enumeratedValue> 9037 <name>clear</name> 9038 <description>INT_IN_FLAG =0</description> 9039 <value>1</value> 9040 </enumeratedValue> 9041 </enumeratedValues> 9042 </field> 9043 </fields> 9044 </register> 9045 <register> 9046 <name>INT_IN_IE</name> 9047 <description>Interrupt Input From CPU Enable.</description> 9048 <addressOffset>0xA8</addressOffset> 9049 <access>read-write</access> 9050 <fields> 9051 <field> 9052 <name>INT_IN_EN</name> 9053 <description>Interrupt Enable.</description> 9054 <bitOffset>0</bitOffset> 9055 <bitWidth>1</bitWidth> 9056 </field> 9057 </fields> 9058 </register> 9059 <register> 9060 <name>IRQ_FLAG</name> 9061 <description>Interrupt Output To CPU Flag.</description> 9062 <addressOffset>0xB0</addressOffset> 9063 <access>read-write</access> 9064 <fields> 9065 <field> 9066 <name>IRQ_FLAG</name> 9067 <description>Interrupt Flag.</description> 9068 <bitOffset>0</bitOffset> 9069 <bitWidth>1</bitWidth> 9070 </field> 9071 </fields> 9072 </register> 9073 <register> 9074 <name>IRQ_IE</name> 9075 <description>Interrupt Output To CPU Control Register.</description> 9076 <addressOffset>0xB4</addressOffset> 9077 <access>read-write</access> 9078 <fields> 9079 <field> 9080 <name>IRQ_EN</name> 9081 <description>Interrupt Enable.</description> 9082 <bitOffset>0</bitOffset> 9083 <bitWidth>1</bitWidth> 9084 </field> 9085 </fields> 9086 </register> 9087 </registers> 9088 </peripheral> 9089<!--HA Hardware Accelerator--> 9090 <peripheral> 9091 <name>HTMR</name> 9092 <description>High Speed Timer Module.</description> 9093 <baseAddress>0x4001B000</baseAddress> 9094 <addressBlock> 9095 <offset>0x00</offset> 9096 <size>0xFFF</size> 9097 <usage>registers</usage> 9098 </addressBlock> 9099 <interrupt> 9100 <name>HTimer</name> 9101 <description>HTimer interrupt.</description> 9102 <value>93</value> 9103 </interrupt> 9104 <registers> 9105 <register> 9106 <name>SEC</name> 9107 <description>HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter.</description> 9108 <addressOffset>0x00</addressOffset> 9109 <resetMask>0x00000000</resetMask> 9110 <fields> 9111 <field> 9112 <name>RTS</name> 9113 <description>HTimer Long Interval Counter.</description> 9114 <bitOffset>0</bitOffset> 9115 <bitWidth>32</bitWidth> 9116 </field> 9117 </fields> 9118 </register> 9119 <register> 9120 <name>SSEC</name> 9121 <description>HTimer Short Interval Counter. This counter ticks every t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 9122 <addressOffset>0x04</addressOffset> 9123 <resetMask>0x00000000</resetMask> 9124 <fields> 9125 <field> 9126 <name>RTSS</name> 9127 <description>HTimer Short Interval Counter.</description> 9128 <bitOffset>0</bitOffset> 9129 <bitWidth>8</bitWidth> 9130 </field> 9131 </fields> 9132 </register> 9133 <register> 9134 <name>RAS</name> 9135 <description>Long Interval Alarm.</description> 9136 <addressOffset>0x08</addressOffset> 9137 <resetMask>0x00000000</resetMask> 9138 <fields> 9139 <field> 9140 <name>RAS</name> 9141 <description>HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0]</description> 9142 <bitOffset>0</bitOffset> 9143 <bitWidth>20</bitWidth> 9144 </field> 9145 </fields> 9146 </register> 9147 <register> 9148 <name>RSSA</name> 9149 <description>HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover.</description> 9150 <addressOffset>0x0C</addressOffset> 9151 <resetMask>0x00000000</resetMask> 9152 <fields> 9153 <field> 9154 <name>RSSA</name> 9155 <description>This register contains the reload value for the short interval alarm.</description> 9156 <bitOffset>0</bitOffset> 9157 <bitWidth>32</bitWidth> 9158 </field> 9159 </fields> 9160 </register> 9161 <register> 9162 <name>CTRL</name> 9163 <description>HTimer Control Register.</description> 9164 <addressOffset>0x10</addressOffset> 9165 <resetValue>0x00000008</resetValue> 9166 <resetMask>0xFFFFFF38</resetMask> 9167 <fields> 9168 <field> 9169 <name>HTEN</name> 9170 <description>HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 9171 <bitOffset>0</bitOffset> 9172 <bitWidth>1</bitWidth> 9173 <enumeratedValues> 9174 <enumeratedValue> 9175 <name>dis</name> 9176 <description>Disable.</description> 9177 <value>0</value> 9178 </enumeratedValue> 9179 <enumeratedValue> 9180 <name>en</name> 9181 <description>Enable.</description> 9182 <value>1</value> 9183 </enumeratedValue> 9184 </enumeratedValues> 9185 </field> 9186 <field> 9187 <name>ADE</name> 9188 <description>Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 9189 <bitOffset>1</bitOffset> 9190 <bitWidth>1</bitWidth> 9191 <enumeratedValues> 9192 <enumeratedValue> 9193 <name>dis</name> 9194 <description>Disable.</description> 9195 <value>0</value> 9196 </enumeratedValue> 9197 <enumeratedValue> 9198 <name>en</name> 9199 <description>Enable.</description> 9200 <value>1</value> 9201 </enumeratedValue> 9202 </enumeratedValues> 9203 </field> 9204 <field> 9205 <name>ASE</name> 9206 <description>Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 9207 <bitOffset>2</bitOffset> 9208 <bitWidth>1</bitWidth> 9209 <enumeratedValues> 9210 <enumeratedValue> 9211 <name>dis</name> 9212 <description>Disable.</description> 9213 <value>0</value> 9214 </enumeratedValue> 9215 <enumeratedValue> 9216 <name>en</name> 9217 <description>Enable.</description> 9218 <value>1</value> 9219 </enumeratedValue> 9220 </enumeratedValues> 9221 </field> 9222 <field> 9223 <name>BUSY</name> 9224 <description>HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 9225 <bitOffset>3</bitOffset> 9226 <bitWidth>1</bitWidth> 9227 <access>read-only</access> 9228 <enumeratedValues> 9229 <enumeratedValue> 9230 <name>idle</name> 9231 <description>Idle.</description> 9232 <value>0</value> 9233 </enumeratedValue> 9234 <enumeratedValue> 9235 <name>busy</name> 9236 <description>Busy.</description> 9237 <value>1</value> 9238 </enumeratedValue> 9239 </enumeratedValues> 9240 </field> 9241 <field> 9242 <name>RDY</name> 9243 <description>HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register.</description> 9244 <bitOffset>4</bitOffset> 9245 <bitWidth>1</bitWidth> 9246 <enumeratedValues> 9247 <enumeratedValue> 9248 <name>busy</name> 9249 <description>Register has not updated.</description> 9250 <value>0</value> 9251 </enumeratedValue> 9252 <enumeratedValue> 9253 <name>ready</name> 9254 <description>Ready.</description> 9255 <value>1</value> 9256 </enumeratedValue> 9257 </enumeratedValues> 9258 </field> 9259 <field> 9260 <name>RDYE</name> 9261 <description>HTimer Ready Interrupt Enable.</description> 9262 <bitOffset>5</bitOffset> 9263 <bitWidth>1</bitWidth> 9264 <enumeratedValues> 9265 <enumeratedValue> 9266 <name>dis</name> 9267 <description>Disable.</description> 9268 <value>0</value> 9269 </enumeratedValue> 9270 <enumeratedValue> 9271 <name>en</name> 9272 <description>Enable.</description> 9273 <value>1</value> 9274 </enumeratedValue> 9275 </enumeratedValues> 9276 </field> 9277 <field> 9278 <name>ALDF</name> 9279 <description>Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 9280 <bitOffset>6</bitOffset> 9281 <bitWidth>1</bitWidth> 9282 <access>read-only</access> 9283 <enumeratedValues> 9284 <enumeratedValue> 9285 <name>inactive</name> 9286 <description>Not active.</description> 9287 <value>0</value> 9288 </enumeratedValue> 9289 <enumeratedValue> 9290 <name>pending</name> 9291 <description>Active.</description> 9292 <value>1</value> 9293 </enumeratedValue> 9294 </enumeratedValues> 9295 </field> 9296 <field> 9297 <name>ALSF</name> 9298 <description>Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 9299 <bitOffset>7</bitOffset> 9300 <bitWidth>1</bitWidth> 9301 <access>read-only</access> 9302 <enumeratedValues> 9303 <enumeratedValue> 9304 <name>inactive</name> 9305 <description>Not active.</description> 9306 <value>0</value> 9307 </enumeratedValue> 9308 <enumeratedValue> 9309 <name>Pending</name> 9310 <description>Active.</description> 9311 <value>1</value> 9312 </enumeratedValue> 9313 </enumeratedValues> 9314 </field> 9315 <field> 9316 <name>WE</name> 9317 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits.</description> 9318 <bitOffset>15</bitOffset> 9319 <bitWidth>1</bitWidth> 9320 <enumeratedValues> 9321 <enumeratedValue> 9322 <name>dis</name> 9323 <description>Not active.</description> 9324 <value>0</value> 9325 </enumeratedValue> 9326 <enumeratedValue> 9327 <name>en</name> 9328 <description>.</description> 9329 <value>1</value> 9330 </enumeratedValue> 9331 </enumeratedValues> 9332 </field> 9333 </fields> 9334 </register> 9335 </registers> 9336 </peripheral> 9337<!--HTMR High Speed Timer Module.--> 9338 <peripheral derivedFrom="HTMR"> 9339 <name>HTMR1</name> 9340 <description>High Speed Timer Module. 1</description> 9341 <baseAddress>0x4001C000</baseAddress> 9342 <interrupt> 9343 <name>HTMR1</name> 9344 <description>HTMR1 IRQ</description> 9345 <value>94</value> 9346 </interrupt> 9347 </peripheral> 9348<!--HTMR1 High Speed Timer Module. 1--> 9349 <peripheral> 9350 <name>I2C0</name> 9351 <description>Inter-Integrated Circuit.</description> 9352 <groupName>I2C</groupName> 9353 <baseAddress>0x4001D000</baseAddress> 9354 <size>32</size> 9355 <addressBlock> 9356 <offset>0x00</offset> 9357 <size>0x1000</size> 9358 <usage>registers</usage> 9359 </addressBlock> 9360 <interrupt> 9361 <name>I2C0</name> 9362 <description>I2C0 IRQ</description> 9363 <value>13</value> 9364 </interrupt> 9365 <registers> 9366 <register> 9367 <name>CTRL</name> 9368 <description>Control Register0.</description> 9369 <addressOffset>0x00</addressOffset> 9370 <fields> 9371 <field> 9372 <name>I2C_EN</name> 9373 <description>I2C Enable.</description> 9374 <bitRange>[0:0]</bitRange> 9375 <access>read-write</access> 9376 <enumeratedValues> 9377 <enumeratedValue> 9378 <name>dis</name> 9379 <description>Disable I2C.</description> 9380 <value>0</value> 9381 </enumeratedValue> 9382 <enumeratedValue> 9383 <name>en</name> 9384 <description>Enable I2C.</description> 9385 <value>1</value> 9386 </enumeratedValue> 9387 </enumeratedValues> 9388 </field> 9389 <field> 9390 <name>MST</name> 9391 <description>Master Mode Enable.</description> 9392 <bitRange>[1:1]</bitRange> 9393 <access>read-write</access> 9394 <enumeratedValues> 9395 <enumeratedValue> 9396 <name>slave_mode</name> 9397 <description>Slave Mode.</description> 9398 <value>0</value> 9399 </enumeratedValue> 9400 <enumeratedValue> 9401 <name>master_mode</name> 9402 <description>Master Mode.</description> 9403 <value>1</value> 9404 </enumeratedValue> 9405 </enumeratedValues> 9406 </field> 9407 <field> 9408 <name>GEN_CALL_ADDR</name> 9409 <description>General Call Address Enable.</description> 9410 <bitRange>[2:2]</bitRange> 9411 <access>read-write</access> 9412 <enumeratedValues> 9413 <enumeratedValue> 9414 <name>dis</name> 9415 <description>Ignore Gneral Call Address.</description> 9416 <value>0</value> 9417 </enumeratedValue> 9418 <enumeratedValue> 9419 <name>en</name> 9420 <description>Acknowledge general call address.</description> 9421 <value>1</value> 9422 </enumeratedValue> 9423 </enumeratedValues> 9424 </field> 9425 <field> 9426 <name>RX_MODE</name> 9427 <description>Interactive Receive Mode.</description> 9428 <bitRange>[3:3]</bitRange> 9429 <access>read-write</access> 9430 <enumeratedValues> 9431 <enumeratedValue> 9432 <name>dis</name> 9433 <description>Disable Interactive Receive Mode.</description> 9434 <value>0</value> 9435 </enumeratedValue> 9436 <enumeratedValue> 9437 <name>en</name> 9438 <description>Enable Interactive Receive Mode.</description> 9439 <value>1</value> 9440 </enumeratedValue> 9441 </enumeratedValues> 9442 </field> 9443 <field> 9444 <name>RX_MODE_ACK</name> 9445 <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description> 9446 <bitRange>[4:4]</bitRange> 9447 <access>read-write</access> 9448 <enumeratedValues> 9449 <enumeratedValue> 9450 <name>ack</name> 9451 <description>return ACK (pulling SDA LOW).</description> 9452 <value>0</value> 9453 </enumeratedValue> 9454 <enumeratedValue> 9455 <name>nack</name> 9456 <description>return NACK (leaving SDA HIGH).</description> 9457 <value>1</value> 9458 </enumeratedValue> 9459 </enumeratedValues> 9460 </field> 9461 <field> 9462 <name>SCL_OUT</name> 9463 <description>SCL Output. This bits control SCL output when SWOE =1.</description> 9464 <bitRange>[6:6]</bitRange> 9465 <access>read-write</access> 9466 <enumeratedValues> 9467 <enumeratedValue> 9468 <name>drive_scl_low</name> 9469 <description>Drive SCL low. </description> 9470 <value>0</value> 9471 </enumeratedValue> 9472 <enumeratedValue> 9473 <name>release_scl</name> 9474 <description>Release SCL.</description> 9475 <value>1</value> 9476 </enumeratedValue> 9477 </enumeratedValues> 9478 </field> 9479 <field> 9480 <name>SDA_OUT</name> 9481 <description>SDA Output. This bits control SDA output when SWOE = 1. </description> 9482 <bitRange>[7:7]</bitRange> 9483 <access>read-write</access> 9484 <enumeratedValues> 9485 <enumeratedValue> 9486 <name>drive_sda_low</name> 9487 <description>Drive SDA low. </description> 9488 <value>0</value> 9489 </enumeratedValue> 9490 <enumeratedValue> 9491 <name>release_sda</name> 9492 <description>Release SDA.</description> 9493 <value>1</value> 9494 </enumeratedValue> 9495 </enumeratedValues> 9496 </field> 9497 <field> 9498 <name>SCL</name> 9499 <description>SCL status. This bit reflects the logic gate of SCL signal. </description> 9500 <bitRange>[8:8]</bitRange> 9501 <access>read-only</access> 9502 </field> 9503 <field> 9504 <name>SDA</name> 9505 <description>SDA status. THis bit reflects the logic gate of SDA signal.</description> 9506 <bitRange>[9:9]</bitRange> 9507 <access>read-only</access> 9508 </field> 9509 <field> 9510 <name>SW_OUT_EN</name> 9511 <description>Software Output Enable.</description> 9512 <bitRange>[10:10]</bitRange> 9513 <access>read-write</access> 9514 <enumeratedValues> 9515 <enumeratedValue> 9516 <name>outputs_disable</name> 9517 <description>I2C Outputs SCLO and SDAO disabled. </description> 9518 <value>0</value> 9519 </enumeratedValue> 9520 <enumeratedValue> 9521 <name>outputs_enable</name> 9522 <description>I2C Outputs SCLO and SDAO enabled.</description> 9523 <value>1</value> 9524 </enumeratedValue> 9525 </enumeratedValues> 9526 </field> 9527 <field> 9528 <name>READ</name> 9529 <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description> 9530 <bitRange>[11:11]</bitRange> 9531 <access>read-only</access> 9532 <enumeratedValues> 9533 <enumeratedValue> 9534 <name>write</name> 9535 <description>Write.</description> 9536 <value>0</value> 9537 </enumeratedValue> 9538 <enumeratedValue> 9539 <name>read</name> 9540 <description>Read.</description> 9541 <value>1</value> 9542 </enumeratedValue> 9543 </enumeratedValues> 9544 </field> 9545 <field> 9546 <name>SCL_CLK_STRETCH_DIS</name> 9547 <description>This bit will disable slave clock stretching when set.</description> 9548 <bitRange>[12:12]</bitRange> 9549 <access>read-write</access> 9550 <enumeratedValues> 9551 <enumeratedValue> 9552 <name>en</name> 9553 <description>Slave clock stretching enabled.</description> 9554 <value>0</value> 9555 </enumeratedValue> 9556 <enumeratedValue> 9557 <name>dis</name> 9558 <description>Slave clock stretching disabled.</description> 9559 <value>1</value> 9560 </enumeratedValue> 9561 </enumeratedValues> 9562 </field> 9563 <field> 9564 <name>SCL_PP_MODE</name> 9565 <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description> 9566 <bitRange>[13:13]</bitRange> 9567 <access>read-write</access> 9568 <enumeratedValues> 9569 <enumeratedValue> 9570 <name>dis</name> 9571 <description>Standard open-drain operation: 9572 drive low for 0, Hi-Z for 1</description> 9573 <value>0</value> 9574 </enumeratedValue> 9575 <enumeratedValue> 9576 <name>en</name> 9577 <description>Non-standard push-pull operation: 9578 drive low for 0, drive high for 1</description> 9579 <value>1</value> 9580 </enumeratedValue> 9581 </enumeratedValues> 9582 </field> 9583 </fields> 9584 </register> 9585 <register> 9586 <name>STATUS</name> 9587 <description>Status Register.</description> 9588 <addressOffset>0x04</addressOffset> 9589 <fields> 9590 <field> 9591 <name>BUS</name> 9592 <description>Bus Status.</description> 9593 <bitRange>[0:0]</bitRange> 9594 <access>read-only</access> 9595 <enumeratedValues> 9596 <enumeratedValue> 9597 <name>idle</name> 9598 <description>I2C Bus Idle.</description> 9599 <value>0</value> 9600 </enumeratedValue> 9601 <enumeratedValue> 9602 <name>busy</name> 9603 <description>I2C Bus Busy.</description> 9604 <value>1</value> 9605 </enumeratedValue> 9606 </enumeratedValues> 9607 </field> 9608 <field> 9609 <name>RX_EMPTY</name> 9610 <description>RX empty.</description> 9611 <bitRange>[1:1]</bitRange> 9612 <access>read-only</access> 9613 <enumeratedValues> 9614 <enumeratedValue> 9615 <name>not_empty</name> 9616 <description>Not Empty.</description> 9617 <value>0</value> 9618 </enumeratedValue> 9619 <enumeratedValue> 9620 <name>empty</name> 9621 <description>Empty.</description> 9622 <value>1</value> 9623 </enumeratedValue> 9624 </enumeratedValues> 9625 </field> 9626 <field> 9627 <name>RX_FULL</name> 9628 <description>RX Full.</description> 9629 <bitRange>[2:2]</bitRange> 9630 <access>read-only</access> 9631 <enumeratedValues> 9632 <enumeratedValue> 9633 <name>not_full</name> 9634 <description>Not Full.</description> 9635 <value>0</value> 9636 </enumeratedValue> 9637 <enumeratedValue> 9638 <name>full</name> 9639 <description>Full.</description> 9640 <value>1</value> 9641 </enumeratedValue> 9642 </enumeratedValues> 9643 </field> 9644 <field> 9645 <name>TX_EMPTY</name> 9646 <description>TX Empty.</description> 9647 <bitRange>[3:3]</bitRange> 9648 <enumeratedValues> 9649 <enumeratedValue> 9650 <name>not_empty</name> 9651 <description>Not Empty.</description> 9652 <value>0</value> 9653 </enumeratedValue> 9654 <enumeratedValue> 9655 <name>empty</name> 9656 <description>Empty.</description> 9657 <value>1</value> 9658 </enumeratedValue> 9659 </enumeratedValues> 9660 </field> 9661 <field> 9662 <name>TX_FULL</name> 9663 <description>TX Full.</description> 9664 <bitRange>[4:4]</bitRange> 9665 <enumeratedValues> 9666 <enumeratedValue> 9667 <name>not_empty</name> 9668 <description>Not Empty.</description> 9669 <value>0</value> 9670 </enumeratedValue> 9671 <enumeratedValue> 9672 <name>empty</name> 9673 <description>Empty.</description> 9674 <value>1</value> 9675 </enumeratedValue> 9676 </enumeratedValues> 9677 </field> 9678 <field> 9679 <name>CLK_MODE</name> 9680 <description>Clock Mode.</description> 9681 <bitRange>[5:5]</bitRange> 9682 <access>read-only</access> 9683 <enumeratedValues> 9684 <enumeratedValue> 9685 <name>not_actively_driving_scl_clock</name> 9686 <description>Device not actively driving SCL clock cycles.</description> 9687 <value>0</value> 9688 </enumeratedValue> 9689 <enumeratedValue> 9690 <name>actively_driving_scl_clock</name> 9691 <description>Device operating as master and actively driving SCL clock cycles.</description> 9692 <value>1</value> 9693 </enumeratedValue> 9694 </enumeratedValues> 9695 </field> 9696 </fields> 9697 </register> 9698 <register> 9699 <name>INT_FL0</name> 9700 <description>Interrupt Status Register.</description> 9701 <addressOffset>0x08</addressOffset> 9702 <fields> 9703 <field> 9704 <name>DONE</name> 9705 <description>Transfer Done Interrupt.</description> 9706 <bitRange>[0:0]</bitRange> 9707 <enumeratedValues> 9708 <enumeratedValue> 9709 <name>inactive</name> 9710 <description>No Interrupt is Pending.</description> 9711 <value>0</value> 9712 </enumeratedValue> 9713 <enumeratedValue> 9714 <name>pending</name> 9715 <description>An interrupt is pending.</description> 9716 <value>1</value> 9717 </enumeratedValue> 9718 </enumeratedValues> 9719 </field> 9720 <field> 9721 <name>RX_MODE</name> 9722 <description>Interactive Receive Interrupt.</description> 9723 <bitRange>[1:1]</bitRange> 9724 <enumeratedValues> 9725 <enumeratedValue> 9726 <name>inactive</name> 9727 <description>No Interrupt is Pending.</description> 9728 <value>0</value> 9729 </enumeratedValue> 9730 <enumeratedValue> 9731 <name>pending</name> 9732 <description>An interrupt is pending.</description> 9733 <value>1</value> 9734 </enumeratedValue> 9735 </enumeratedValues> 9736 </field> 9737 <field> 9738 <name>GEN_CALL_ADDR</name> 9739 <description>Slave General Call Address Match Interrupt.</description> 9740 <bitRange>[2:2]</bitRange> 9741 <enumeratedValues> 9742 <enumeratedValue> 9743 <name>inactive</name> 9744 <description>No Interrupt is Pending.</description> 9745 <value>0</value> 9746 </enumeratedValue> 9747 <enumeratedValue> 9748 <name>pending</name> 9749 <description>An interrupt is pending.</description> 9750 <value>1</value> 9751 </enumeratedValue> 9752 </enumeratedValues> 9753 </field> 9754 <field> 9755 <name>ADDR_MATCH</name> 9756 <description>Slave Address Match Interrupt.</description> 9757 <bitRange>[3:3]</bitRange> 9758 <enumeratedValues> 9759 <enumeratedValue> 9760 <name>inactive</name> 9761 <description>No Interrupt is Pending.</description> 9762 <value>0</value> 9763 </enumeratedValue> 9764 <enumeratedValue> 9765 <name>pending</name> 9766 <description>An interrupt is pending.</description> 9767 <value>1</value> 9768 </enumeratedValue> 9769 </enumeratedValues> 9770 </field> 9771 <field> 9772 <name>RX_THRESH</name> 9773 <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description> 9774 <bitRange>[4:4]</bitRange> 9775 <enumeratedValues> 9776 <enumeratedValue> 9777 <name>inactive</name> 9778 <description>No interrupt is pending.</description> 9779 <value>0</value> 9780 </enumeratedValue> 9781 <enumeratedValue> 9782 <name>pending</name> 9783 <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description> 9784 <value>1</value> 9785 </enumeratedValue> 9786 </enumeratedValues> 9787 </field> 9788 <field> 9789 <name>TX_THRESH</name> 9790 <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description> 9791 <bitRange>[5:5]</bitRange> 9792 <enumeratedValues> 9793 <enumeratedValue> 9794 <name>inactive</name> 9795 <description>No interrupt is pending.</description> 9796 <value>0</value> 9797 </enumeratedValue> 9798 <enumeratedValue> 9799 <name>pending</name> 9800 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 9801 <value>1</value> 9802 </enumeratedValue> 9803 </enumeratedValues> 9804 </field> 9805 <field> 9806 <name>STOP</name> 9807 <description>STOP Interrupt.</description> 9808 <bitRange>[6:6]</bitRange> 9809 <enumeratedValues> 9810 <enumeratedValue> 9811 <name>inactive</name> 9812 <description>No interrupt is pending.</description> 9813 <value>0</value> 9814 </enumeratedValue> 9815 <enumeratedValue> 9816 <name>pending</name> 9817 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 9818 <value>1</value> 9819 </enumeratedValue> 9820 </enumeratedValues> 9821 </field> 9822 <field> 9823 <name>ADDR_ACK</name> 9824 <description>Address Acknowledge Interrupt.</description> 9825 <bitRange>[7:7]</bitRange> 9826 <enumeratedValues> 9827 <enumeratedValue> 9828 <name>inactive</name> 9829 <description>No Interrupt is Pending.</description> 9830 <value>0</value> 9831 </enumeratedValue> 9832 <enumeratedValue> 9833 <name>pending</name> 9834 <description>An interrupt is pending.</description> 9835 <value>1</value> 9836 </enumeratedValue> 9837 </enumeratedValues> 9838 </field> 9839 <field> 9840 <name>ARB_ER</name> 9841 <description>Arbritation error Interrupt.</description> 9842 <bitRange>[8:8]</bitRange> 9843 <enumeratedValues> 9844 <enumeratedValue> 9845 <name>inactive</name> 9846 <description>No Interrupt is Pending.</description> 9847 <value>0</value> 9848 </enumeratedValue> 9849 <enumeratedValue> 9850 <name>pending</name> 9851 <description>An interrupt is pending.</description> 9852 <value>1</value> 9853 </enumeratedValue> 9854 </enumeratedValues> 9855 </field> 9856 <field> 9857 <name>TO_ER</name> 9858 <description>timeout Error Interrupt.</description> 9859 <bitRange>[9:9]</bitRange> 9860 <enumeratedValues> 9861 <enumeratedValue> 9862 <name>inactive</name> 9863 <description>No Interrupt is Pending.</description> 9864 <value>0</value> 9865 </enumeratedValue> 9866 <enumeratedValue> 9867 <name>pending</name> 9868 <description>An interrupt is pending.</description> 9869 <value>1</value> 9870 </enumeratedValue> 9871 </enumeratedValues> 9872 </field> 9873 <field> 9874 <name>ADDR_NACK_ER</name> 9875 <description>Address NACK Error Interrupt.</description> 9876 <bitRange>[10:10]</bitRange> 9877 <enumeratedValues> 9878 <enumeratedValue> 9879 <name>inactive</name> 9880 <description>No Interrupt is Pending.</description> 9881 <value>0</value> 9882 </enumeratedValue> 9883 <enumeratedValue> 9884 <name>pending</name> 9885 <description>An interrupt is pending.</description> 9886 <value>1</value> 9887 </enumeratedValue> 9888 </enumeratedValues> 9889 </field> 9890 <field> 9891 <name>DATA_ER</name> 9892 <description>Data NACK Error Interrupt.</description> 9893 <bitRange>[11:11]</bitRange> 9894 <enumeratedValues> 9895 <enumeratedValue> 9896 <name>inactive</name> 9897 <description>No Interrupt is Pending.</description> 9898 <value>0</value> 9899 </enumeratedValue> 9900 <enumeratedValue> 9901 <name>pending</name> 9902 <description>An interrupt is pending.</description> 9903 <value>1</value> 9904 </enumeratedValue> 9905 </enumeratedValues> 9906 </field> 9907 <field> 9908 <name>DO_NOT_RESP_ER</name> 9909 <description>Do Not Respond Error Interrupt.</description> 9910 <bitRange>[12:12]</bitRange> 9911 <enumeratedValues> 9912 <enumeratedValue> 9913 <name>inactive</name> 9914 <description>No Interrupt is Pending.</description> 9915 <value>0</value> 9916 </enumeratedValue> 9917 <enumeratedValue> 9918 <name>pending</name> 9919 <description>An interrupt is pending.</description> 9920 <value>1</value> 9921 </enumeratedValue> 9922 </enumeratedValues> 9923 </field> 9924 <field> 9925 <name>START_ER</name> 9926 <description>Start Error Interrupt.</description> 9927 <bitRange>[13:13]</bitRange> 9928 <enumeratedValues> 9929 <enumeratedValue> 9930 <name>inactive</name> 9931 <description>No Interrupt is Pending.</description> 9932 <value>0</value> 9933 </enumeratedValue> 9934 <enumeratedValue> 9935 <name>pending</name> 9936 <description>An interrupt is pending.</description> 9937 <value>1</value> 9938 </enumeratedValue> 9939 </enumeratedValues> 9940 </field> 9941 <field> 9942 <name>STOP_ER</name> 9943 <description>Stop Error Interrupt.</description> 9944 <bitRange>[14:14]</bitRange> 9945 <enumeratedValues> 9946 <enumeratedValue> 9947 <name>inactive</name> 9948 <description>No Interrupt is Pending.</description> 9949 <value>0</value> 9950 </enumeratedValue> 9951 <enumeratedValue> 9952 <name>pending</name> 9953 <description>An interrupt is pending.</description> 9954 <value>1</value> 9955 </enumeratedValue> 9956 </enumeratedValues> 9957 </field> 9958 <field> 9959 <name>TX_LOCK_OUT</name> 9960 <description>Transmit Lock Out Interrupt.</description> 9961 <bitRange>[15:15]</bitRange> 9962 <enumeratedValues> 9963 <enumeratedValue> 9964 <name>unlocked</name> 9965 <description>TX FIFO not locked.</description> 9966 <value>0</value> 9967 </enumeratedValue> 9968 <enumeratedValue> 9969 <name>locked</name> 9970 <description>TX FIFO locked.</description> 9971 <value>1</value> 9972 </enumeratedValue> 9973 </enumeratedValues> 9974 </field> 9975 <field> 9976 <name>RD_ADDR_MATCH</name> 9977 <description>Slave Read Address Match Interrupt</description> 9978 <bitRange>[22:22]</bitRange> 9979 <enumeratedValues> 9980 <enumeratedValue> 9981 <name>no_match</name> 9982 <description>No address match.</description> 9983 <value>0</value> 9984 </enumeratedValue> 9985 <enumeratedValue> 9986 <name>match</name> 9987 <description>Address match.</description> 9988 <value>1</value> 9989 </enumeratedValue> 9990 </enumeratedValues> 9991 </field> 9992 <field> 9993 <name>WR_ADDR_MATCH</name> 9994 <description>Slave Write Address Match Interrupt</description> 9995 <bitRange>[23:23]</bitRange> 9996 <enumeratedValues> 9997 <enumeratedValue> 9998 <name>no_match</name> 9999 <description>No address match.</description> 10000 <value>0</value> 10001 </enumeratedValue> 10002 <enumeratedValue> 10003 <name>match</name> 10004 <description>Address match.</description> 10005 <value>1</value> 10006 </enumeratedValue> 10007 </enumeratedValues> 10008 </field> 10009 </fields> 10010 </register> 10011 <register> 10012 <name>INT_EN0</name> 10013 <description>Interrupt Enable Register.</description> 10014 <addressOffset>0x0C</addressOffset> 10015 <access>read-write</access> 10016 <fields> 10017 <field> 10018 <name>DONE</name> 10019 <description>Transfer Done Interrupt Enable.</description> 10020 <bitRange>[0:0]</bitRange> 10021 <access>read-write</access> 10022 <enumeratedValues> 10023 <enumeratedValue> 10024 <name>dis</name> 10025 <description>Interrupt disabled.</description> 10026 <value>0</value> 10027 </enumeratedValue> 10028 <enumeratedValue> 10029 <name>en</name> 10030 <description>Interrupt enabled when DONE = 1.</description> 10031 <value>1</value> 10032 </enumeratedValue> 10033 </enumeratedValues> 10034 </field> 10035 <field> 10036 <name>RX_MODE</name> 10037 <description>Description not available.</description> 10038 <bitRange>[1:1]</bitRange> 10039 <access>read-write</access> 10040 <enumeratedValues> 10041 <enumeratedValue> 10042 <name>dis</name> 10043 <description>Interrupt disabled.</description> 10044 <value>0</value> 10045 </enumeratedValue> 10046 <enumeratedValue> 10047 <name>en</name> 10048 <description>Interrupt enabled when RX_MODE = 1.</description> 10049 <value>1</value> 10050 </enumeratedValue> 10051 </enumeratedValues> 10052 </field> 10053 <field> 10054 <name>GEN_CALL_ADDR</name> 10055 <description>Slave mode general call address match received input enable.</description> 10056 <bitRange>[2:2]</bitRange> 10057 <access>read-write</access> 10058 <enumeratedValues> 10059 <enumeratedValue> 10060 <name>dis</name> 10061 <description>Interrupt disabled.</description> 10062 <value>0</value> 10063 </enumeratedValue> 10064 <enumeratedValue> 10065 <name>en</name> 10066 <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description> 10067 <value>1</value> 10068 </enumeratedValue> 10069 </enumeratedValues> 10070 </field> 10071 <field> 10072 <name>ADDR_MATCH</name> 10073 <description>Slave mode incoming address match interrupt.</description> 10074 <bitRange>[3:3]</bitRange> 10075 <access>read-write</access> 10076 <enumeratedValues> 10077 <enumeratedValue> 10078 <name>dis</name> 10079 <description>Interrupt disabled.</description> 10080 <value>0</value> 10081 </enumeratedValue> 10082 <enumeratedValue> 10083 <name>en</name> 10084 <description>Interrupt enabled when ADDR_MATCH = 1.</description> 10085 <value>1</value> 10086 </enumeratedValue> 10087 </enumeratedValues> 10088 </field> 10089 <field> 10090 <name>RX_THRESH</name> 10091 <description>RX FIFO Above Treshold Level Interrupt Enable.</description> 10092 <bitRange>[4:4]</bitRange> 10093 <access>read-write</access> 10094 <enumeratedValues> 10095 <enumeratedValue> 10096 <name>dis</name> 10097 <description>Interrupt disabled.</description> 10098 <value>0</value> 10099 </enumeratedValue> 10100 <enumeratedValue> 10101 <name>en</name> 10102 <description>Interrupt enabled.</description> 10103 <value>1</value> 10104 </enumeratedValue> 10105 </enumeratedValues> 10106 </field> 10107 <field> 10108 <name>TX_THRESH</name> 10109 <description>TX FIFO Below Treshold Level Interrupt Enable.</description> 10110 <bitRange>[5:5]</bitRange> 10111 <enumeratedValues> 10112 <enumeratedValue> 10113 <name>dis</name> 10114 <description>Interrupt disabled.</description> 10115 <value>0</value> 10116 </enumeratedValue> 10117 <enumeratedValue> 10118 <name>en</name> 10119 <description>Interrupt enabled.</description> 10120 <value>1</value> 10121 </enumeratedValue> 10122 </enumeratedValues> 10123 </field> 10124 <field> 10125 <name>STOP</name> 10126 <description>Stop Interrupt Enable</description> 10127 <bitRange>[6:6]</bitRange> 10128 <access>read-write</access> 10129 <enumeratedValues> 10130 <enumeratedValue> 10131 <name>dis</name> 10132 <description>Interrupt disabled.</description> 10133 <value>0</value> 10134 </enumeratedValue> 10135 <enumeratedValue> 10136 <name>en</name> 10137 <description>Interrupt enabled when STOP = 1.</description> 10138 <value>1</value> 10139 </enumeratedValue> 10140 </enumeratedValues> 10141 </field> 10142 <field> 10143 <name>ADDR_ACK</name> 10144 <description>Received Address ACK from Slave Interrupt.</description> 10145 <bitRange>[7:7]</bitRange> 10146 <enumeratedValues> 10147 <enumeratedValue> 10148 <name>dis</name> 10149 <description>Interrupt disabled.</description> 10150 <value>0</value> 10151 </enumeratedValue> 10152 <enumeratedValue> 10153 <name>en</name> 10154 <description>Interrupt enabled.</description> 10155 <value>1</value> 10156 </enumeratedValue> 10157 </enumeratedValues> 10158 </field> 10159 <field> 10160 <name>ARB_ER</name> 10161 <description>Master Mode Arbitration Lost Interrupt.</description> 10162 <bitRange>[8:8]</bitRange> 10163 <enumeratedValues> 10164 <enumeratedValue> 10165 <name>dis</name> 10166 <description>Interrupt disabled.</description> 10167 <value>0</value> 10168 </enumeratedValue> 10169 <enumeratedValue> 10170 <name>en</name> 10171 <description>Interrupt enabled.</description> 10172 <value>1</value> 10173 </enumeratedValue> 10174 </enumeratedValues> 10175 </field> 10176 <field> 10177 <name>TO_ER</name> 10178 <description>Timeout Error Interrupt Enable.</description> 10179 <bitRange>[9:9]</bitRange> 10180 <enumeratedValues> 10181 <enumeratedValue> 10182 <name>dis</name> 10183 <description>Interrupt disabled.</description> 10184 <value>0</value> 10185 </enumeratedValue> 10186 <enumeratedValue> 10187 <name>en</name> 10188 <description>Interrupt enabled.</description> 10189 <value>1</value> 10190 </enumeratedValue> 10191 </enumeratedValues> 10192 </field> 10193 <field> 10194 <name>ADDR_NACK_ERR</name> 10195 <description>Master Mode Address NACK Received Interrupt.</description> 10196 <bitRange>[10:10]</bitRange> 10197 <enumeratedValues> 10198 <enumeratedValue> 10199 <name>dis</name> 10200 <description>Interrupt disabled.</description> 10201 <value>0</value> 10202 </enumeratedValue> 10203 <enumeratedValue> 10204 <name>en</name> 10205 <description>Interrupt enabled.</description> 10206 <value>1</value> 10207 </enumeratedValue> 10208 </enumeratedValues> 10209 </field> 10210 <field> 10211 <name>DATA_ER</name> 10212 <description>Master Mode Data NACK Received Interrupt.</description> 10213 <bitRange>[11:11]</bitRange> 10214 <enumeratedValues> 10215 <enumeratedValue> 10216 <name>dis</name> 10217 <description>Interrupt disabled.</description> 10218 <value>0</value> 10219 </enumeratedValue> 10220 <enumeratedValue> 10221 <name>en</name> 10222 <description>Interrupt enabled.</description> 10223 <value>1</value> 10224 </enumeratedValue> 10225 </enumeratedValues> 10226 </field> 10227 <field> 10228 <name>DO_NOT_RESP_ER</name> 10229 <description>Slave Mode Do Not Respond Interrupt.</description> 10230 <bitRange>[12:12]</bitRange> 10231 <enumeratedValues> 10232 <enumeratedValue> 10233 <name>dis</name> 10234 <description>Interrupt disabled.</description> 10235 <value>0</value> 10236 </enumeratedValue> 10237 <enumeratedValue> 10238 <name>en</name> 10239 <description>Interrupt enabled.</description> 10240 <value>1</value> 10241 </enumeratedValue> 10242 </enumeratedValues> 10243 </field> 10244 <field> 10245 <name>START_ER</name> 10246 <description>Out of Sequence START condition detected interrupt.</description> 10247 <bitRange>[13:13]</bitRange> 10248 <enumeratedValues> 10249 <enumeratedValue> 10250 <name>dis</name> 10251 <description>Interrupt disabled.</description> 10252 <value>0</value> 10253 </enumeratedValue> 10254 <enumeratedValue> 10255 <name>en</name> 10256 <description>Interrupt enabled.</description> 10257 <value>1</value> 10258 </enumeratedValue> 10259 </enumeratedValues> 10260 </field> 10261 <field> 10262 <name>STOP_ER</name> 10263 <description>Out of Sequence STOP condition detected interrupt.</description> 10264 <bitRange>[14:14]</bitRange> 10265 <enumeratedValues> 10266 <enumeratedValue> 10267 <name>dis</name> 10268 <description>Interrupt disabled.</description> 10269 <value>0</value> 10270 </enumeratedValue> 10271 <enumeratedValue> 10272 <name>en</name> 10273 <description>Interrupt enabled.</description> 10274 <value>1</value> 10275 </enumeratedValue> 10276 </enumeratedValues> 10277 </field> 10278 <field> 10279 <name>TX_LOCK_OUT</name> 10280 <description>TX FIFO Locked Out Interrupt.</description> 10281 <bitRange>[15:15]</bitRange> 10282 <enumeratedValues> 10283 <enumeratedValue> 10284 <name>dis</name> 10285 <description>Interrupt disabled.</description> 10286 <value>0</value> 10287 </enumeratedValue> 10288 <enumeratedValue> 10289 <name>en</name> 10290 <description>Interrupt enabled.</description> 10291 <value>1</value> 10292 </enumeratedValue> 10293 </enumeratedValues> 10294 </field> 10295 <field> 10296 <name>RD_ADDR_MATCH</name> 10297 <description>Slave Read Address Match Interrupt</description> 10298 <bitRange>[22:22]</bitRange> 10299 <enumeratedValues> 10300 <enumeratedValue> 10301 <name>dis</name> 10302 <description>Interrupt disabled.</description> 10303 <value>0</value> 10304 </enumeratedValue> 10305 <enumeratedValue> 10306 <name>en</name> 10307 <description>Interrupt enabled.</description> 10308 <value>1</value> 10309 </enumeratedValue> 10310 </enumeratedValues> 10311 </field> 10312 <field> 10313 <name>WR_ADDR_MATCH</name> 10314 <description>Slave Write Address Match Interrupt</description> 10315 <bitRange>[23:23]</bitRange> 10316 <enumeratedValues> 10317 <enumeratedValue> 10318 <name>dis</name> 10319 <description>Interrupt disabled.</description> 10320 <value>0</value> 10321 </enumeratedValue> 10322 <enumeratedValue> 10323 <name>en</name> 10324 <description>Interrupt enabled.</description> 10325 <value>1</value> 10326 </enumeratedValue> 10327 </enumeratedValues> 10328 </field> 10329 </fields> 10330 </register> 10331 <register> 10332 <name>INT_FL1</name> 10333 <description>Interrupt Status Register 1.</description> 10334 <addressOffset>0x10</addressOffset> 10335 <fields> 10336 <field> 10337 <name>RX_OVERFLOW</name> 10338 <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description> 10339 <bitRange>[0:0]</bitRange> 10340 <enumeratedValues> 10341 <enumeratedValue> 10342 <name>inactive</name> 10343 <description>No Interrupt is Pending.</description> 10344 <value>0</value> 10345 </enumeratedValue> 10346 <enumeratedValue> 10347 <name>pending</name> 10348 <description>An interrupt is pending.</description> 10349 <value>1</value> 10350 </enumeratedValue> 10351 </enumeratedValues> 10352 </field> 10353 <field> 10354 <name>TX_UNDERFLOW</name> 10355 <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description> 10356 <bitRange>[1:1]</bitRange> 10357 <enumeratedValues> 10358 <enumeratedValue> 10359 <name>inactive</name> 10360 <description>No Interrupt is Pending.</description> 10361 <value>0</value> 10362 </enumeratedValue> 10363 <enumeratedValue> 10364 <name>pending</name> 10365 <description>An interrupt is pending.</description> 10366 <value>1</value> 10367 </enumeratedValue> 10368 </enumeratedValues> 10369 </field> 10370 <field> 10371 <name>START</name> 10372 <description>START Condition Status Flag.</description> 10373 <bitRange>[2:2]</bitRange> 10374 <enumeratedValues> 10375 <enumeratedValue> 10376 <name>not_detected</name> 10377 <description>START condition not detected.</description> 10378 <value>0</value> 10379 </enumeratedValue> 10380 <enumeratedValue> 10381 <name>detected</name> 10382 <description>START condition detected.</description> 10383 <value>1</value> 10384 </enumeratedValue> 10385 </enumeratedValues> 10386 </field> 10387 </fields> 10388 </register> 10389 <register> 10390 <name>INT_EN1</name> 10391 <description>Interrupt Staus Register 1.</description> 10392 <addressOffset>0x14</addressOffset> 10393 <access>read-write</access> 10394 <fields> 10395 <field> 10396 <name>RX_OVERFLOW</name> 10397 <description>Receiver Overflow Interrupt Enable.</description> 10398 <bitRange>[0:0]</bitRange> 10399 <enumeratedValues> 10400 <enumeratedValue> 10401 <name>dis</name> 10402 <description>No Interrupt is Pending.</description> 10403 <value>0</value> 10404 </enumeratedValue> 10405 <enumeratedValue> 10406 <name>en</name> 10407 <description>An interrupt is pending.</description> 10408 <value>1</value> 10409 </enumeratedValue> 10410 </enumeratedValues> 10411 </field> 10412 <field> 10413 <name>TX_UNDERFLOW</name> 10414 <description>Transmit Underflow Interrupt Enable.</description> 10415 <bitRange>[1:1]</bitRange> 10416 <enumeratedValues> 10417 <enumeratedValue> 10418 <name>dis</name> 10419 <description>No Interrupt is Pending.</description> 10420 <value>0</value> 10421 </enumeratedValue> 10422 <enumeratedValue> 10423 <name>en</name> 10424 <description>An interrupt is pending.</description> 10425 <value>1</value> 10426 </enumeratedValue> 10427 </enumeratedValues> 10428 </field> 10429 <field> 10430 <name>START</name> 10431 <description>START Condition Interrupt Enable.</description> 10432 <bitRange>[2:2]</bitRange> 10433 <enumeratedValues> 10434 <enumeratedValue> 10435 <name>dis</name> 10436 <description>Disable START condition interrupt.</description> 10437 <value>0</value> 10438 </enumeratedValue> 10439 <enumeratedValue> 10440 <name>en</name> 10441 <description>Enable START condition interrupt.</description> 10442 <value>1</value> 10443 </enumeratedValue> 10444 </enumeratedValues> 10445 </field> 10446 </fields> 10447 </register> 10448 <register> 10449 <name>FIFO_LEN</name> 10450 <description>FIFO Configuration Register.</description> 10451 <addressOffset>0x18</addressOffset> 10452 <fields> 10453 <field> 10454 <name>RX_LEN</name> 10455 <description>Receive FIFO Length.</description> 10456 <bitRange>[7:0]</bitRange> 10457 <access>read-only</access> 10458 </field> 10459 <field> 10460 <name>TX_LEN</name> 10461 <description>Transmit FIFO Length.</description> 10462 <bitRange>[15:8]</bitRange> 10463 <access>read-only</access> 10464 </field> 10465 </fields> 10466 </register> 10467 <register> 10468 <name>RX_CTRL0</name> 10469 <description>Receive Control Register 0.</description> 10470 <addressOffset>0x1C</addressOffset> 10471 <fields> 10472 <field> 10473 <name>DNR</name> 10474 <description>Do Not Respond.</description> 10475 <bitRange>[0:0]</bitRange> 10476 <enumeratedValues> 10477 <enumeratedValue> 10478 <name>respond</name> 10479 <description>Always respond to address match.</description> 10480 <value>0</value> 10481 </enumeratedValue> 10482 <enumeratedValue> 10483 <name>not_respond_rx_fifo_empty</name> 10484 <description>Do not respond to address match when RX_FIFO is not empty.</description> 10485 <value>1</value> 10486 </enumeratedValue> 10487 </enumeratedValues> 10488 </field> 10489 <field> 10490 <name>RX_FLUSH</name> 10491 <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description> 10492 <bitRange>[7:7]</bitRange> 10493 <enumeratedValues> 10494 <enumeratedValue> 10495 <name>not_flushed</name> 10496 <description>FIFO not flushed.</description> 10497 <value>0</value> 10498 </enumeratedValue> 10499 <enumeratedValue> 10500 <name>flush</name> 10501 <description>Flush RX_FIFO.</description> 10502 <value>1</value> 10503 </enumeratedValue> 10504 </enumeratedValues> 10505 </field> 10506 <field> 10507 <name>RX_THRESH</name> 10508 <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description> 10509 <bitRange>[11:8]</bitRange> 10510 </field> 10511 </fields> 10512 </register> 10513 <register> 10514 <name>RX_CTRL1</name> 10515 <description>Receive Control Register 1.</description> 10516 <addressOffset>0x20</addressOffset> 10517 <fields> 10518 <field> 10519 <name>RX_CNT</name> 10520 <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description> 10521 <bitRange>[7:0]</bitRange> 10522 </field> 10523 <field> 10524 <name>RX_FIFO</name> 10525 <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description> 10526 <bitRange>[11:8]</bitRange> 10527 <access>read-only</access> 10528 </field> 10529 </fields> 10530 </register> 10531 <register> 10532 <name>TX_CTRL0</name> 10533 <description>Transmit Control Register 0.</description> 10534 <addressOffset>0x24</addressOffset> 10535 <fields> 10536 <field> 10537 <name>TX_PRELOAD</name> 10538 <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description> 10539 <bitRange>[0:0]</bitRange> 10540 </field> 10541 <field> 10542 <name>TX_READY_MODE</name> 10543 <description>Transmit FIFO Ready Manual Mode.</description> 10544 <bitRange>[1:1]</bitRange> 10545 <enumeratedValues> 10546 <enumeratedValue> 10547 <name>en</name> 10548 <description>HW control of I2CTXRDY enabled.</description> 10549 <value>0</value> 10550 </enumeratedValue> 10551 <enumeratedValue> 10552 <name>dis</name> 10553 <description>HW control of I2CTXRDY disabled.</description> 10554 <value>1</value> 10555 </enumeratedValue> 10556 </enumeratedValues> 10557 </field> 10558 <field> 10559 <name>TX_AMGC_AFD</name> 10560 <description>TX FIFO General Call Address Match Auto Flush Disable.</description> 10561 <bitRange>[2:2]</bitRange> 10562 <enumeratedValues> 10563 <enumeratedValue> 10564 <name>en</name> 10565 <description>Enabled.</description> 10566 <value>0</value> 10567 </enumeratedValue> 10568 <enumeratedValue> 10569 <name>dis</name> 10570 <description>Disabled.</description> 10571 <value>1</value> 10572 </enumeratedValue> 10573 </enumeratedValues> 10574 </field> 10575 <field> 10576 <name>TX_AMW_AFD</name> 10577 <description>TX FIFO Slave Address Match Write Auto Flush Disable.</description> 10578 <bitRange>[3:3]</bitRange> 10579 <enumeratedValues> 10580 <enumeratedValue> 10581 <name>en</name> 10582 <description>Enabled.</description> 10583 <value>0</value> 10584 </enumeratedValue> 10585 <enumeratedValue> 10586 <name>dis</name> 10587 <description>Disabled.</description> 10588 <value>1</value> 10589 </enumeratedValue> 10590 </enumeratedValues> 10591 </field> 10592 <field> 10593 <name>TX_AMR_AFD</name> 10594 <description>TX FIFO Slave Address Match Read Auto Flush Disable.</description> 10595 <bitRange>[4:4]</bitRange> 10596 <enumeratedValues> 10597 <enumeratedValue> 10598 <name>en</name> 10599 <description>Enabled.</description> 10600 <value>0</value> 10601 </enumeratedValue> 10602 <enumeratedValue> 10603 <name>dis</name> 10604 <description>Disabled.</description> 10605 <value>1</value> 10606 </enumeratedValue> 10607 </enumeratedValues> 10608 </field> 10609 <field> 10610 <name>TX_NACK_AFD</name> 10611 <description>TX FIFO received NACK Auto Flush Disable.</description> 10612 <bitRange>[5:5]</bitRange> 10613 <enumeratedValues> 10614 <enumeratedValue> 10615 <name>en</name> 10616 <description>Enabled.</description> 10617 <value>0</value> 10618 </enumeratedValue> 10619 <enumeratedValue> 10620 <name>dis</name> 10621 <description>Disabled.</description> 10622 <value>1</value> 10623 </enumeratedValue> 10624 </enumeratedValues> 10625 </field> 10626 <field> 10627 <name>TX_FLUSH</name> 10628 <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description> 10629 <bitRange>[7:7]</bitRange> 10630 <enumeratedValues> 10631 <enumeratedValue> 10632 <name>not_flushed</name> 10633 <description>FIFO not flushed.</description> 10634 <value>0</value> 10635 </enumeratedValue> 10636 <enumeratedValue> 10637 <name>flush</name> 10638 <description>Flush TX_FIFO.</description> 10639 <value>1</value> 10640 </enumeratedValue> 10641 </enumeratedValues> 10642 </field> 10643 <field> 10644 <name>TX_THRESH</name> 10645 <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description> 10646 <bitRange>[11:8]</bitRange> 10647 </field> 10648 </fields> 10649 </register> 10650 <register> 10651 <name>TX_CTRL1</name> 10652 <description>Transmit Control Register 1.</description> 10653 <addressOffset>0x28</addressOffset> 10654 <fields> 10655 <field> 10656 <name>TX_READY</name> 10657 <description>Transmit FIFO Preload Ready.</description> 10658 <bitRange>[0:0]</bitRange> 10659 </field> 10660 <field> 10661 <name>TX_FIFO</name> 10662 <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description> 10663 <bitRange>[11:8]</bitRange> 10664 <access>read-only</access> 10665 </field> 10666 </fields> 10667 </register> 10668 <register> 10669 <name>FIFO</name> 10670 <description>Data Register.</description> 10671 <addressOffset>0x2C</addressOffset> 10672 <fields> 10673 <field> 10674 <name>DATA</name> 10675 <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description> 10676 <bitOffset>0</bitOffset> 10677 <bitWidth>8</bitWidth> 10678 </field> 10679 </fields> 10680 </register> 10681 <register> 10682 <name>MASTER_CTRL</name> 10683 <description>Master Control Register.</description> 10684 <addressOffset>0x30</addressOffset> 10685 <fields> 10686 <field> 10687 <name>START</name> 10688 <description>Setting this bit to 1 will start a master transfer.</description> 10689 <bitRange>[0:0]</bitRange> 10690 </field> 10691 <field> 10692 <name>RESTART</name> 10693 <description>Setting this bit to 1 will generate a repeated START.</description> 10694 <bitRange>[1:1]</bitRange> 10695 </field> 10696 <field> 10697 <name>STOP</name> 10698 <description>Setting this bit to 1 will generate a STOP condition.</description> 10699 <bitRange>[2:2]</bitRange> 10700 </field> 10701 <field> 10702 <name>SL_EX_ADDR</name> 10703 <description>Slave Extend Address Select.</description> 10704 <bitRange>[7:7]</bitRange> 10705 <enumeratedValues> 10706 <enumeratedValue> 10707 <name>7_bits_address</name> 10708 <description>7-bit address.</description> 10709 <value>0</value> 10710 </enumeratedValue> 10711 <enumeratedValue> 10712 <name>10_bits_address</name> 10713 <description>10-bit address.</description> 10714 <value>1</value> 10715 </enumeratedValue> 10716 </enumeratedValues> 10717 </field> 10718 </fields> 10719 </register> 10720 <register> 10721 <name>CLK_LO</name> 10722 <description>Clock Low Register.</description> 10723 <addressOffset>0x34</addressOffset> 10724 <fields> 10725 <field> 10726 <name>SCL_LO</name> 10727 <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description> 10728 <bitRange>[8:0]</bitRange> 10729 </field> 10730 </fields> 10731 </register> 10732 <register> 10733 <name>CLK_HI</name> 10734 <description>Clock high Register.</description> 10735 <addressOffset>0x38</addressOffset> 10736 <fields> 10737 <field> 10738 <name>SCL_HI</name> 10739 <description>Clock High. In master mode, these bits define the SCL high period.</description> 10740 <bitRange>[8:0]</bitRange> 10741 </field> 10742 </fields> 10743 </register> 10744 <register> 10745 <name>TIMEOUT</name> 10746 <description>Timeout Register</description> 10747 <addressOffset>0x40</addressOffset> 10748 <fields> 10749 <field> 10750 <name>TO</name> 10751 <description>Timeout</description> 10752 <bitRange>[15:0]</bitRange> 10753 </field> 10754 </fields> 10755 </register> 10756 <register> 10757 <name>DMA</name> 10758 <description>DMA Register.</description> 10759 <addressOffset>0x48</addressOffset> 10760 <fields> 10761 <field> 10762 <name>TX_EN</name> 10763 <description>TX channel enable.</description> 10764 <bitRange>[0:0]</bitRange> 10765 <enumeratedValues> 10766 <enumeratedValue> 10767 <name>dis</name> 10768 <description>Disable.</description> 10769 <value>0</value> 10770 </enumeratedValue> 10771 <enumeratedValue> 10772 <name>en</name> 10773 <description>Enable.</description> 10774 <value>1</value> 10775 </enumeratedValue> 10776 </enumeratedValues> 10777 </field> 10778 <field> 10779 <name>RX_EN</name> 10780 <description>RX channel enable.</description> 10781 <bitRange>[1:1]</bitRange> 10782 <enumeratedValues> 10783 <enumeratedValue> 10784 <name>dis</name> 10785 <description>Disable.</description> 10786 <value>0</value> 10787 </enumeratedValue> 10788 <enumeratedValue> 10789 <name>en</name> 10790 <description>Enable.</description> 10791 <value>1</value> 10792 </enumeratedValue> 10793 </enumeratedValues> 10794 </field> 10795 </fields> 10796 </register> 10797 <register> 10798 <name>SLAVE_ADDR</name> 10799 <description>Slave Address Register.</description> 10800 <addressOffset>0x4C</addressOffset> 10801 <fields> 10802 <field> 10803 <name>SLAVE_ADDR</name> 10804 <description>Slave Address.</description> 10805 <bitRange>[9:0]</bitRange> 10806 </field> 10807 <field> 10808 <name>EX_ADDR</name> 10809 <description>Extended Address Select.</description> 10810 <bitRange>[15:15]</bitRange> 10811 <enumeratedValues> 10812 <enumeratedValue> 10813 <name>7_bits_address</name> 10814 <description>7-bit address.</description> 10815 <value>0</value> 10816 </enumeratedValue> 10817 <enumeratedValue> 10818 <name>10_bits_address</name> 10819 <description>10-bit address.</description> 10820 <value>1</value> 10821 </enumeratedValue> 10822 </enumeratedValues> 10823 </field> 10824 </fields> 10825 </register> 10826 </registers> 10827 </peripheral> 10828<!--I2C0 Inter-Integrated Circuit.--> 10829 <peripheral derivedFrom="I2C0"> 10830 <name>I2C1</name> 10831 <description>Inter-Integrated Circuit. 1</description> 10832 <baseAddress>0x4001E000</baseAddress> 10833 <interrupt> 10834 <name>I2C1</name> 10835 <description>I2C1 IRQ</description> 10836 <value>36</value> 10837 </interrupt> 10838 </peripheral> 10839<!--I2C1 Inter-Integrated Circuit. 1--> 10840 <peripheral derivedFrom="I2C0"> 10841 <name>I2C2</name> 10842 <description>Inter-Integrated Circuit. 2</description> 10843 <baseAddress>0x4001F000</baseAddress> 10844 <interrupt> 10845 <name>I2C2</name> 10846 <description>I2C2 IRQ</description> 10847 <value>62</value> 10848 </interrupt> 10849 </peripheral> 10850<!--I2C2 Inter-Integrated Circuit. 2--> 10851 <peripheral> 10852 <name>ICC0</name> 10853 <description>Instruction Cache Controller Registers</description> 10854 <baseAddress>0x4002A000</baseAddress> 10855 <addressBlock> 10856 <offset>0x00</offset> 10857 <size>0x1000</size> 10858 <usage>registers</usage> 10859 </addressBlock> 10860 <registers> 10861 <register> 10862 <name>CACHE_ID</name> 10863 <description>Cache ID Register.</description> 10864 <addressOffset>0x0000</addressOffset> 10865 <access>read-only</access> 10866 <fields> 10867 <field> 10868 <name>RELNUM</name> 10869 <description>Release Number. Identifies the RTL release version.</description> 10870 <bitOffset>0</bitOffset> 10871 <bitWidth>6</bitWidth> 10872 </field> 10873 <field> 10874 <name>PARTNUM</name> 10875 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 10876 <bitOffset>6</bitOffset> 10877 <bitWidth>4</bitWidth> 10878 </field> 10879 <field> 10880 <name>CCHID</name> 10881 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 10882 <bitOffset>10</bitOffset> 10883 <bitWidth>6</bitWidth> 10884 </field> 10885 </fields> 10886 </register> 10887 <register> 10888 <name>MEMCFG</name> 10889 <description>Memory Configuration Register.</description> 10890 <addressOffset>0x0004</addressOffset> 10891 <access>read-only</access> 10892 <resetValue>0x00080008</resetValue> 10893 <fields> 10894 <field> 10895 <name>CCHSZ</name> 10896 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 10897 <bitOffset>0</bitOffset> 10898 <bitWidth>16</bitWidth> 10899 </field> 10900 <field> 10901 <name>MEMSZ</name> 10902 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 10903 <bitOffset>16</bitOffset> 10904 <bitWidth>16</bitWidth> 10905 </field> 10906 </fields> 10907 </register> 10908 <register> 10909 <name>CACHE_CTRL</name> 10910 <description>Cache Control and Status Register.</description> 10911 <addressOffset>0x0100</addressOffset> 10912 <fields> 10913 <field> 10914 <name>EN</name> 10915 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 10916 <bitOffset>0</bitOffset> 10917 <bitWidth>1</bitWidth> 10918 <enumeratedValues> 10919 <enumeratedValue> 10920 <name>dis</name> 10921 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 10922 <value>0</value> 10923 </enumeratedValue> 10924 <enumeratedValue> 10925 <name>en</name> 10926 <description>Cache Enabled.</description> 10927 <value>1</value> 10928 </enumeratedValue> 10929 </enumeratedValues> 10930 </field> 10931 <field> 10932 <name>RDY</name> 10933 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 10934 <bitOffset>16</bitOffset> 10935 <bitWidth>1</bitWidth> 10936 <access>read-only</access> 10937 <enumeratedValues> 10938 <enumeratedValue> 10939 <name>invalid</name> 10940 <description>Not Ready.</description> 10941 <value>0</value> 10942 </enumeratedValue> 10943 <enumeratedValue> 10944 <name>ready</name> 10945 <description>Ready.</description> 10946 <value>1</value> 10947 </enumeratedValue> 10948 </enumeratedValues> 10949 </field> 10950 </fields> 10951 </register> 10952 <register> 10953 <name>INVALIDATE</name> 10954 <description>Invalidate All Registers.</description> 10955 <addressOffset>0x0700</addressOffset> 10956 <access>read-write</access> 10957 <fields> 10958 <field> 10959 <name>INVALID</name> 10960 <description>Invalidate.</description> 10961 <bitOffset>0</bitOffset> 10962 <bitWidth>32</bitWidth> 10963 </field> 10964 </fields> 10965 </register> 10966 </registers> 10967 </peripheral> 10968<!--ICC0 Instruction Cache Controller Registers--> 10969 <peripheral> 10970 <name>MCR</name> 10971 <description>Misc Control.</description> 10972 <baseAddress>0x40006C00</baseAddress> 10973 <addressBlock> 10974 <offset>0x00</offset> 10975 <size>0x400</size> 10976 <usage>registers</usage> 10977 </addressBlock> 10978 <registers> 10979 <register> 10980 <name>ECCEN</name> 10981 <description>ECC Enable Register</description> 10982 <addressOffset>0x00</addressOffset> 10983 <fields> 10984 <field> 10985 <name>SYSRAM0ECCEN</name> 10986 <description>ECC System RAM Enable.</description> 10987 <bitOffset>0</bitOffset> 10988 <bitWidth>1</bitWidth> 10989 <enumeratedValues> 10990 <enumeratedValue> 10991 <name>dis</name> 10992 <description>disabled.</description> 10993 <value>0</value> 10994 </enumeratedValue> 10995 <enumeratedValue> 10996 <name>en</name> 10997 <description>enabled.</description> 10998 <value>1</value> 10999 </enumeratedValue> 11000 </enumeratedValues> 11001 </field> 11002 <field> 11003 <name>SYSRAM1ECCEN</name> 11004 <description>ECC System RAM Enable.</description> 11005 <bitOffset>1</bitOffset> 11006 <bitWidth>1</bitWidth> 11007 <enumeratedValues> 11008 <enumeratedValue> 11009 <name>dis</name> 11010 <description>disabled.</description> 11011 <value>0</value> 11012 </enumeratedValue> 11013 <enumeratedValue> 11014 <name>en</name> 11015 <description>enabled.</description> 11016 <value>1</value> 11017 </enumeratedValue> 11018 </enumeratedValues> 11019 </field> 11020 <field> 11021 <name>SYSRAM2ECCEN</name> 11022 <description>ECC System RAM Enable.</description> 11023 <bitOffset>2</bitOffset> 11024 <bitWidth>1</bitWidth> 11025 <enumeratedValues> 11026 <enumeratedValue> 11027 <name>dis</name> 11028 <description>disabled.</description> 11029 <value>0</value> 11030 </enumeratedValue> 11031 <enumeratedValue> 11032 <name>en</name> 11033 <description>enabled.</description> 11034 <value>1</value> 11035 </enumeratedValue> 11036 </enumeratedValues> 11037 </field> 11038 <field> 11039 <name>SYSRAM3ECCEN</name> 11040 <description>ECC System RAM Enable.</description> 11041 <bitOffset>3</bitOffset> 11042 <bitWidth>1</bitWidth> 11043 <enumeratedValues> 11044 <enumeratedValue> 11045 <name>dis</name> 11046 <description>disabled.</description> 11047 <value>0</value> 11048 </enumeratedValue> 11049 <enumeratedValue> 11050 <name>en</name> 11051 <description>enabled.</description> 11052 <value>1</value> 11053 </enumeratedValue> 11054 </enumeratedValues> 11055 </field> 11056 <field> 11057 <name>SYSRAM4ECCEN</name> 11058 <description>ECC System RAM Enable.</description> 11059 <bitOffset>4</bitOffset> 11060 <bitWidth>1</bitWidth> 11061 <enumeratedValues> 11062 <enumeratedValue> 11063 <name>dis</name> 11064 <description>disabled.</description> 11065 <value>0</value> 11066 </enumeratedValue> 11067 <enumeratedValue> 11068 <name>en</name> 11069 <description>enabled.</description> 11070 <value>1</value> 11071 </enumeratedValue> 11072 </enumeratedValues> 11073 </field> 11074 <field> 11075 <name>SYSRAM5ECCEN</name> 11076 <description>ECC System RAM Enable.</description> 11077 <bitOffset>5</bitOffset> 11078 <bitWidth>1</bitWidth> 11079 <enumeratedValues> 11080 <enumeratedValue> 11081 <name>dis</name> 11082 <description>disabled.</description> 11083 <value>0</value> 11084 </enumeratedValue> 11085 <enumeratedValue> 11086 <name>en</name> 11087 <description>enabled.</description> 11088 <value>1</value> 11089 </enumeratedValue> 11090 </enumeratedValues> 11091 </field> 11092 <field> 11093 <name>IC0ECCEN</name> 11094 <description>Icache0 ECC Enable.</description> 11095 <bitOffset>8</bitOffset> 11096 <bitWidth>1</bitWidth> 11097 <enumeratedValues> 11098 <enumeratedValue> 11099 <name>dis</name> 11100 <description>disabled.</description> 11101 <value>0</value> 11102 </enumeratedValue> 11103 <enumeratedValue> 11104 <name>en</name> 11105 <description>enabled.</description> 11106 <value>1</value> 11107 </enumeratedValue> 11108 </enumeratedValues> 11109 </field> 11110 <field> 11111 <name>ICXIPECCEN</name> 11112 <description>IcacheXIP ECC Enable.</description> 11113 <bitOffset>10</bitOffset> 11114 <bitWidth>1</bitWidth> 11115 <enumeratedValues> 11116 <enumeratedValue> 11117 <name>dis</name> 11118 <description>disabled.</description> 11119 <value>0</value> 11120 </enumeratedValue> 11121 <enumeratedValue> 11122 <name>en</name> 11123 <description>enabled.</description> 11124 <value>1</value> 11125 </enumeratedValue> 11126 </enumeratedValues> 11127 </field> 11128 <field> 11129 <name>FL0ECCEN</name> 11130 <description>Flash0 ECC Enable.</description> 11131 <bitOffset>11</bitOffset> 11132 <bitWidth>1</bitWidth> 11133 <enumeratedValues> 11134 <enumeratedValue> 11135 <name>dis</name> 11136 <description>disabled.</description> 11137 <value>0</value> 11138 </enumeratedValue> 11139 <enumeratedValue> 11140 <name>en</name> 11141 <description>enabled.</description> 11142 <value>1</value> 11143 </enumeratedValue> 11144 </enumeratedValues> 11145 </field> 11146 <field> 11147 <name>FL1ECCEN</name> 11148 <description>Flash1 ECC Enable.</description> 11149 <bitOffset>12</bitOffset> 11150 <bitWidth>1</bitWidth> 11151 <enumeratedValues> 11152 <enumeratedValue> 11153 <name>dis</name> 11154 <description>disabled.</description> 11155 <value>0</value> 11156 </enumeratedValue> 11157 <enumeratedValue> 11158 <name>en</name> 11159 <description>enabled.</description> 11160 <value>1</value> 11161 </enumeratedValue> 11162 </enumeratedValues> 11163 </field> 11164 </fields> 11165 </register> 11166 <register> 11167 <name>PDOWN</name> 11168 <description>PDOWN Drive Strength</description> 11169 <addressOffset>0x08</addressOffset> 11170 <fields> 11171 <field> 11172 <name>PDOWNDS</name> 11173 <description>PDOWN Drive Strength</description> 11174 <bitOffset>0</bitOffset> 11175 <bitWidth>2</bitWidth> 11176 </field> 11177 <field> 11178 <name>PDOWNVS</name> 11179 <description>PDOWN Voltage Select</description> 11180 <bitOffset>2</bitOffset> 11181 <bitWidth>1</bitWidth> 11182 </field> 11183 </fields> 11184 </register> 11185 <register> 11186 <name>CTRL</name> 11187 <description>Misc Power State Control Register</description> 11188 <addressOffset>0x10</addressOffset> 11189 <fields> 11190 <field> 11191 <name>VDDCSW</name> 11192 <description>Controls switching of VCORE</description> 11193 <bitOffset>1</bitOffset> 11194 <bitWidth>2</bitWidth> 11195 </field> 11196 <field> 11197 <name>USBSWEN_N</name> 11198 <description>USB Switch Control</description> 11199 <bitOffset>3</bitOffset> 11200 <bitWidth>1</bitWidth> 11201 <enumeratedValues> 11202 <enumeratedValue> 11203 <name>off</name> 11204 <description>USB SW off in LP modes</description> 11205 <value>1</value> 11206 </enumeratedValue> 11207 <enumeratedValue> 11208 <name>on</name> 11209 <description>USB SW On</description> 11210 <value>0</value> 11211 </enumeratedValue> 11212 </enumeratedValues> 11213 </field> 11214 <field> 11215 <name>P1M</name> 11216 <description>Enable the Reset Pad Pull Up Resistors</description> 11217 <bitOffset>9</bitOffset> 11218 <bitWidth>1</bitWidth> 11219 <enumeratedValues> 11220 <enumeratedValue> 11221 <name>1m</name> 11222 <description>1MOhm Pullup</description> 11223 <value>0</value> 11224 </enumeratedValue> 11225 <enumeratedValue> 11226 <name>25k</name> 11227 <description>25kOhm Pullup.</description> 11228 <value>1</value> 11229 </enumeratedValue> 11230 </enumeratedValues> 11231 </field> 11232 <field> 11233 <name>rstn_voltage_sel</name> 11234 <description>Error! Description not Found!</description> 11235 <bitOffset>10</bitOffset> 11236 <bitWidth>1</bitWidth> 11237 </field> 11238 </fields> 11239 </register> 11240 </registers> 11241 </peripheral> 11242<!--MCR Misc Control.--> 11243 <peripheral> 11244 <name>OWM</name> 11245 <description>1-Wire Master Interface.</description> 11246 <baseAddress>0x4003D000</baseAddress> 11247 <size>32</size> 11248 <access>read-write</access> 11249 <addressBlock> 11250 <offset>0</offset> 11251 <size>0x1000</size> 11252 <usage>registers</usage> 11253 </addressBlock> 11254 <interrupt> 11255 <name>OneWire</name> 11256 <value>67</value> 11257 </interrupt> 11258 <registers> 11259 <register> 11260 <name>CFG</name> 11261 <description>1-Wire Master Configuration.</description> 11262 <addressOffset>0x0000</addressOffset> 11263 <access>read-write</access> 11264 <fields> 11265 <field> 11266 <name>long_line_mode</name> 11267 <description>Long Line Mode.</description> 11268 <bitRange>[0:0]</bitRange> 11269 <access>read-write</access> 11270 </field> 11271 <field> 11272 <name>force_pres_det</name> 11273 <description>Force Line During Presence Detect.</description> 11274 <bitRange>[1:1]</bitRange> 11275 <access>read-write</access> 11276 </field> 11277 <field> 11278 <name>bit_bang_en</name> 11279 <description>Bit Bang Enable.</description> 11280 <bitRange>[2:2]</bitRange> 11281 <access>read-write</access> 11282 </field> 11283 <field> 11284 <name>ext_pullup_mode</name> 11285 <description>Provide an extra output control to control an external pullup.</description> 11286 <bitRange>[3:3]</bitRange> 11287 <access>read-write</access> 11288 </field> 11289 <field> 11290 <name>ext_pullup_enable</name> 11291 <description>Enable External Pullup.</description> 11292 <bitRange>[4:4]</bitRange> 11293 <access>read-write</access> 11294 </field> 11295 <field> 11296 <name>single_bit_mode</name> 11297 <description>Enable Single Bit TX/RX Mode.</description> 11298 <bitRange>[5:5]</bitRange> 11299 <access>read-write</access> 11300 </field> 11301 <field> 11302 <name>overdrive</name> 11303 <description>Enables overdrive speed for 1-Wire operations.</description> 11304 <bitRange>[6:6]</bitRange> 11305 <access>read-write</access> 11306 </field> 11307 <field> 11308 <name>int_pullup_enable</name> 11309 <description>Enable intenral pullup.</description> 11310 <bitRange>[7:7]</bitRange> 11311 <access>read-write</access> 11312 </field> 11313 </fields> 11314 </register> 11315 <register> 11316 <name>CLK_DIV_1US</name> 11317 <description>1-Wire Master Clock Divisor.</description> 11318 <addressOffset>0x0004</addressOffset> 11319 <access>read-write</access> 11320 <fields> 11321 <field> 11322 <name>divisor</name> 11323 <description>Clock Divisor for 1Mhz.</description> 11324 <bitRange>[7:0]</bitRange> 11325 <access>read-write</access> 11326 </field> 11327 </fields> 11328 </register> 11329 <register> 11330 <name>CTRL_STAT</name> 11331 <description>1-Wire Master Control/Status.</description> 11332 <addressOffset>0x0008</addressOffset> 11333 <access>read-write</access> 11334 <fields> 11335 <field> 11336 <name>start_ow_reset</name> 11337 <description>Start OW Reset.</description> 11338 <bitRange>[0:0]</bitRange> 11339 <access>read-write</access> 11340 </field> 11341 <field> 11342 <name>sra_mode</name> 11343 <description>SRA Mode.</description> 11344 <bitRange>[1:1]</bitRange> 11345 <access>read-write</access> 11346 </field> 11347 <field> 11348 <name>bit_bang_oe</name> 11349 <description>Bit Bang Output Enable.</description> 11350 <bitRange>[2:2]</bitRange> 11351 <access>read-write</access> 11352 </field> 11353 <field> 11354 <name>ow_input</name> 11355 <description>OW Input State.</description> 11356 <bitRange>[3:3]</bitRange> 11357 <access>read-only</access> 11358 </field> 11359 <field> 11360 <name>od_spec_mode</name> 11361 <description>Overdrive Spec Mode.</description> 11362 <bitRange>[4:4]</bitRange> 11363 <access>read-only</access> 11364 </field> 11365 <field> 11366 <name>presence_detect</name> 11367 <description>Presence Pulse Detected.</description> 11368 <bitRange>[5:5]</bitRange> 11369 <access>read-only</access> 11370 </field> 11371 </fields> 11372 </register> 11373 <register> 11374 <name>DATA</name> 11375 <description>1-Wire Master Data Buffer.</description> 11376 <addressOffset>0x000C</addressOffset> 11377 <access>read-write</access> 11378 <fields> 11379 <field> 11380 <name>tx_rx</name> 11381 <description>TX/RX Buffer.</description> 11382 <bitRange>[7:0]</bitRange> 11383 <access>read-write</access> 11384 </field> 11385 </fields> 11386 </register> 11387 <register> 11388 <name>INTFL</name> 11389 <description>1-Wire Master Interrupt Flags.</description> 11390 <addressOffset>0x0010</addressOffset> 11391 <access>read-write</access> 11392 <fields> 11393 <field> 11394 <name>ow_reset_done</name> 11395 <description>OW Reset Sequence Completed.</description> 11396 <bitRange>[0:0]</bitRange> 11397 <access>read-write</access> 11398 </field> 11399 <field> 11400 <name>tx_data_empty</name> 11401 <description>TX Data Empty Interrupt Flag.</description> 11402 <bitRange>[1:1]</bitRange> 11403 <access>read-write</access> 11404 </field> 11405 <field> 11406 <name>rx_data_ready</name> 11407 <description>RX Data Ready Interrupt Flag</description> 11408 <bitRange>[2:2]</bitRange> 11409 <access>read-write</access> 11410 </field> 11411 <field> 11412 <name>line_short</name> 11413 <description>OW Line Short Detected Interrupt Flag.</description> 11414 <bitRange>[3:3]</bitRange> 11415 <access>read-write</access> 11416 </field> 11417 <field> 11418 <name>line_low</name> 11419 <description>OW Line Low Detected Interrupt Flag.</description> 11420 <bitRange>[4:4]</bitRange> 11421 <access>read-write</access> 11422 </field> 11423 </fields> 11424 </register> 11425 <register> 11426 <name>INTEN</name> 11427 <description>1-Wire Master Interrupt Enables.</description> 11428 <addressOffset>0x0014</addressOffset> 11429 <access>read-write</access> 11430 <fields> 11431 <field> 11432 <name>ow_reset_done</name> 11433 <description>OW Reset Sequence Completed.</description> 11434 <bitRange>[0:0]</bitRange> 11435 <access>read-write</access> 11436 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11437 </field> 11438 <field> 11439 <name>tx_data_empty</name> 11440 <description>Tx Data Empty Interrupt Enable.</description> 11441 <bitRange>[1:1]</bitRange> 11442 <access>read-write</access> 11443 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11444 </field> 11445 <field> 11446 <name>rx_data_ready</name> 11447 <description>Rx Data Ready Interrupt Enable.</description> 11448 <bitRange>[2:2]</bitRange> 11449 <access>read-write</access> 11450 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11451 </field> 11452 <field> 11453 <name>line_short</name> 11454 <description>OW Line Short Detected Interrupt Enable.</description> 11455 <bitRange>[3:3]</bitRange> 11456 <access>read-write</access> 11457 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11458 </field> 11459 <field> 11460 <name>line_low</name> 11461 <description>OW Line Low Detected Interrupt Enable.</description> 11462 <bitRange>[4:4]</bitRange> 11463 <access>read-write</access> 11464 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11465 </field> 11466 </fields> 11467 </register> 11468 </registers> 11469 </peripheral> 11470<!--OWM 1-Wire Master Interface.--> 11471 <peripheral> 11472 <name>PT</name> 11473 <description>Pulse Train</description> 11474 <groupName>Pulse_Train</groupName> 11475 <baseAddress>0x4003C020</baseAddress> 11476 <size>32</size> 11477 <access>read-write</access> 11478 <addressBlock> 11479 <offset>0</offset> 11480 <size>0x0010</size> 11481 <usage>registers</usage> 11482 </addressBlock> 11483 <registers> 11484 <register> 11485 <name>RATE_LENGTH</name> 11486 <description>Pulse Train Configuration</description> 11487 <addressOffset>0x0000</addressOffset> 11488 <access>read-write</access> 11489 <fields> 11490 <field> 11491 <name>rate_control</name> 11492 <description>Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.</description> 11493 <bitOffset>0</bitOffset> 11494 <bitWidth>27</bitWidth> 11495 <access>read-write</access> 11496 </field> 11497 <field> 11498 <name>mode</name> 11499 <description>Pulse Train Output Mode/Train Length</description> 11500 <bitOffset>27</bitOffset> 11501 <bitWidth>5</bitWidth> 11502 <access>read-write</access> 11503 <enumeratedValues> 11504 <enumeratedValue> 11505 <name>32_BIT</name> 11506 <description>Pulse train, 32 bit pattern.</description> 11507 <value>0</value> 11508 </enumeratedValue> 11509 <enumeratedValue> 11510 <name>SQUARE_WAVE</name> 11511 <description>Square wave mode.</description> 11512 <value>1</value> 11513 </enumeratedValue> 11514 <enumeratedValue> 11515 <name>2_BIT</name> 11516 <description>Pulse train, 2 bit pattern.</description> 11517 <value>2</value> 11518 </enumeratedValue> 11519 <enumeratedValue> 11520 <name>3_BIT</name> 11521 <description>Pulse train, 3 bit pattern.</description> 11522 <value>3</value> 11523 </enumeratedValue> 11524 <enumeratedValue> 11525 <name>4_BIT</name> 11526 <description>Pulse train, 4 bit pattern.</description> 11527 <value>4</value> 11528 </enumeratedValue> 11529 <enumeratedValue> 11530 <name>5_BIT</name> 11531 <description>Pulse train, 5 bit pattern.</description> 11532 <value>5</value> 11533 </enumeratedValue> 11534 <enumeratedValue> 11535 <name>6_BIT</name> 11536 <description>Pulse train, 6 bit pattern.</description> 11537 <value>6</value> 11538 </enumeratedValue> 11539 <enumeratedValue> 11540 <name>7_BIT</name> 11541 <description>Pulse train, 7 bit pattern.</description> 11542 <value>7</value> 11543 </enumeratedValue> 11544 <enumeratedValue> 11545 <name>8_BIT</name> 11546 <description>Pulse train, 8 bit pattern.</description> 11547 <value>8</value> 11548 </enumeratedValue> 11549 <enumeratedValue> 11550 <name>9_BIT</name> 11551 <description>Pulse train, 9 bit pattern.</description> 11552 <value>9</value> 11553 </enumeratedValue> 11554 <enumeratedValue> 11555 <name>10_BIT</name> 11556 <description>Pulse train, 10 bit pattern.</description> 11557 <value>10</value> 11558 </enumeratedValue> 11559 <enumeratedValue> 11560 <name>11_BIT</name> 11561 <description>Pulse train, 11 bit pattern.</description> 11562 <value>11</value> 11563 </enumeratedValue> 11564 <enumeratedValue> 11565 <name>12_BIT</name> 11566 <description>Pulse train, 12 bit pattern.</description> 11567 <value>12</value> 11568 </enumeratedValue> 11569 <enumeratedValue> 11570 <name>13_BIT</name> 11571 <description>Pulse train, 13 bit pattern.</description> 11572 <value>13</value> 11573 </enumeratedValue> 11574 <enumeratedValue> 11575 <name>14_BIT</name> 11576 <description>Pulse train, 14 bit pattern.</description> 11577 <value>14</value> 11578 </enumeratedValue> 11579 <enumeratedValue> 11580 <name>15_BIT</name> 11581 <description>Pulse train, 15 bit pattern.</description> 11582 <value>15</value> 11583 </enumeratedValue> 11584 <enumeratedValue> 11585 <name>16_BIT</name> 11586 <description>Pulse train, 16 bit pattern.</description> 11587 <value>16</value> 11588 </enumeratedValue> 11589 <enumeratedValue> 11590 <name>17_BIT</name> 11591 <description>Pulse train, 17 bit pattern.</description> 11592 <value>17</value> 11593 </enumeratedValue> 11594 <enumeratedValue> 11595 <name>18_BIT</name> 11596 <description>Pulse train, 18 bit pattern.</description> 11597 <value>18</value> 11598 </enumeratedValue> 11599 <enumeratedValue> 11600 <name>19_BIT</name> 11601 <description>Pulse train, 19 bit pattern.</description> 11602 <value>19</value> 11603 </enumeratedValue> 11604 <enumeratedValue> 11605 <name>20_BIT</name> 11606 <description>Pulse train, 20 bit pattern.</description> 11607 <value>20</value> 11608 </enumeratedValue> 11609 <enumeratedValue> 11610 <name>21_BIT</name> 11611 <description>Pulse train, 21 bit pattern.</description> 11612 <value>21</value> 11613 </enumeratedValue> 11614 <enumeratedValue> 11615 <name>22_BIT</name> 11616 <description>Pulse train, 22 bit pattern.</description> 11617 <value>22</value> 11618 </enumeratedValue> 11619 <enumeratedValue> 11620 <name>23_BIT</name> 11621 <description>Pulse train, 23 bit pattern.</description> 11622 <value>23</value> 11623 </enumeratedValue> 11624 <enumeratedValue> 11625 <name>24_BIT</name> 11626 <description>Pulse train, 24 bit pattern.</description> 11627 <value>24</value> 11628 </enumeratedValue> 11629 <enumeratedValue> 11630 <name>25_BIT</name> 11631 <description>Pulse train, 25 bit pattern.</description> 11632 <value>25</value> 11633 </enumeratedValue> 11634 <enumeratedValue> 11635 <name>26_BIT</name> 11636 <description>Pulse train, 26 bit pattern.</description> 11637 <value>26</value> 11638 </enumeratedValue> 11639 <enumeratedValue> 11640 <name>27_BIT</name> 11641 <description>Pulse train, 27 bit pattern.</description> 11642 <value>27</value> 11643 </enumeratedValue> 11644 <enumeratedValue> 11645 <name>28_BIT</name> 11646 <description>Pulse train, 28 bit pattern.</description> 11647 <value>28</value> 11648 </enumeratedValue> 11649 <enumeratedValue> 11650 <name>29_BIT</name> 11651 <description>Pulse train, 29 bit pattern.</description> 11652 <value>29</value> 11653 </enumeratedValue> 11654 <enumeratedValue> 11655 <name>30_BIT</name> 11656 <description>Pulse train, 30 bit pattern.</description> 11657 <value>30</value> 11658 </enumeratedValue> 11659 <enumeratedValue> 11660 <name>31_BIT</name> 11661 <description>Pulse train, 31 bit pattern.</description> 11662 <value>31</value> 11663 </enumeratedValue> 11664 </enumeratedValues> 11665 </field> 11666 </fields> 11667 </register> 11668 <register> 11669 <name>TRAIN</name> 11670 <description>Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.</description> 11671 <addressOffset>0x0004</addressOffset> 11672 <access>read-write</access> 11673 </register> 11674 <register> 11675 <name>LOOP</name> 11676 <description>Pulse Train Loop Count</description> 11677 <addressOffset>0x0008</addressOffset> 11678 <access>read-write</access> 11679 <fields> 11680 <field> 11681 <name>count</name> 11682 <description>Number of loops for this pulse train to repeat.</description> 11683 <bitOffset>0</bitOffset> 11684 <bitWidth>16</bitWidth> 11685 <access>read-write</access> 11686 </field> 11687 <field> 11688 <name>delay</name> 11689 <description>Delay between loops of the Pulse Train in PT Peripheral Clock cycles</description> 11690 <bitOffset>16</bitOffset> 11691 <bitWidth>12</bitWidth> 11692 <access>read-write</access> 11693 </field> 11694 </fields> 11695 </register> 11696 <register> 11697 <name>RESTART</name> 11698 <description> Pulse Train Auto-Restart Configuration.</description> 11699 <addressOffset>0x000C</addressOffset> 11700 <access>read-write</access> 11701 <fields> 11702 <field> 11703 <name>pt_x_select</name> 11704 <description>Auto-Restart PT X Select</description> 11705 <bitOffset>0</bitOffset> 11706 <bitWidth>5</bitWidth> 11707 <access>read-write</access> 11708 </field> 11709 <field> 11710 <name>on_pt_x_loop_exit</name> 11711 <description>Enable Auto-Restart on PT X Loop Exit</description> 11712 <bitOffset>7</bitOffset> 11713 <bitWidth>1</bitWidth> 11714 <access>read-write</access> 11715 </field> 11716 <field> 11717 <name>pt_y_select</name> 11718 <description>Auto-Restart PT Y Select</description> 11719 <bitOffset>8</bitOffset> 11720 <bitWidth>5</bitWidth> 11721 <access>read-write</access> 11722 </field> 11723 <field> 11724 <name>on_pt_y_loop_exit</name> 11725 <description>Enable Auto-Restart on PT Y Loop Exit</description> 11726 <bitOffset>15</bitOffset> 11727 <bitWidth>1</bitWidth> 11728 <access>read-write</access> 11729 </field> 11730 </fields> 11731 </register> 11732 </registers> 11733 </peripheral> 11734<!--PT Pulse Train--> 11735 <peripheral derivedFrom="PT"> 11736 <name>PT1</name> 11737 <description>Pulse Train 1</description> 11738 <baseAddress>0x4003C040</baseAddress> 11739 </peripheral> 11740<!--PT1 Pulse Train 1--> 11741 <peripheral derivedFrom="PT"> 11742 <name>PT2</name> 11743 <description>Pulse Train 2</description> 11744 <baseAddress>0x4003C060</baseAddress> 11745 </peripheral> 11746<!--PT2 Pulse Train 2--> 11747 <peripheral derivedFrom="PT"> 11748 <name>PT3</name> 11749 <description>Pulse Train 3</description> 11750 <baseAddress>0x4003C080</baseAddress> 11751 </peripheral> 11752<!--PT3 Pulse Train 3--> 11753 <peripheral derivedFrom="PT"> 11754 <name>PT4</name> 11755 <description>Pulse Train 4</description> 11756 <baseAddress>0x4003C0A0</baseAddress> 11757 </peripheral> 11758<!--PT4 Pulse Train 4--> 11759 <peripheral derivedFrom="PT"> 11760 <name>PT5</name> 11761 <description>Pulse Train 5</description> 11762 <baseAddress>0x4003C0C0</baseAddress> 11763 </peripheral> 11764<!--PT5 Pulse Train 5--> 11765 <peripheral derivedFrom="PT"> 11766 <name>PT6</name> 11767 <description>Pulse Train 6</description> 11768 <baseAddress>0x4003C0E0</baseAddress> 11769 </peripheral> 11770<!--PT6 Pulse Train 6--> 11771 <peripheral derivedFrom="PT"> 11772 <name>PT7</name> 11773 <description>Pulse Train 7</description> 11774 <baseAddress>0x4003C100</baseAddress> 11775 </peripheral> 11776<!--PT7 Pulse Train 7--> 11777 <peripheral derivedFrom="PT"> 11778 <name>PT8</name> 11779 <description>Pulse Train 8</description> 11780 <baseAddress /> 11781 </peripheral> 11782<!--PT8 Pulse Train 8--> 11783 <peripheral> 11784 <name>PTG</name> 11785 <description>Pulse Train Generation</description> 11786 <groupName>Pulse_Train</groupName> 11787 <baseAddress>0x4003C000</baseAddress> 11788 <size>32</size> 11789 <access>read-write</access> 11790 <addressBlock> 11791 <offset>0</offset> 11792 <size>0x0018</size> 11793 <usage>registers</usage> 11794 </addressBlock> 11795 <interrupt> 11796 <name>PT</name> 11797 <description>Pulse Train IRQ</description> 11798 <value>59</value> 11799 </interrupt> 11800 <registers> 11801 <register> 11802 <name>ENABLE</name> 11803 <description>Global Enable/Disable Controls for All Pulse Trains</description> 11804 <addressOffset>0x0000</addressOffset> 11805 <access>read-write</access> 11806 <fields> 11807 <field> 11808 <name>pt0</name> 11809 <description>Enable/Disable control for PT0</description> 11810 <bitOffset>0</bitOffset> 11811 <bitWidth>1</bitWidth> 11812 <access>read-write</access> 11813 </field> 11814 <field> 11815 <name>pt1</name> 11816 <description>Enable/Disable control for PT1</description> 11817 <bitOffset>1</bitOffset> 11818 <bitWidth>1</bitWidth> 11819 <access>read-write</access> 11820 </field> 11821 <field> 11822 <name>pt2</name> 11823 <description>Enable/Disable control for PT2</description> 11824 <bitOffset>2</bitOffset> 11825 <bitWidth>1</bitWidth> 11826 <access>read-write</access> 11827 </field> 11828 <field> 11829 <name>pt3</name> 11830 <description>Enable/Disable control for PT3</description> 11831 <bitOffset>3</bitOffset> 11832 <bitWidth>1</bitWidth> 11833 <access>read-write</access> 11834 </field> 11835 <field> 11836 <name>pt4</name> 11837 <description>Enable/Disable control for PT4</description> 11838 <bitOffset>4</bitOffset> 11839 <bitWidth>1</bitWidth> 11840 <access>read-write</access> 11841 </field> 11842 <field> 11843 <name>pt5</name> 11844 <description>Enable/Disable control for PT5</description> 11845 <bitOffset>5</bitOffset> 11846 <bitWidth>1</bitWidth> 11847 <access>read-write</access> 11848 </field> 11849 <field> 11850 <name>pt6</name> 11851 <description>Enable/Disable control for PT6</description> 11852 <bitOffset>6</bitOffset> 11853 <bitWidth>1</bitWidth> 11854 <access>read-write</access> 11855 </field> 11856 <field> 11857 <name>pt7</name> 11858 <description>Enable/Disable control for PT7</description> 11859 <bitOffset>7</bitOffset> 11860 <bitWidth>1</bitWidth> 11861 <access>read-write</access> 11862 </field> 11863 </fields> 11864 </register> 11865 <register> 11866 <name>RESYNC</name> 11867 <description>Global Resync (All Pulse Trains) Control</description> 11868 <addressOffset>0x0004</addressOffset> 11869 <access>read-write</access> 11870 <fields> 11871 <field> 11872 <name>pt0</name> 11873 <description>Resync control for PT0</description> 11874 <bitOffset>0</bitOffset> 11875 <bitWidth>1</bitWidth> 11876 <access>read-write</access> 11877 </field> 11878 <field> 11879 <name>pt1</name> 11880 <description>Resync control for PT1</description> 11881 <bitOffset>1</bitOffset> 11882 <bitWidth>1</bitWidth> 11883 <access>read-write</access> 11884 </field> 11885 <field> 11886 <name>pt2</name> 11887 <description>Resync control for PT2</description> 11888 <bitOffset>2</bitOffset> 11889 <bitWidth>1</bitWidth> 11890 <access>read-write</access> 11891 </field> 11892 <field> 11893 <name>pt3</name> 11894 <description>Resync control for PT3</description> 11895 <bitOffset>3</bitOffset> 11896 <bitWidth>1</bitWidth> 11897 <access>read-write</access> 11898 </field> 11899 <field> 11900 <name>pt4</name> 11901 <description>Resync control for PT4</description> 11902 <bitOffset>4</bitOffset> 11903 <bitWidth>1</bitWidth> 11904 <access>read-write</access> 11905 </field> 11906 <field> 11907 <name>pt5</name> 11908 <description>Resync control for PT5</description> 11909 <bitOffset>5</bitOffset> 11910 <bitWidth>1</bitWidth> 11911 <access>read-write</access> 11912 </field> 11913 <field> 11914 <name>pt6</name> 11915 <description>Resync control for PT6</description> 11916 <bitOffset>6</bitOffset> 11917 <bitWidth>1</bitWidth> 11918 <access>read-write</access> 11919 </field> 11920 <field> 11921 <name>pt7</name> 11922 <description>Resync control for PT7</description> 11923 <bitOffset>7</bitOffset> 11924 <bitWidth>1</bitWidth> 11925 <access>read-write</access> 11926 </field> 11927 </fields> 11928 </register> 11929 <register> 11930 <name>INTFL</name> 11931 <description>Pulse Train Interrupt Flags</description> 11932 <addressOffset>0x0008</addressOffset> 11933 <access>read-write</access> 11934 <fields> 11935 <field> 11936 <name>pt0</name> 11937 <description>Pulse Train 0 Stopped Interrupt Flag</description> 11938 <bitOffset>0</bitOffset> 11939 <bitWidth>1</bitWidth> 11940 <access>read-write</access> 11941 </field> 11942 <field> 11943 <name>pt1</name> 11944 <description>Pulse Train 1 Stopped Interrupt Flag</description> 11945 <bitOffset>1</bitOffset> 11946 <bitWidth>1</bitWidth> 11947 <access>read-write</access> 11948 </field> 11949 <field> 11950 <name>pt2</name> 11951 <description>Pulse Train 2 Stopped Interrupt Flag</description> 11952 <bitOffset>2</bitOffset> 11953 <bitWidth>1</bitWidth> 11954 <access>read-write</access> 11955 </field> 11956 <field> 11957 <name>pt3</name> 11958 <description>Pulse Train 3 Stopped Interrupt Flag</description> 11959 <bitOffset>3</bitOffset> 11960 <bitWidth>1</bitWidth> 11961 <access>read-write</access> 11962 </field> 11963 <field> 11964 <name>pt4</name> 11965 <description>Pulse Train 4 Stopped Interrupt Flag</description> 11966 <bitOffset>4</bitOffset> 11967 <bitWidth>1</bitWidth> 11968 <access>read-write</access> 11969 </field> 11970 <field> 11971 <name>pt5</name> 11972 <description>Pulse Train 5 Stopped Interrupt Flag</description> 11973 <bitOffset>5</bitOffset> 11974 <bitWidth>1</bitWidth> 11975 <access>read-write</access> 11976 </field> 11977 <field> 11978 <name>pt6</name> 11979 <description>Pulse Train 6 Stopped Interrupt Flag</description> 11980 <bitOffset>6</bitOffset> 11981 <bitWidth>1</bitWidth> 11982 <access>read-write</access> 11983 </field> 11984 <field> 11985 <name>pt7</name> 11986 <description>Pulse Train 7 Stopped Interrupt Flag</description> 11987 <bitOffset>7</bitOffset> 11988 <bitWidth>1</bitWidth> 11989 <access>read-write</access> 11990 </field> 11991 </fields> 11992 </register> 11993 <register> 11994 <name>INTEN</name> 11995 <description>Pulse Train Interrupt Enable/Disable</description> 11996 <addressOffset>0x000C</addressOffset> 11997 <access>read-write</access> 11998 <fields> 11999 <field> 12000 <name>pt0</name> 12001 <description>Pulse Train 0 Stopped Interrupt Enable/Disable</description> 12002 <bitOffset>0</bitOffset> 12003 <bitWidth>1</bitWidth> 12004 <access>read-write</access> 12005 </field> 12006 <field> 12007 <name>pt1</name> 12008 <description>Pulse Train 1 Stopped Interrupt Enable/Disable</description> 12009 <bitOffset>1</bitOffset> 12010 <bitWidth>1</bitWidth> 12011 <access>read-write</access> 12012 </field> 12013 <field> 12014 <name>pt2</name> 12015 <description>Pulse Train 2 Stopped Interrupt Enable/Disable</description> 12016 <bitOffset>2</bitOffset> 12017 <bitWidth>1</bitWidth> 12018 <access>read-write</access> 12019 </field> 12020 <field> 12021 <name>pt3</name> 12022 <description>Pulse Train 3 Stopped Interrupt Enable/Disable</description> 12023 <bitOffset>3</bitOffset> 12024 <bitWidth>1</bitWidth> 12025 <access>read-write</access> 12026 </field> 12027 <field> 12028 <name>pt4</name> 12029 <description>Pulse Train 4 Stopped Interrupt Enable/Disable</description> 12030 <bitOffset>4</bitOffset> 12031 <bitWidth>1</bitWidth> 12032 <access>read-write</access> 12033 </field> 12034 <field> 12035 <name>pt5</name> 12036 <description>Pulse Train 5 Stopped Interrupt Enable/Disable</description> 12037 <bitOffset>5</bitOffset> 12038 <bitWidth>1</bitWidth> 12039 <access>read-write</access> 12040 </field> 12041 <field> 12042 <name>pt6</name> 12043 <description>Pulse Train 6 Stopped Interrupt Enable/Disable</description> 12044 <bitOffset>6</bitOffset> 12045 <bitWidth>1</bitWidth> 12046 <access>read-write</access> 12047 </field> 12048 <field> 12049 <name>pt7</name> 12050 <description>Pulse Train 7 Stopped Interrupt Enable/Disable</description> 12051 <bitOffset>7</bitOffset> 12052 <bitWidth>1</bitWidth> 12053 <access>read-write</access> 12054 </field> 12055 </fields> 12056 </register> 12057 <register> 12058 <name>SAFE_EN</name> 12059 <description>Pulse Train Global Safe Enable.</description> 12060 <addressOffset>0x0010</addressOffset> 12061 <access>write-only</access> 12062 <fields> 12063 <field> 12064 <name>PT0</name> 12065 <bitOffset>0</bitOffset> 12066 <bitWidth>1</bitWidth> 12067 <access>write-only</access> 12068 </field> 12069 <field> 12070 <name>PT1</name> 12071 <bitOffset>1</bitOffset> 12072 <bitWidth>1</bitWidth> 12073 <access>write-only</access> 12074 </field> 12075 <field> 12076 <name>PT2</name> 12077 <bitOffset>2</bitOffset> 12078 <bitWidth>1</bitWidth> 12079 <access>write-only</access> 12080 </field> 12081 <field> 12082 <name>PT3</name> 12083 <bitOffset>3</bitOffset> 12084 <bitWidth>1</bitWidth> 12085 <access>write-only</access> 12086 </field> 12087 <field> 12088 <name>PT4</name> 12089 <bitOffset>4</bitOffset> 12090 <bitWidth>1</bitWidth> 12091 <access>write-only</access> 12092 </field> 12093 <field> 12094 <name>PT5</name> 12095 <bitOffset>5</bitOffset> 12096 <bitWidth>1</bitWidth> 12097 <access>write-only</access> 12098 </field> 12099 <field> 12100 <name>PT6</name> 12101 <bitOffset>6</bitOffset> 12102 <bitWidth>1</bitWidth> 12103 <access>write-only</access> 12104 </field> 12105 <field> 12106 <name>PT7</name> 12107 <bitOffset>7</bitOffset> 12108 <bitWidth>1</bitWidth> 12109 <access>write-only</access> 12110 </field> 12111 </fields> 12112 </register> 12113 <register> 12114 <name>SAFE_DIS</name> 12115 <description>Pulse Train Global Safe Disable.</description> 12116 <addressOffset>0x0014</addressOffset> 12117 <access>write-only</access> 12118 <fields> 12119 <field> 12120 <name>PT0</name> 12121 <bitOffset>0</bitOffset> 12122 <bitWidth>1</bitWidth> 12123 <access>write-only</access> 12124 </field> 12125 <field> 12126 <name>PT1</name> 12127 <bitOffset>1</bitOffset> 12128 <bitWidth>1</bitWidth> 12129 <access>write-only</access> 12130 </field> 12131 <field> 12132 <name>PT2</name> 12133 <bitOffset>2</bitOffset> 12134 <bitWidth>1</bitWidth> 12135 <access>write-only</access> 12136 </field> 12137 <field> 12138 <name>PT3</name> 12139 <bitOffset>3</bitOffset> 12140 <bitWidth>1</bitWidth> 12141 <access>write-only</access> 12142 </field> 12143 <field> 12144 <name>PT4</name> 12145 <bitOffset>4</bitOffset> 12146 <bitWidth>1</bitWidth> 12147 <access>write-only</access> 12148 </field> 12149 <field> 12150 <name>PT5</name> 12151 <bitOffset>5</bitOffset> 12152 <bitWidth>1</bitWidth> 12153 <access>write-only</access> 12154 </field> 12155 <field> 12156 <name>PT6</name> 12157 <bitOffset>6</bitOffset> 12158 <bitWidth>1</bitWidth> 12159 <access>write-only</access> 12160 </field> 12161 <field> 12162 <name>PT7</name> 12163 <bitOffset>7</bitOffset> 12164 <bitWidth>1</bitWidth> 12165 <access>write-only</access> 12166 </field> 12167 </fields> 12168 </register> 12169 </registers> 12170 </peripheral> 12171<!--PTG Pulse Train Generation--> 12172 <peripheral> 12173 <name>PWRSEQ</name> 12174 <description>Power Sequencer / Low Power Control Register.</description> 12175 <baseAddress>0x40006800</baseAddress> 12176 <addressBlock> 12177 <offset>0x00</offset> 12178 <size>0x400</size> 12179 <usage>registers</usage> 12180 </addressBlock> 12181 <registers> 12182 <register> 12183 <name>LPCN</name> 12184 <description>Low Power Control Register.</description> 12185 <addressOffset>0x00</addressOffset> 12186 <fields> 12187 <field> 12188 <name>RAMRET_EN</name> 12189 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12190 <bitOffset>0</bitOffset> 12191 <bitWidth>2</bitWidth> 12192 </field> 12193 <field> 12194 <name>OVR</name> 12195 <description>Operating Voltage Range</description> 12196 <bitOffset>4</bitOffset> 12197 <bitWidth>2</bitWidth> 12198 <enumeratedValues> 12199 <enumeratedValue> 12200 <name>0_9V</name> 12201 <description>0.9V 24MHz</description> 12202 <value>0</value> 12203 </enumeratedValue> 12204 <enumeratedValue> 12205 <name>1_0V</name> 12206 <description>1.0V 48MHz</description> 12207 <value>1</value> 12208 </enumeratedValue> 12209 <enumeratedValue> 12210 <name>1_1V</name> 12211 <description>1.1V 96MHz</description> 12212 <value>2</value> 12213 </enumeratedValue> 12214 </enumeratedValues> 12215 </field> 12216 <field> 12217 <name>RETREG_EN</name> 12218 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description> 12219 <bitOffset>8</bitOffset> 12220 <bitWidth>1</bitWidth> 12221 <enumeratedValues> 12222 <enumeratedValue> 12223 <name>dis</name> 12224 <description>Disabled.</description> 12225 <value>0</value> 12226 </enumeratedValue> 12227 <enumeratedValue> 12228 <name>en</name> 12229 <description>Enabled.</description> 12230 <value>1</value> 12231 </enumeratedValue> 12232 </enumeratedValues> 12233 </field> 12234 <field> 12235 <name>FASTWK_EN</name> 12236 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). </description> 12237 <bitOffset>10</bitOffset> 12238 <bitWidth>1</bitWidth> 12239 <enumeratedValues> 12240 <enumeratedValue> 12241 <name>dis</name> 12242 <description>Disabled.</description> 12243 <value>0</value> 12244 </enumeratedValue> 12245 <enumeratedValue> 12246 <name>en</name> 12247 <description>Enabled.</description> 12248 <value>1</value> 12249 </enumeratedValue> 12250 </enumeratedValues> 12251 </field> 12252 <field> 12253 <name>BG_DIS</name> 12254 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 12255 <bitOffset>11</bitOffset> 12256 <bitWidth>1</bitWidth> 12257 <enumeratedValues> 12258 <enumeratedValue> 12259 <name>on</name> 12260 <description>Bandgap is always ON.</description> 12261 <value>0</value> 12262 </enumeratedValue> 12263 <enumeratedValue> 12264 <name>off</name> 12265 <description>Bandgap is OFF in DeepSleep mode (default).</description> 12266 <value>1</value> 12267 </enumeratedValue> 12268 </enumeratedValues> 12269 </field> 12270 <field> 12271 <name>VCOREPOR_DIS</name> 12272 <description>VCore Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.</description> 12273 <bitOffset>12</bitOffset> 12274 <bitWidth>1</bitWidth> 12275 <enumeratedValues> 12276 <enumeratedValue> 12277 <name>dis</name> 12278 <description>Disabled.</description> 12279 <value>0</value> 12280 </enumeratedValue> 12281 <enumeratedValue> 12282 <name>en</name> 12283 <description>Enabled.</description> 12284 <value>1</value> 12285 </enumeratedValue> 12286 </enumeratedValues> 12287 </field> 12288 <field> 12289 <name>LDO_DIS</name> 12290 <description>Disable Main LDO</description> 12291 <bitOffset>16</bitOffset> 12292 <bitWidth>1</bitWidth> 12293 </field> 12294 <field> 12295 <name>VCOREMON_DIS</name> 12296 <description>Vcore Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 12297 <bitOffset>20</bitOffset> 12298 <bitWidth>1</bitWidth> 12299 <enumeratedValues> 12300 <enumeratedValue> 12301 <name>en</name> 12302 <description>Enable if Bandgap is ON (default) </description> 12303 <value>0</value> 12304 </enumeratedValue> 12305 <enumeratedValue> 12306 <name>dis</name> 12307 <description>Disabled.</description> 12308 <value>1</value> 12309 </enumeratedValue> 12310 </enumeratedValues> 12311 </field> 12312 <field> 12313 <name>VRTCMON_DIS</name> 12314 <description>VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.</description> 12315 <bitOffset>21</bitOffset> 12316 <bitWidth>1</bitWidth> 12317 <enumeratedValues> 12318 <enumeratedValue> 12319 <name>en</name> 12320 <description>Enable if Bandgap is ON (default) </description> 12321 <value>0</value> 12322 </enumeratedValue> 12323 <enumeratedValue> 12324 <name>dis</name> 12325 <description>Disabled.</description> 12326 <value>1</value> 12327 </enumeratedValue> 12328 </enumeratedValues> 12329 </field> 12330 <field> 12331 <name>VDDAMON_DIS</name> 12332 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 12333 <bitOffset>22</bitOffset> 12334 <bitWidth>1</bitWidth> 12335 <enumeratedValues> 12336 <enumeratedValue> 12337 <name>en</name> 12338 <description>Enable if Bandgap is ON (default) </description> 12339 <value>0</value> 12340 </enumeratedValue> 12341 <enumeratedValue> 12342 <name>dis</name> 12343 <description>Disabled.</description> 12344 <value>1</value> 12345 </enumeratedValue> 12346 </enumeratedValues> 12347 </field> 12348 <field> 12349 <name>VDDIOMON_DIS</name> 12350 <description>VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 12351 <bitOffset>23</bitOffset> 12352 <bitWidth>1</bitWidth> 12353 <enumeratedValues> 12354 <enumeratedValue> 12355 <name>en</name> 12356 <description>Enable if Bandgap is ON (default) </description> 12357 <value>0</value> 12358 </enumeratedValue> 12359 <enumeratedValue> 12360 <name>dis</name> 12361 <description>Disabled.</description> 12362 <value>1</value> 12363 </enumeratedValue> 12364 </enumeratedValues> 12365 </field> 12366 <field> 12367 <name>VDDIOHMON_DIS</name> 12368 <description>VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 12369 <bitOffset>24</bitOffset> 12370 <bitWidth>1</bitWidth> 12371 <enumeratedValues> 12372 <enumeratedValue> 12373 <name>en</name> 12374 <description>Enable if Bandgap is ON (default) </description> 12375 <value>0</value> 12376 </enumeratedValue> 12377 <enumeratedValue> 12378 <name>dis</name> 12379 <description>Disabled.</description> 12380 <value>1</value> 12381 </enumeratedValue> 12382 </enumeratedValues> 12383 </field> 12384 <field> 12385 <name>PORVDDBMON_DIS</name> 12386 <description>VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods.</description> 12387 <bitOffset>27</bitOffset> 12388 <bitWidth>1</bitWidth> 12389 <enumeratedValues> 12390 <enumeratedValue> 12391 <name>dis</name> 12392 <description>Disabled.</description> 12393 <value>0</value> 12394 </enumeratedValue> 12395 <enumeratedValue> 12396 <name>en</name> 12397 <description>Enabled.</description> 12398 <value>1</value> 12399 </enumeratedValue> 12400 </enumeratedValues> 12401 </field> 12402 </fields> 12403 </register> 12404 <register> 12405 <name>LPWKST0</name> 12406 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 12407 <addressOffset>0x04</addressOffset> 12408 <fields> 12409 <field> 12410 <name>ST</name> 12411 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 12412 <bitOffset>0</bitOffset> 12413 <bitWidth>1</bitWidth> 12414 </field> 12415 </fields> 12416 </register> 12417 <register> 12418 <name>LPWKEN0</name> 12419 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 12420 <addressOffset>0x08</addressOffset> 12421 <fields> 12422 <field> 12423 <name>EN</name> 12424 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 12425 <bitOffset>0</bitOffset> 12426 <bitWidth>31</bitWidth> 12427 </field> 12428 </fields> 12429 </register> 12430 <register derivedFrom="LPWKST0"> 12431 <name>LPWKST1</name> 12432 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 12433 <addressOffset>0x0C</addressOffset> 12434 </register> 12435 <register derivedFrom="LPWKEN0"> 12436 <name>LPWKEN1</name> 12437 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 12438 <addressOffset>0x10</addressOffset> 12439 </register> 12440 <register derivedFrom="LPWKST0"> 12441 <name>LPWKST2</name> 12442 <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description> 12443 <addressOffset>0x14</addressOffset> 12444 </register> 12445 <register derivedFrom="LPWKEN0"> 12446 <name>LPWKEN2</name> 12447 <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description> 12448 <addressOffset>0x18</addressOffset> 12449 </register> 12450 <register derivedFrom="LPWKST0"> 12451 <name>LPWKST3</name> 12452 <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description> 12453 <addressOffset>0x1C</addressOffset> 12454 </register> 12455 <register derivedFrom="LPWKEN0"> 12456 <name>LPWKEN3</name> 12457 <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description> 12458 <addressOffset>0x20</addressOffset> 12459 </register> 12460 <register> 12461 <name>LPPWKST</name> 12462 <description>Low Power Peripheral Wakeup Status Register.</description> 12463 <addressOffset>0x30</addressOffset> 12464 <fields> 12465 <field> 12466 <name>USBLS</name> 12467 <description>USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN.</description> 12468 <bitOffset>0</bitOffset> 12469 <bitWidth>2</bitWidth> 12470 </field> 12471 <field> 12472 <name>USBVBUS</name> 12473 <description>USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off.</description> 12474 <bitOffset>2</bitOffset> 12475 <bitWidth>1</bitWidth> 12476 </field> 12477 <field> 12478 <name>HA0</name> 12479 <description>Hardware Accelerator 0 Detect Wakeup Status Flag</description> 12480 <bitOffset>3</bitOffset> 12481 <bitWidth>1</bitWidth> 12482 </field> 12483 <field> 12484 <name>BBMOD</name> 12485 <description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description> 12486 <bitOffset>16</bitOffset> 12487 <bitWidth>1</bitWidth> 12488 </field> 12489 <field> 12490 <name>RST</name> 12491 <description>Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup</description> 12492 <bitOffset>17</bitOffset> 12493 <bitWidth>1</bitWidth> 12494 </field> 12495 <field> 12496 <name>SDMA1</name> 12497 <description>Smart DMA (1) Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transitions from low to high or high to low</description> 12498 <bitOffset>18</bitOffset> 12499 <bitWidth>1</bitWidth> 12500 </field> 12501 </fields> 12502 </register> 12503 <register> 12504 <name>LPPWKEN</name> 12505 <description>Low Power Peripheral Wakeup Enable Register.</description> 12506 <addressOffset>0x34</addressOffset> 12507 <fields> 12508 <field> 12509 <name>USBLS</name> 12510 <description>USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set.</description> 12511 <bitOffset>0</bitOffset> 12512 <bitWidth>2</bitWidth> 12513 </field> 12514 <field> 12515 <name>USBVBUS</name> 12516 <description>USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description> 12517 <bitOffset>2</bitOffset> 12518 <bitWidth>1</bitWidth> 12519 </field> 12520 <field> 12521 <name>SDMA0</name> 12522 <description>Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ.</description> 12523 <bitOffset>3</bitOffset> 12524 <bitWidth>1</bitWidth> 12525 </field> 12526 <field> 12527 <name>SDMA1</name> 12528 <description>Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ.</description> 12529 <bitOffset>18</bitOffset> 12530 <bitWidth>1</bitWidth> 12531 </field> 12532 </fields> 12533 </register> 12534 <register> 12535 <name>LPMEMSD</name> 12536 <description>Low Power Memory Shutdown Control.</description> 12537 <addressOffset>0x40</addressOffset> 12538 <fields> 12539 <field> 12540 <name>RAM0</name> 12541 <description>System RAM block 0 Shut Down.</description> 12542 <bitOffset>0</bitOffset> 12543 <bitWidth>1</bitWidth> 12544 <enumeratedValues> 12545 <enumeratedValue> 12546 <name>normal</name> 12547 <description>Normal Operating Mode.</description> 12548 <value>0</value> 12549 </enumeratedValue> 12550 <enumeratedValue> 12551 <name>shutdown</name> 12552 <description>Shutdown Mode.</description> 12553 <value>1</value> 12554 </enumeratedValue> 12555 </enumeratedValues> 12556 </field> 12557 <field> 12558 <name>RAM1</name> 12559 <description>System RAM block 1 Shut Down.</description> 12560 <bitOffset>1</bitOffset> 12561 <bitWidth>1</bitWidth> 12562 <enumeratedValues> 12563 <enumeratedValue> 12564 <name>normal</name> 12565 <description>Normal Operating Mode.</description> 12566 <value>0</value> 12567 </enumeratedValue> 12568 <enumeratedValue> 12569 <name>shutdown</name> 12570 <description>Shutdown Mode.</description> 12571 <value>1</value> 12572 </enumeratedValue> 12573 </enumeratedValues> 12574 </field> 12575 <field> 12576 <name>RAM2</name> 12577 <description>System RAM block 2 Shut Down.</description> 12578 <bitOffset>2</bitOffset> 12579 <bitWidth>1</bitWidth> 12580 <enumeratedValues> 12581 <enumeratedValue> 12582 <name>normal</name> 12583 <description>Normal Operating Mode.</description> 12584 <value>0</value> 12585 </enumeratedValue> 12586 <enumeratedValue> 12587 <name>shutdown</name> 12588 <description>Shutdown Mode.</description> 12589 <value>1</value> 12590 </enumeratedValue> 12591 </enumeratedValues> 12592 </field> 12593 <field> 12594 <name>RAM3</name> 12595 <description>System RAM block 3 Shut Down.</description> 12596 <bitOffset>3</bitOffset> 12597 <bitWidth>1</bitWidth> 12598 <enumeratedValues> 12599 <enumeratedValue> 12600 <name>normal</name> 12601 <description>Normal Operating Mode.</description> 12602 <value>0</value> 12603 </enumeratedValue> 12604 <enumeratedValue> 12605 <name>shutdown</name> 12606 <description>Shutdown Mode.</description> 12607 <value>1</value> 12608 </enumeratedValue> 12609 </enumeratedValues> 12610 </field> 12611 <field> 12612 <name>RAM4</name> 12613 <description>System RAM block 4 Shut Down.</description> 12614 <bitOffset>4</bitOffset> 12615 <bitWidth>1</bitWidth> 12616 <enumeratedValues> 12617 <enumeratedValue> 12618 <name>normal</name> 12619 <description>Normal Operating Mode.</description> 12620 <value>0</value> 12621 </enumeratedValue> 12622 <enumeratedValue> 12623 <name>shutdown</name> 12624 <description>Shutdown Mode.</description> 12625 <value>1</value> 12626 </enumeratedValue> 12627 </enumeratedValues> 12628 </field> 12629 <field> 12630 <name>RAM5</name> 12631 <description>System RAM block 5 Shut Down.</description> 12632 <bitOffset>5</bitOffset> 12633 <bitWidth>1</bitWidth> 12634 <enumeratedValues> 12635 <enumeratedValue> 12636 <name>normal</name> 12637 <description>Normal Operating Mode.</description> 12638 <value>0</value> 12639 </enumeratedValue> 12640 <enumeratedValue> 12641 <name>shutdown</name> 12642 <description>Shutdown Mode.</description> 12643 <value>1</value> 12644 </enumeratedValue> 12645 </enumeratedValues> 12646 </field> 12647 <field> 12648 <name>ICACHE</name> 12649 <description>Instruction Cache RAM Shut Down.</description> 12650 <bitOffset>7</bitOffset> 12651 <bitWidth>1</bitWidth> 12652 <enumeratedValues> 12653 <enumeratedValue> 12654 <name>normal</name> 12655 <description>Normal Operating Mode.</description> 12656 <value>0</value> 12657 </enumeratedValue> 12658 <enumeratedValue> 12659 <name>shutdown</name> 12660 <description>Shutdown Mode.</description> 12661 <value>1</value> 12662 </enumeratedValue> 12663 </enumeratedValues> 12664 </field> 12665 <field> 12666 <name>ICACHEXIP</name> 12667 <description>XiP Instruction Cache RAM Shut Down.</description> 12668 <bitOffset>8</bitOffset> 12669 <bitWidth>1</bitWidth> 12670 <enumeratedValues> 12671 <enumeratedValue> 12672 <name>normal</name> 12673 <description>Normal Operating Mode.</description> 12674 <value>0</value> 12675 </enumeratedValue> 12676 <enumeratedValue> 12677 <name>shutdown</name> 12678 <description>Shutdown Mode.</description> 12679 <value>1</value> 12680 </enumeratedValue> 12681 </enumeratedValues> 12682 </field> 12683 <field> 12684 <name>SRCC</name> 12685 <description>System Cache RAM Shut Down.</description> 12686 <bitOffset>9</bitOffset> 12687 <bitWidth>1</bitWidth> 12688 <enumeratedValues> 12689 <enumeratedValue> 12690 <name>normal</name> 12691 <description>Normal Operating Mode.</description> 12692 <value>0</value> 12693 </enumeratedValue> 12694 <enumeratedValue> 12695 <name>shutdown</name> 12696 <description>Shutdown Mode.</description> 12697 <value>1</value> 12698 </enumeratedValue> 12699 </enumeratedValues> 12700 </field> 12701 <field> 12702 <name>USBFIFO</name> 12703 <description>USB FIFO Shut Down.</description> 12704 <bitOffset>11</bitOffset> 12705 <bitWidth>1</bitWidth> 12706 <enumeratedValues> 12707 <enumeratedValue> 12708 <name>normal</name> 12709 <description>Normal Operating Mode.</description> 12710 <value>0</value> 12711 </enumeratedValue> 12712 <enumeratedValue> 12713 <name>shutdown</name> 12714 <description>Shutdown Mode.</description> 12715 <value>1</value> 12716 </enumeratedValue> 12717 </enumeratedValues> 12718 </field> 12719 <field> 12720 <name>ROM</name> 12721 <description>ROM Shut Down.</description> 12722 <bitOffset>12</bitOffset> 12723 <bitWidth>1</bitWidth> 12724 <enumeratedValues> 12725 <enumeratedValue> 12726 <name>normal</name> 12727 <description>Normal Operating Mode.</description> 12728 <value>0</value> 12729 </enumeratedValue> 12730 <enumeratedValue> 12731 <name>shutdown</name> 12732 <description>Shutdown Mode.</description> 12733 <value>1</value> 12734 </enumeratedValue> 12735 </enumeratedValues> 12736 </field> 12737 </fields> 12738 </register> 12739 <register> 12740 <name>LPVDDPD</name> 12741 <description>Low Power VDD Domain Power Down Control.</description> 12742 <addressOffset>0x44</addressOffset> 12743 </register> 12744 <register> 12745 <name>GP0</name> 12746 <description>General Purpose Register 0</description> 12747 <addressOffset>0x48</addressOffset> 12748 </register> 12749 <register> 12750 <name>GP1</name> 12751 <description>General Purpose Register 1</description> 12752 <addressOffset>0x4C</addressOffset> 12753 </register> 12754 </registers> 12755 </peripheral> 12756<!--PWRSEQ Power Sequencer / Low Power Control Register.--> 12757 <peripheral> 12758 <name>RTC</name> 12759 <description>Real Time Clock and Alarm.</description> 12760 <baseAddress>0x40006000</baseAddress> 12761 <addressBlock> 12762 <offset>0x00</offset> 12763 <size>0x400</size> 12764 <usage>registers</usage> 12765 </addressBlock> 12766 <interrupt> 12767 <name>RTC</name> 12768 <description>RTC interrupt.</description> 12769 <value>3</value> 12770 </interrupt> 12771 <registers> 12772 <register> 12773 <name>SEC</name> 12774 <description>RTC Second Counter. This register contains the 32-bit second counter.</description> 12775 <addressOffset>0x00</addressOffset> 12776 <resetMask>0x00000000</resetMask> 12777 <fields> 12778 <field> 12779 <name>SEC</name> 12780 <description>Seconds Counter.</description> 12781 <bitOffset>0</bitOffset> 12782 <bitWidth>32</bitWidth> 12783 </field> 12784 </fields> 12785 </register> 12786 <register> 12787 <name>SSEC</name> 12788 <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 12789 <addressOffset>0x04</addressOffset> 12790 <resetMask>0x00000000</resetMask> 12791 <fields> 12792 <field> 12793 <name>SSEC</name> 12794 <description>Sub-Seconds Counter (12-bit).</description> 12795 <bitOffset>0</bitOffset> 12796 <bitWidth>12</bitWidth> 12797 </field> 12798 </fields> 12799 </register> 12800 <register> 12801 <name>TODA</name> 12802 <description>Time-of-day Alarm.</description> 12803 <addressOffset>0x08</addressOffset> 12804 <resetMask>0x00000000</resetMask> 12805 <fields> 12806 <field> 12807 <name>TOD_ALARM</name> 12808 <description>Time-of-day Alarm.</description> 12809 <bitOffset>0</bitOffset> 12810 <bitWidth>20</bitWidth> 12811 </field> 12812 </fields> 12813 </register> 12814 <register> 12815 <name>SSECA</name> 12816 <description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description> 12817 <addressOffset>0x0C</addressOffset> 12818 <resetMask>0x00000000</resetMask> 12819 <fields> 12820 <field> 12821 <name>SSEC_ALARM</name> 12822 <description>This register contains the reload value for the sub-second alarm.</description> 12823 <bitOffset>0</bitOffset> 12824 <bitWidth>32</bitWidth> 12825 </field> 12826 </fields> 12827 </register> 12828 <register> 12829 <name>CTRL</name> 12830 <description>RTC Control Register.</description> 12831 <addressOffset>0x10</addressOffset> 12832 <resetValue>0x00000008</resetValue> 12833 <resetMask>0xFFFFFF38</resetMask> 12834 <fields> 12835 <field> 12836 <name>RTCE</name> 12837 <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 12838 <bitOffset>0</bitOffset> 12839 <bitWidth>1</bitWidth> 12840 <enumeratedValues> 12841 <enumeratedValue> 12842 <name>dis</name> 12843 <description>Disable.</description> 12844 <value>0</value> 12845 </enumeratedValue> 12846 <enumeratedValue> 12847 <name>en</name> 12848 <description>Enable.</description> 12849 <value>1</value> 12850 </enumeratedValue> 12851 </enumeratedValues> 12852 </field> 12853 <field> 12854 <name>ADE</name> 12855 <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 12856 <bitOffset>1</bitOffset> 12857 <bitWidth>1</bitWidth> 12858 <enumeratedValues> 12859 <enumeratedValue> 12860 <name>dis</name> 12861 <description>Disable.</description> 12862 <value>0</value> 12863 </enumeratedValue> 12864 <enumeratedValue> 12865 <name>en</name> 12866 <description>Enable.</description> 12867 <value>1</value> 12868 </enumeratedValue> 12869 </enumeratedValues> 12870 </field> 12871 <field> 12872 <name>ASE</name> 12873 <description>Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 12874 <bitOffset>2</bitOffset> 12875 <bitWidth>1</bitWidth> 12876 <enumeratedValues> 12877 <enumeratedValue> 12878 <name>dis</name> 12879 <description>Disable.</description> 12880 <value>0</value> 12881 </enumeratedValue> 12882 <enumeratedValue> 12883 <name>en</name> 12884 <description>Enable.</description> 12885 <value>1</value> 12886 </enumeratedValue> 12887 </enumeratedValues> 12888 </field> 12889 <field> 12890 <name>BUSY</name> 12891 <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 12892 <bitOffset>3</bitOffset> 12893 <bitWidth>1</bitWidth> 12894 <access>read-only</access> 12895 <enumeratedValues> 12896 <enumeratedValue> 12897 <name>idle</name> 12898 <description>Idle.</description> 12899 <value>0</value> 12900 </enumeratedValue> 12901 <enumeratedValue> 12902 <name>busy</name> 12903 <description>Busy.</description> 12904 <value>1</value> 12905 </enumeratedValue> 12906 </enumeratedValues> 12907 </field> 12908 <field> 12909 <name>RDY</name> 12910 <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description> 12911 <bitOffset>4</bitOffset> 12912 <bitWidth>1</bitWidth> 12913 <enumeratedValues> 12914 <enumeratedValue> 12915 <name>busy</name> 12916 <description>Register has not updated.</description> 12917 <value>0</value> 12918 </enumeratedValue> 12919 <enumeratedValue> 12920 <name>ready</name> 12921 <description>Ready.</description> 12922 <value>1</value> 12923 </enumeratedValue> 12924 </enumeratedValues> 12925 </field> 12926 <field> 12927 <name>RDYE</name> 12928 <description>RTC Ready Interrupt Enable.</description> 12929 <bitOffset>5</bitOffset> 12930 <bitWidth>1</bitWidth> 12931 <enumeratedValues> 12932 <enumeratedValue> 12933 <name>dis</name> 12934 <description>Disable.</description> 12935 <value>0</value> 12936 </enumeratedValue> 12937 <enumeratedValue> 12938 <name>en</name> 12939 <description>Enable.</description> 12940 <value>1</value> 12941 </enumeratedValue> 12942 </enumeratedValues> 12943 </field> 12944 <field> 12945 <name>ALDF</name> 12946 <description>Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 12947 <bitOffset>6</bitOffset> 12948 <bitWidth>1</bitWidth> 12949 <access>read-only</access> 12950 <enumeratedValues> 12951 <enumeratedValue> 12952 <name>inactive</name> 12953 <description>Not active.</description> 12954 <value>0</value> 12955 </enumeratedValue> 12956 <enumeratedValue> 12957 <name>pending</name> 12958 <description>Active.</description> 12959 <value>1</value> 12960 </enumeratedValue> 12961 </enumeratedValues> 12962 </field> 12963 <field> 12964 <name>ALSF</name> 12965 <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 12966 <bitOffset>7</bitOffset> 12967 <bitWidth>1</bitWidth> 12968 <access>read-only</access> 12969 <enumeratedValues> 12970 <enumeratedValue> 12971 <name>inactive</name> 12972 <description>Not active.</description> 12973 <value>0</value> 12974 </enumeratedValue> 12975 <enumeratedValue> 12976 <name>pending</name> 12977 <description>Active.</description> 12978 <value>1</value> 12979 </enumeratedValue> 12980 </enumeratedValues> 12981 </field> 12982 <field> 12983 <name>SQE</name> 12984 <description>Square Wave Output Enable.</description> 12985 <bitOffset>8</bitOffset> 12986 <bitWidth>1</bitWidth> 12987 <enumeratedValues> 12988 <enumeratedValue> 12989 <name>dis</name> 12990 <description>Disable.</description> 12991 <value>0</value> 12992 </enumeratedValue> 12993 <enumeratedValue> 12994 <name>en</name> 12995 <description>Enable.</description> 12996 <value>1</value> 12997 </enumeratedValue> 12998 </enumeratedValues> 12999 </field> 13000 <field> 13001 <name>FT</name> 13002 <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description> 13003 <bitOffset>9</bitOffset> 13004 <bitWidth>2</bitWidth> 13005 <enumeratedValues> 13006 <enumeratedValue> 13007 <name>freq1Hz</name> 13008 <description>1 Hz (Compensated).</description> 13009 <value>0</value> 13010 </enumeratedValue> 13011 <enumeratedValue> 13012 <name>freq512Hz</name> 13013 <description>512 Hz (Compensated).</description> 13014 <value>1</value> 13015 </enumeratedValue> 13016 <enumeratedValue> 13017 <name>freq4KHz</name> 13018 <description>4 KHz.</description> 13019 <value>2</value> 13020 </enumeratedValue> 13021 </enumeratedValues> 13022 </field> 13023 <field> 13024 <name>ACRE</name> 13025 <description>Asynchronous Counter Read Enable.</description> 13026 <bitOffset>14</bitOffset> 13027 <bitWidth>1</bitWidth> 13028 <enumeratedValues> 13029 <enumeratedValue> 13030 <name>sync</name> 13031 <description>Synchronous.</description> 13032 <value>0</value> 13033 </enumeratedValue> 13034 <enumeratedValue> 13035 <name>async</name> 13036 <description>Asynchronous.</description> 13037 <value>1</value> 13038 </enumeratedValue> 13039 </enumeratedValues> 13040 </field> 13041 <field> 13042 <name>WE</name> 13043 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description> 13044 <bitOffset>15</bitOffset> 13045 <bitWidth>1</bitWidth> 13046 <enumeratedValues> 13047 <enumeratedValue> 13048 <name>ignore</name> 13049 <description>Ignored.</description> 13050 <value>0</value> 13051 </enumeratedValue> 13052 <enumeratedValue> 13053 <name>allow</name> 13054 <description>Allowed.</description> 13055 <value>1</value> 13056 </enumeratedValue> 13057 </enumeratedValues> 13058 </field> 13059 </fields> 13060 </register> 13061 <register> 13062 <name>TRIM</name> 13063 <description>RTC Trim Register.</description> 13064 <addressOffset>0x14</addressOffset> 13065 <resetMask>0x00000000</resetMask> 13066 <fields> 13067 <field> 13068 <name>TRIM</name> 13069 <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 13070 <bitOffset>0</bitOffset> 13071 <bitWidth>8</bitWidth> 13072 </field> 13073 <field> 13074 <name>COUNT</name> 13075 <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description> 13076 <bitOffset>8</bitOffset> 13077 <bitWidth>24</bitWidth> 13078 </field> 13079 </fields> 13080 </register> 13081 <register> 13082 <name>OSCCTRL</name> 13083 <description>RTC Oscillator Control Register.</description> 13084 <addressOffset>0x18</addressOffset> 13085 <resetMask>0x00000000</resetMask> 13086 <fields> 13087 <field> 13088 <name>BYPASS</name> 13089 <description>RTC Crystal Bypass</description> 13090 <bitOffset>4</bitOffset> 13091 <bitWidth>1</bitWidth> 13092 <enumeratedValues> 13093 <enumeratedValue> 13094 <name>dis</name> 13095 <description>Disable.</description> 13096 <value>0</value> 13097 </enumeratedValue> 13098 <enumeratedValue> 13099 <name>en</name> 13100 <description>Enable.</description> 13101 <value>1</value> 13102 </enumeratedValue> 13103 </enumeratedValues> 13104 </field> 13105 <field> 13106 <name>32KOUT</name> 13107 <description>RTC 32kHz Square Wave Output</description> 13108 <bitOffset>5</bitOffset> 13109 <bitWidth>1</bitWidth> 13110 <enumeratedValues> 13111 <enumeratedValue> 13112 <name>dis</name> 13113 <description>Disable.</description> 13114 <value>0</value> 13115 </enumeratedValue> 13116 <enumeratedValue> 13117 <name>en</name> 13118 <description>Enable.</description> 13119 <value>1</value> 13120 </enumeratedValue> 13121 </enumeratedValues> 13122 </field> 13123 </fields> 13124 </register> 13125 </registers> 13126 </peripheral> 13127<!--RTC Real Time Clock and Alarm.--> 13128 <peripheral> 13129 <name>SCN</name> 13130 <description>Smart Card Interface.</description> 13131 <groupName>SCN</groupName> 13132 <baseAddress>0x4002C000</baseAddress> 13133 <addressBlock> 13134 <offset>0x00</offset> 13135 <size>0x1000</size> 13136 <usage>registers</usage> 13137 </addressBlock> 13138 <interrupt> 13139 <name>SC0</name> 13140 <description>SC0 IRQ</description> 13141 <value>11</value> 13142 </interrupt> 13143 <registers> 13144 <register> 13145 <name>CR</name> 13146 <description>Control Register.</description> 13147 <addressOffset>0x00</addressOffset> 13148 <fields> 13149 <field> 13150 <name>CONV</name> 13151 <description>Convention Select Bit.</description> 13152 <bitOffset>0</bitOffset> 13153 <bitWidth>1</bitWidth> 13154 </field> 13155 <field> 13156 <name>CREP</name> 13157 <description>Character Repeat Enable Bit.</description> 13158 <bitOffset>1</bitOffset> 13159 <bitWidth>1</bitWidth> 13160 </field> 13161 <field> 13162 <name>WTEN</name> 13163 <description>Wait Time Counter Enable Bit.</description> 13164 <bitOffset>2</bitOffset> 13165 <bitWidth>1</bitWidth> 13166 </field> 13167 <field> 13168 <name>UART</name> 13169 <description>Smart Card Mode Bit.</description> 13170 <bitOffset>3</bitOffset> 13171 <bitWidth>1</bitWidth> 13172 </field> 13173 <field> 13174 <name>CCEN</name> 13175 <description>Clock Counter Enable Bit.</description> 13176 <bitOffset>4</bitOffset> 13177 <bitWidth>1</bitWidth> 13178 </field> 13179 <field> 13180 <name>RXFLUSH</name> 13181 <description>Receive FIFO Flush.</description> 13182 <bitOffset>5</bitOffset> 13183 <bitWidth>1</bitWidth> 13184 </field> 13185 <field> 13186 <name>TXFLUSH</name> 13187 <description>Transmit FIFO Flush.</description> 13188 <bitOffset>6</bitOffset> 13189 <bitWidth>1</bitWidth> 13190 </field> 13191 <field> 13192 <name>RXTHD</name> 13193 <description>Receive FIFO Depth.</description> 13194 <bitOffset>8</bitOffset> 13195 <bitWidth>4</bitWidth> 13196 </field> 13197 <field> 13198 <name>TXTHD</name> 13199 <description>Transmit FIFO Depth.</description> 13200 <bitOffset>12</bitOffset> 13201 <bitWidth>4</bitWidth> 13202 </field> 13203 </fields> 13204 </register> 13205 <register> 13206 <name>SR</name> 13207 <description>Status Register.</description> 13208 <addressOffset>0x04</addressOffset> 13209 <fields> 13210 <field> 13211 <name>PAR</name> 13212 <description>Parity Error Detector Flag.</description> 13213 <bitOffset>0</bitOffset> 13214 <bitWidth>1</bitWidth> 13215 </field> 13216 <field> 13217 <name>WTOV</name> 13218 <description>Waiting Time Counter Overflow.</description> 13219 <bitOffset>1</bitOffset> 13220 <bitWidth>1</bitWidth> 13221 </field> 13222 <field> 13223 <name>CCOV</name> 13224 <description>Clock Counter Overflow Flag.</description> 13225 <bitOffset>2</bitOffset> 13226 <bitWidth>1</bitWidth> 13227 </field> 13228 <field> 13229 <name>TXCF</name> 13230 <description>Transmit Complete Flag.</description> 13231 <bitOffset>3</bitOffset> 13232 <bitWidth>1</bitWidth> 13233 </field> 13234 <field> 13235 <name>RXEMPTY</name> 13236 <description>Receive FIFO Empty Flag.</description> 13237 <bitOffset>4</bitOffset> 13238 <bitWidth>1</bitWidth> 13239 </field> 13240 <field> 13241 <name>RXFULL</name> 13242 <description>Receive FIFO Full Flag.</description> 13243 <bitOffset>5</bitOffset> 13244 <bitWidth>1</bitWidth> 13245 </field> 13246 <field> 13247 <name>TXEMPTY</name> 13248 <description>Transmit FIFO Empty Flag.</description> 13249 <bitOffset>6</bitOffset> 13250 <bitWidth>1</bitWidth> 13251 </field> 13252 <field> 13253 <name>TXFULL</name> 13254 <description>Transmit FIFO Full Flag.</description> 13255 <bitOffset>7</bitOffset> 13256 <bitWidth>1</bitWidth> 13257 </field> 13258 <field> 13259 <name>RXELT</name> 13260 <description>Number of Bytes in the Receive FIFO.</description> 13261 <bitOffset>8</bitOffset> 13262 <bitWidth>4</bitWidth> 13263 </field> 13264 <field> 13265 <name>TXELT</name> 13266 <description>Number of Bytes in the Transmit FIFO.</description> 13267 <bitOffset>12</bitOffset> 13268 <bitWidth>4</bitWidth> 13269 </field> 13270 </fields> 13271 </register> 13272 <register> 13273 <name>PN</name> 13274 <description>Pin Register,</description> 13275 <addressOffset>0x08</addressOffset> 13276 <fields> 13277 <field> 13278 <name>CRDRST</name> 13279 <description>Smart Card Reset Pin Control.</description> 13280 <bitOffset>0</bitOffset> 13281 <bitWidth>1</bitWidth> 13282 </field> 13283 <field> 13284 <name>CRDCLK</name> 13285 <description>Smart Card Clock Piin Control.</description> 13286 <bitOffset>1</bitOffset> 13287 <bitWidth>1</bitWidth> 13288 </field> 13289 <field> 13290 <name>CRDIO</name> 13291 <description>Smart Card IO Pin Control.</description> 13292 <bitOffset>2</bitOffset> 13293 <bitWidth>1</bitWidth> 13294 </field> 13295 <field> 13296 <name>CRDC4</name> 13297 <description>Smart Card SCn_C4 Pin Control.</description> 13298 <bitOffset>3</bitOffset> 13299 <bitWidth>1</bitWidth> 13300 </field> 13301 <field> 13302 <name>CRDC8</name> 13303 <description>Smart Card SCn_C8 Pin Control.</description> 13304 <bitOffset>4</bitOffset> 13305 <bitWidth>1</bitWidth> 13306 </field> 13307 <field> 13308 <name>CLKSEL</name> 13309 <description>Smart Card Clock Select.</description> 13310 <bitOffset>5</bitOffset> 13311 <bitWidth>1</bitWidth> 13312 </field> 13313 </fields> 13314 </register> 13315 <register> 13316 <name>ETUR</name> 13317 <description>ETU Register.</description> 13318 <addressOffset>0x0C</addressOffset> 13319 <fields> 13320 <field> 13321 <name>ETU</name> 13322 <description>Elemental Time Unit Value.</description> 13323 <bitOffset>0</bitOffset> 13324 <bitWidth>15</bitWidth> 13325 </field> 13326 <field> 13327 <name>COMP</name> 13328 <description>Compensation Mode Enable Bit.</description> 13329 <bitOffset>15</bitOffset> 13330 <bitWidth>1</bitWidth> 13331 </field> 13332 <field> 13333 <name>HALF</name> 13334 <description>Half ETU Count Selection Bit.</description> 13335 <bitOffset>16</bitOffset> 13336 <bitWidth>1</bitWidth> 13337 </field> 13338 </fields> 13339 </register> 13340 <register> 13341 <name>GTR</name> 13342 <description>Guard Time Register.</description> 13343 <addressOffset>0x10</addressOffset> 13344 <fields> 13345 <field> 13346 <name>GT</name> 13347 <description>Guard Time.</description> 13348 <bitOffset>0</bitOffset> 13349 <bitWidth>16</bitWidth> 13350 </field> 13351 </fields> 13352 </register> 13353 <register> 13354 <name>WT0R</name> 13355 <description>Waiting Time 0 Register.</description> 13356 <addressOffset>0x14</addressOffset> 13357 <fields> 13358 <field> 13359 <name>WT</name> 13360 <description>Wait Time.</description> 13361 <bitOffset>0</bitOffset> 13362 <bitWidth>32</bitWidth> 13363 </field> 13364 </fields> 13365 </register> 13366 <register> 13367 <name>WT1R</name> 13368 <description>Waiting Time 1 Register.</description> 13369 <addressOffset>0x18</addressOffset> 13370 <fields> 13371 <field> 13372 <name>WT</name> 13373 <description>Wait Time.</description> 13374 <bitOffset>0</bitOffset> 13375 <bitWidth>8</bitWidth> 13376 </field> 13377 </fields> 13378 </register> 13379 <register> 13380 <name>IER</name> 13381 <description>Interrupt Enable Register.</description> 13382 <addressOffset>0x1C</addressOffset> 13383 <fields> 13384 <field> 13385 <name>PARIE</name> 13386 <description>Parity Error Interrupt Enable.</description> 13387 <bitOffset>0</bitOffset> 13388 <bitWidth>1</bitWidth> 13389 </field> 13390 <field> 13391 <name>WTIE</name> 13392 <description>Waiting Time Overflow Interrupt Enable.</description> 13393 <bitOffset>1</bitOffset> 13394 <bitWidth>1</bitWidth> 13395 </field> 13396 <field> 13397 <name>CTIE</name> 13398 <description>Clock Counter Overflow Interrupt Enable.</description> 13399 <bitOffset>2</bitOffset> 13400 <bitWidth>1</bitWidth> 13401 </field> 13402 <field> 13403 <name>TCIE</name> 13404 <description>Character Transmission Completion Interrupt Enable.</description> 13405 <bitOffset>3</bitOffset> 13406 <bitWidth>1</bitWidth> 13407 </field> 13408 <field> 13409 <name>RXEIE</name> 13410 <description>Receive FIFO Empty Interrupt Enable.</description> 13411 <bitOffset>4</bitOffset> 13412 <bitWidth>1</bitWidth> 13413 </field> 13414 <field> 13415 <name>RXTIE</name> 13416 <description>Receive FIFO Threshold Reached Interrupt Enable.</description> 13417 <bitOffset>5</bitOffset> 13418 <bitWidth>1</bitWidth> 13419 </field> 13420 <field> 13421 <name>RXFIE</name> 13422 <description>Receive FIFO Full Interrupt Enable.</description> 13423 <bitOffset>6</bitOffset> 13424 <bitWidth>1</bitWidth> 13425 </field> 13426 <field> 13427 <name>TXEIE</name> 13428 <description>Transmit FIFO Empty Interrupt Enable.</description> 13429 <bitOffset>7</bitOffset> 13430 <bitWidth>1</bitWidth> 13431 </field> 13432 <field> 13433 <name>TXTIE</name> 13434 <description>Transmit FIFO Threshold Reached Interrupt Enable.</description> 13435 <bitOffset>8</bitOffset> 13436 <bitWidth>1</bitWidth> 13437 </field> 13438 </fields> 13439 </register> 13440 <register> 13441 <name>ISR</name> 13442 <description>Interrupt Status Register.</description> 13443 <addressOffset>0x20</addressOffset> 13444 <fields> 13445 <field> 13446 <name>PARIS</name> 13447 <description>Parity Error Interrupt Status Flag.</description> 13448 <bitOffset>0</bitOffset> 13449 <bitWidth>1</bitWidth> 13450 </field> 13451 <field> 13452 <name>WTIS</name> 13453 <description>Waiting Time Overflow Interrupt Status Flag.</description> 13454 <bitOffset>1</bitOffset> 13455 <bitWidth>1</bitWidth> 13456 </field> 13457 <field> 13458 <name>CTIS</name> 13459 <description>Clock Counter Overflow Interrupt Status Flag.</description> 13460 <bitOffset>2</bitOffset> 13461 <bitWidth>1</bitWidth> 13462 </field> 13463 <field> 13464 <name>TCIS</name> 13465 <description>Character Transmission Completion Interrupt Status Flag.</description> 13466 <bitOffset>3</bitOffset> 13467 <bitWidth>1</bitWidth> 13468 </field> 13469 <field> 13470 <name>RXEIS</name> 13471 <description>Receive FIFO Empty Interrupt Status Flag.</description> 13472 <bitOffset>4</bitOffset> 13473 <bitWidth>1</bitWidth> 13474 </field> 13475 <field> 13476 <name>RXTIS</name> 13477 <description>Receive FIFO Threshold Reached Interrupt Status Flag.</description> 13478 <bitOffset>5</bitOffset> 13479 <bitWidth>1</bitWidth> 13480 </field> 13481 <field> 13482 <name>RXFIS</name> 13483 <description>Receive FIFO Full Interrupt Status Flag.</description> 13484 <bitOffset>6</bitOffset> 13485 <bitWidth>1</bitWidth> 13486 </field> 13487 <field> 13488 <name>TXEIS</name> 13489 <description>Transmit FIFO Empty Interrupt Status Flag.</description> 13490 <bitOffset>7</bitOffset> 13491 <bitWidth>1</bitWidth> 13492 </field> 13493 <field> 13494 <name>TXTIS</name> 13495 <description>Transmit FIFO Threshold Reached Interrupt Status Flag.</description> 13496 <bitOffset>8</bitOffset> 13497 <bitWidth>1</bitWidth> 13498 </field> 13499 </fields> 13500 </register> 13501 <register> 13502 <name>TXR</name> 13503 <description>Transmit Register.</description> 13504 <addressOffset>0x24</addressOffset> 13505 <fields> 13506 <field> 13507 <name>DATA</name> 13508 <description>Transmit Data.</description> 13509 <bitOffset>0</bitOffset> 13510 <bitWidth>8</bitWidth> 13511 </field> 13512 </fields> 13513 </register> 13514 <register> 13515 <name>RXR</name> 13516 <description>Receive Register.</description> 13517 <addressOffset>0x28</addressOffset> 13518 <fields> 13519 <field> 13520 <name>DATA</name> 13521 <description>Receive Data.</description> 13522 <bitOffset>0</bitOffset> 13523 <bitWidth>8</bitWidth> 13524 </field> 13525 <field> 13526 <name>PARER</name> 13527 <description>Parity Error Detect Bit.</description> 13528 <bitOffset>8</bitOffset> 13529 <bitWidth>1</bitWidth> 13530 </field> 13531 </fields> 13532 </register> 13533 <register> 13534 <name>CCR</name> 13535 <description>Clock Counter Register,</description> 13536 <addressOffset>0x2C</addressOffset> 13537 <fields> 13538 <field> 13539 <name>CCYC</name> 13540 <description>Number of Clock Cycles to Count.</description> 13541 <bitOffset>0</bitOffset> 13542 <bitWidth>24</bitWidth> 13543 </field> 13544 <field> 13545 <name>MAN</name> 13546 <description>Manual Mode.</description> 13547 <bitOffset>31</bitOffset> 13548 <bitWidth>1</bitWidth> 13549 </field> 13550 </fields> 13551 </register> 13552 </registers> 13553 </peripheral> 13554<!--SCN Smart Card Interface.--> 13555 <peripheral derivedFrom="SCN"> 13556 <name>SCN1</name> 13557 <description>Smart Card Interface. 1</description> 13558 <baseAddress>0x4002D000</baseAddress> 13559 <interrupt> 13560 <name>SCN1</name> 13561 <description>SCN1 IRQ</description> 13562 <value>37</value> 13563 </interrupt> 13564 </peripheral> 13565<!--SCN1 Smart Card Interface. 1--> 13566 <peripheral> 13567 <name>SDHC</name> 13568 <description>SDHC/SDIO Controller</description> 13569 <baseAddress>0x40037000</baseAddress> 13570 <addressBlock> 13571 <offset>0</offset> 13572 <size>0x1000</size> 13573 <usage>registers</usage> 13574 </addressBlock> 13575 <interrupt> 13576 <name>SDHC</name> 13577 <value>66</value> 13578 </interrupt> 13579 <registers> 13580 <register> 13581 <name>SDMA</name> 13582 <description>SDMA System Address / Argument 2.</description> 13583 <addressOffset>0x00</addressOffset> 13584 <size>32</size> 13585 <fields> 13586 <field> 13587 <name>ADDR</name> 13588 <description>SDMA System Address / Argument 2 of Auto CMD23.</description> 13589 <bitOffset>0</bitOffset> 13590 <bitWidth>32</bitWidth> 13591 </field> 13592 </fields> 13593 </register> 13594 <register> 13595 <name>BLK_SIZE</name> 13596 <description>Block Size.</description> 13597 <addressOffset>0x04</addressOffset> 13598 <size>16</size> 13599 <fields> 13600 <field> 13601 <name>TRANS</name> 13602 <description>Transfer Block Size.</description> 13603 <bitOffset>0</bitOffset> 13604 <bitWidth>12</bitWidth> 13605 </field> 13606 <field> 13607 <name>HOST_BUFF</name> 13608 <description>Host SDMA Buffer Boundary.</description> 13609 <bitOffset>12</bitOffset> 13610 <bitWidth>3</bitWidth> 13611 </field> 13612 </fields> 13613 </register> 13614 <register> 13615 <name>BLK_CNT</name> 13616 <description>Block Count.</description> 13617 <addressOffset>0x06</addressOffset> 13618 <size>16</size> 13619 <fields> 13620 <field> 13621 <name>TRANS</name> 13622 <description>Blocks Count For Current Transfer.</description> 13623 <bitOffset>0</bitOffset> 13624 <bitWidth>16</bitWidth> 13625 </field> 13626 </fields> 13627 </register> 13628 <register> 13629 <name>ARG_1</name> 13630 <description>Argument 1.</description> 13631 <addressOffset>0x08</addressOffset> 13632 <size>32</size> 13633 <fields> 13634 <field> 13635 <name>CMD</name> 13636 <description>Command Argument 1.</description> 13637 <bitOffset>0</bitOffset> 13638 <bitWidth>32</bitWidth> 13639 </field> 13640 </fields> 13641 </register> 13642 <register> 13643 <name>TRANS</name> 13644 <description>Transfer Mode.</description> 13645 <addressOffset>0x0C</addressOffset> 13646 <size>16</size> 13647 <fields> 13648 <field> 13649 <name>DMA_EN</name> 13650 <description>DMA Enable.</description> 13651 <bitOffset>0</bitOffset> 13652 <bitWidth>1</bitWidth> 13653 <enumeratedValues> 13654 <name>enable</name> 13655 <enumeratedValue> 13656 <name>dma_transfer</name> 13657 <value>1</value> 13658 </enumeratedValue> 13659 <enumeratedValue> 13660 <name>non_dma_transfer</name> 13661 <value>0</value> 13662 </enumeratedValue> 13663 </enumeratedValues> 13664 </field> 13665 <field> 13666 <name>BLK_CNT_EN</name> 13667 <description>Block Count Enable.</description> 13668 <bitOffset>1</bitOffset> 13669 <bitWidth>1</bitWidth> 13670 <enumeratedValues> 13671 <name>count</name> 13672 <enumeratedValue> 13673 <name>enable</name> 13674 <value>1</value> 13675 </enumeratedValue> 13676 <enumeratedValue> 13677 <name>disable</name> 13678 <value>0</value> 13679 </enumeratedValue> 13680 </enumeratedValues> 13681 </field> 13682 <field> 13683 <name>AUTO_CMD_EN</name> 13684 <description>Auto CMD Enable.</description> 13685 <bitOffset>2</bitOffset> 13686 <bitWidth>2</bitWidth> 13687 <enumeratedValues> 13688 <name>CMD</name> 13689 <enumeratedValue> 13690 <name>disable</name> 13691 <value>0</value> 13692 </enumeratedValue> 13693 <enumeratedValue> 13694 <name>cmd12</name> 13695 <value>1</value> 13696 </enumeratedValue> 13697 <enumeratedValue> 13698 <name>cmd23</name> 13699 <value>2</value> 13700 </enumeratedValue> 13701 </enumeratedValues> 13702 </field> 13703 <field> 13704 <name>READ_WRITE</name> 13705 <description>Data Transfer Direction Select.</description> 13706 <bitOffset>4</bitOffset> 13707 <bitWidth>1</bitWidth> 13708 <enumeratedValues> 13709 <name>read</name> 13710 <enumeratedValue> 13711 <name>read</name> 13712 <value>1</value> 13713 </enumeratedValue> 13714 <enumeratedValue> 13715 <name>write</name> 13716 <value>0</value> 13717 </enumeratedValue> 13718 </enumeratedValues> 13719 </field> 13720 <field> 13721 <name>MULTI</name> 13722 <description>Multi / Single Block Select.</description> 13723 <bitOffset>5</bitOffset> 13724 <bitWidth>1</bitWidth> 13725 <enumeratedValues> 13726 <name>multi</name> 13727 <enumeratedValue> 13728 <name>enable</name> 13729 <value>1</value> 13730 </enumeratedValue> 13731 <enumeratedValue> 13732 <name>disable</name> 13733 <value>0</value> 13734 </enumeratedValue> 13735 </enumeratedValues> 13736 </field> 13737 </fields> 13738 </register> 13739 <register> 13740 <name>CMD</name> 13741 <description>Command.</description> 13742 <addressOffset>0x0E</addressOffset> 13743 <size>16</size> 13744 <fields> 13745 <field> 13746 <name>RESP_TYPE</name> 13747 <description>Response Type Select.</description> 13748 <bitOffset>0</bitOffset> 13749 <bitWidth>2</bitWidth> 13750 </field> 13751 <field> 13752 <name>CRC_CHK_EN</name> 13753 <description>Command CRC Check Enable.</description> 13754 <bitOffset>3</bitOffset> 13755 <bitWidth>1</bitWidth> 13756 </field> 13757 <field> 13758 <name>IDX_CHK_EN</name> 13759 <description>Command Index Check Enable.</description> 13760 <bitOffset>4</bitOffset> 13761 <bitWidth>1</bitWidth> 13762 </field> 13763 <field> 13764 <name>DATA_PRES_SEL</name> 13765 <description>Data Present Select.</description> 13766 <bitOffset>5</bitOffset> 13767 <bitWidth>1</bitWidth> 13768 </field> 13769 <field> 13770 <name>TYPE</name> 13771 <description>Command Type.</description> 13772 <bitOffset>6</bitOffset> 13773 <bitWidth>2</bitWidth> 13774 </field> 13775 <field> 13776 <name>IDX</name> 13777 <description>Command Index.</description> 13778 <bitOffset>8</bitOffset> 13779 <bitWidth>6</bitWidth> 13780 </field> 13781 </fields> 13782 </register> 13783 <register> 13784 <dim>4</dim> 13785 <dimIncrement>4</dimIncrement> 13786 <name>RESP[%s]</name> 13787 <description>Response 0 Register 0-7.</description> 13788 <addressOffset>0x010</addressOffset> 13789 <size>32</size> 13790 <fields> 13791 <field> 13792 <name>CMD_RESP</name> 13793 <description>Command Response.</description> 13794 <bitOffset>0</bitOffset> 13795 <bitWidth>32</bitWidth> 13796 </field> 13797 </fields> 13798 </register> 13799 <register> 13800 <name>BUFFER</name> 13801 <description>Buffer Data Port.</description> 13802 <addressOffset>0x20</addressOffset> 13803 <size>32</size> 13804 <fields> 13805 <field> 13806 <name>DATA</name> 13807 <description>Buffer Data.</description> 13808 <bitOffset>0</bitOffset> 13809 <bitWidth>32</bitWidth> 13810 </field> 13811 </fields> 13812 </register> 13813 <register> 13814 <name>PRESENT</name> 13815 <description>Present State.</description> 13816 <addressOffset>0x024</addressOffset> 13817 <size>32</size> 13818 <access>read-only</access> 13819 <fields> 13820 <field> 13821 <name>CMD</name> 13822 <description>Command Inhibit (CMD).</description> 13823 <bitOffset>0</bitOffset> 13824 <bitWidth>1</bitWidth> 13825 <access>read-only</access> 13826 </field> 13827 <field> 13828 <name>DAT</name> 13829 <description>Command Inhibit (DAT).</description> 13830 <bitOffset>1</bitOffset> 13831 <bitWidth>1</bitWidth> 13832 <access>read-only</access> 13833 </field> 13834 <field> 13835 <name>DAT_LINE_ACTIVE</name> 13836 <description>DAT Line Active.</description> 13837 <bitOffset>2</bitOffset> 13838 <bitWidth>1</bitWidth> 13839 <access>read-only</access> 13840 </field> 13841 <field> 13842 <name>RETUNING</name> 13843 <description>Re-Tuning Request.</description> 13844 <bitOffset>3</bitOffset> 13845 <bitWidth>1</bitWidth> 13846 <access>read-only</access> 13847 </field> 13848 <field> 13849 <name>WRITE_TRANSFER</name> 13850 <description>Write Transfer Active.</description> 13851 <bitOffset>8</bitOffset> 13852 <bitWidth>1</bitWidth> 13853 <access>read-only</access> 13854 </field> 13855 <field> 13856 <name>READ_TRANSFER</name> 13857 <description>Read Transfer Active.</description> 13858 <bitOffset>9</bitOffset> 13859 <bitWidth>1</bitWidth> 13860 <access>read-only</access> 13861 </field> 13862 <field> 13863 <name>BUFFER_WRITE</name> 13864 <description>Buffer Write Enable.</description> 13865 <bitOffset>10</bitOffset> 13866 <bitWidth>1</bitWidth> 13867 <access>read-only</access> 13868 </field> 13869 <field> 13870 <name>BUFFER_READ</name> 13871 <description>Buffer Read Enable.</description> 13872 <bitOffset>11</bitOffset> 13873 <bitWidth>1</bitWidth> 13874 <access>read-only</access> 13875 </field> 13876 <field> 13877 <name>CARD_INSERTED</name> 13878 <description>Card Inserted.</description> 13879 <bitOffset>16</bitOffset> 13880 <bitWidth>1</bitWidth> 13881 <access>read-only</access> 13882 </field> 13883 <field> 13884 <name>CARD_STATE</name> 13885 <description>Card State Stable.</description> 13886 <bitOffset>17</bitOffset> 13887 <bitWidth>1</bitWidth> 13888 <access>read-only</access> 13889 </field> 13890 <field> 13891 <name>CARD_DETECT</name> 13892 <description>Card Detect Pin Level.</description> 13893 <bitOffset>18</bitOffset> 13894 <bitWidth>1</bitWidth> 13895 <access>read-only</access> 13896 </field> 13897 <field> 13898 <name>WP</name> 13899 <description>Write Protect Switch Pin Level.</description> 13900 <bitOffset>19</bitOffset> 13901 <bitWidth>1</bitWidth> 13902 <access>read-only</access> 13903 </field> 13904 <field> 13905 <name>DAT_SIGNAL_LEVEL</name> 13906 <description>DAT[3:0] Line Signal Level.</description> 13907 <bitOffset>20</bitOffset> 13908 <bitWidth>4</bitWidth> 13909 </field> 13910 <field> 13911 <name>CMD_SIGNAL_LEVEL</name> 13912 <description>CMD Line Signal Level.</description> 13913 <bitOffset>24</bitOffset> 13914 <bitWidth>1</bitWidth> 13915 </field> 13916 </fields> 13917 </register> 13918 <register> 13919 <name>HOST_CN_1</name> 13920 <description>Host Control 1.</description> 13921 <addressOffset>0x028</addressOffset> 13922 <size>8</size> 13923 <fields> 13924 <field> 13925 <name>LED_CN</name> 13926 <description>LED Control.</description> 13927 <bitOffset>0</bitOffset> 13928 <bitWidth>1</bitWidth> 13929 </field> 13930 <field> 13931 <name>DATA_TRANSFER_WIDTH</name> 13932 <description>Data Transfer Width.</description> 13933 <bitOffset>1</bitOffset> 13934 <bitWidth>1</bitWidth> 13935 </field> 13936 <field> 13937 <name>HS_EN</name> 13938 <description>High Speed Enable.</description> 13939 <bitOffset>2</bitOffset> 13940 <bitWidth>1</bitWidth> 13941 </field> 13942 <field> 13943 <name>DMA_SELECT</name> 13944 <description>DMA Select.</description> 13945 <bitOffset>3</bitOffset> 13946 <bitWidth>2</bitWidth> 13947 </field> 13948 <field> 13949 <name>EXT_DATA_TRANSFER_WIDTH</name> 13950 <description>Extended Data Transfer Width.</description> 13951 <bitOffset>5</bitOffset> 13952 <bitWidth>1</bitWidth> 13953 </field> 13954 <field> 13955 <name>CARD_DETECT_TEST</name> 13956 <description>Card Detect Test Level.</description> 13957 <bitOffset>6</bitOffset> 13958 <bitWidth>1</bitWidth> 13959 </field> 13960 <field> 13961 <name>CARD_DETECT_SIGNAL</name> 13962 <description>Card Detect Signal Selection.</description> 13963 <bitOffset>7</bitOffset> 13964 <bitWidth>1</bitWidth> 13965 </field> 13966 </fields> 13967 </register> 13968 <register> 13969 <name>PWR</name> 13970 <description>Power Control.</description> 13971 <addressOffset>0x029</addressOffset> 13972 <size>8</size> 13973 <fields> 13974 <field> 13975 <name>BUS_POWER</name> 13976 <description>SD Bus Power.</description> 13977 <bitOffset>0</bitOffset> 13978 <bitWidth>1</bitWidth> 13979 </field> 13980 <field> 13981 <name>BUS_VOLT_SEL</name> 13982 <description>SD Bus Voltage Select.</description> 13983 <bitOffset>1</bitOffset> 13984 <bitWidth>3</bitWidth> 13985 </field> 13986 </fields> 13987 </register> 13988 <register> 13989 <name>BLK_GAP</name> 13990 <description>Block Gap Control.</description> 13991 <addressOffset>0x02A</addressOffset> 13992 <size>8</size> 13993 <fields> 13994 <field> 13995 <name>STOP</name> 13996 <description>Stop At Block Gap Request.</description> 13997 <bitOffset>0</bitOffset> 13998 <bitWidth>1</bitWidth> 13999 </field> 14000 <field> 14001 <name>CONT</name> 14002 <description>Continue Request.</description> 14003 <bitOffset>1</bitOffset> 14004 <bitWidth>1</bitWidth> 14005 </field> 14006 <field> 14007 <name>READ_WAIT</name> 14008 <description>Read Wait Control.</description> 14009 <bitOffset>2</bitOffset> 14010 <bitWidth>1</bitWidth> 14011 </field> 14012 <field> 14013 <name>INTR</name> 14014 <description>Interrupt At Block Gap.</description> 14015 <bitOffset>3</bitOffset> 14016 <bitWidth>1</bitWidth> 14017 </field> 14018 </fields> 14019 </register> 14020 <register> 14021 <name>WAKEUP</name> 14022 <description>Wakeup Control.</description> 14023 <addressOffset>0x02B</addressOffset> 14024 <size>8</size> 14025 <fields> 14026 <field> 14027 <name>CARD_INT</name> 14028 <description>Wakeup Event Enable On Card Interrupt.</description> 14029 <bitOffset>0</bitOffset> 14030 <bitWidth>1</bitWidth> 14031 </field> 14032 <field> 14033 <name>CARD_INS</name> 14034 <description>Wakeup Event Enable On SD Card Insertion.</description> 14035 <bitOffset>1</bitOffset> 14036 <bitWidth>1</bitWidth> 14037 </field> 14038 <field> 14039 <name>CARD_REM</name> 14040 <description>Wakeup Event Enable On SD Card Removal.</description> 14041 <bitOffset>2</bitOffset> 14042 <bitWidth>1</bitWidth> 14043 </field> 14044 </fields> 14045 </register> 14046 <register> 14047 <name>CLK_CN</name> 14048 <description>Clock Control.</description> 14049 <addressOffset>0x02C</addressOffset> 14050 <size>16</size> 14051 <fields> 14052 <field> 14053 <name>INTERNAL_CLK_EN</name> 14054 <description>Internal Clock Enable.</description> 14055 <bitOffset>0</bitOffset> 14056 <bitWidth>1</bitWidth> 14057 </field> 14058 <field> 14059 <name>INTERNAL_CLK_STABLE</name> 14060 <description>Internal Clock Stable.</description> 14061 <bitOffset>1</bitOffset> 14062 <bitWidth>1</bitWidth> 14063 <access>read-only</access> 14064 </field> 14065 <field> 14066 <name>SD_CLK_EN</name> 14067 <description>SD Clock Enable.</description> 14068 <bitOffset>2</bitOffset> 14069 <bitWidth>1</bitWidth> 14070 </field> 14071 <field> 14072 <name>CLK_GEN_SEL</name> 14073 <description>Clock Generator Select.</description> 14074 <bitOffset>5</bitOffset> 14075 <bitWidth>1</bitWidth> 14076 <access>read-only</access> 14077 </field> 14078 <field> 14079 <name>UPPER_SDCLK_FREQ_SEL</name> 14080 <description>Upper Bits of SDCLK Frequency Select.</description> 14081 <bitOffset>6</bitOffset> 14082 <bitWidth>2</bitWidth> 14083 </field> 14084 <field> 14085 <name>SDCLK_FREQ_SEL</name> 14086 <description>SDCLK Frequency Select.</description> 14087 <bitOffset>8</bitOffset> 14088 <bitWidth>8</bitWidth> 14089 </field> 14090 </fields> 14091 </register> 14092 <register> 14093 <name>TO</name> 14094 <description>Timeout Control.</description> 14095 <addressOffset>0x02E</addressOffset> 14096 <size>8</size> 14097 <fields> 14098 <field> 14099 <name>DATA_COUNT_VALUE</name> 14100 <description>Data Timeout Counter Value.</description> 14101 <bitOffset>0</bitOffset> 14102 <bitWidth>3</bitWidth> 14103 </field> 14104 </fields> 14105 </register> 14106 <register> 14107 <name>SW_RESET</name> 14108 <description>Software Reset.</description> 14109 <addressOffset>0x02F</addressOffset> 14110 <size>8</size> 14111 <fields> 14112 <field> 14113 <name>RESET_ALL</name> 14114 <description>Software Reset For All.</description> 14115 <bitOffset>0</bitOffset> 14116 <bitWidth>1</bitWidth> 14117 </field> 14118 <field> 14119 <name>RESET_CMD</name> 14120 <description>Software Reset For CMD Line.</description> 14121 <bitOffset>1</bitOffset> 14122 <bitWidth>1</bitWidth> 14123 </field> 14124 <field> 14125 <name>RESET_DAT</name> 14126 <description>Software Reset For DAT Line.</description> 14127 <bitOffset>2</bitOffset> 14128 <bitWidth>1</bitWidth> 14129 </field> 14130 </fields> 14131 </register> 14132 <register> 14133 <name>INT_STAT</name> 14134 <description>Normal Interrupt Status.</description> 14135 <addressOffset>0x030</addressOffset> 14136 <size>16</size> 14137 <fields> 14138 <field> 14139 <name>CMD_COMP</name> 14140 <description>Command Complete.</description> 14141 <bitOffset>0</bitOffset> 14142 <bitWidth>1</bitWidth> 14143 </field> 14144 <field> 14145 <name>TRANS_COMP</name> 14146 <description>Transfer Complete.</description> 14147 <bitOffset>1</bitOffset> 14148 <bitWidth>1</bitWidth> 14149 </field> 14150 <field> 14151 <name>BLK_GAP_EVENT</name> 14152 <description>Block Gap Event.</description> 14153 <bitOffset>2</bitOffset> 14154 <bitWidth>1</bitWidth> 14155 </field> 14156 <field> 14157 <name>DMA</name> 14158 <description>DMA Interrupt.</description> 14159 <bitOffset>3</bitOffset> 14160 <bitWidth>1</bitWidth> 14161 </field> 14162 <field> 14163 <name>BUFF_WR_READY</name> 14164 <description>Buffer Write Ready.</description> 14165 <bitOffset>4</bitOffset> 14166 <bitWidth>1</bitWidth> 14167 </field> 14168 <field> 14169 <name>BUFF_RD_READY</name> 14170 <description>Buffer Read Ready.</description> 14171 <bitOffset>5</bitOffset> 14172 <bitWidth>1</bitWidth> 14173 </field> 14174 <field> 14175 <name>CARD_INSERTION</name> 14176 <description>Card Insertion.</description> 14177 <bitOffset>6</bitOffset> 14178 <bitWidth>1</bitWidth> 14179 </field> 14180 <field> 14181 <name>CARD_REMOVAL</name> 14182 <description>Card Removal.</description> 14183 <bitOffset>7</bitOffset> 14184 <bitWidth>1</bitWidth> 14185 </field> 14186 <field> 14187 <name>CARD_INTR</name> 14188 <description>Card Interrupt.</description> 14189 <bitOffset>8</bitOffset> 14190 <bitWidth>1</bitWidth> 14191 </field> 14192 <field> 14193 <name>RETUNING</name> 14194 <description>Re-Tuning Event.</description> 14195 <bitOffset>12</bitOffset> 14196 <bitWidth>1</bitWidth> 14197 </field> 14198 <field> 14199 <name>ERR_INTR</name> 14200 <description>Error Interrupt.</description> 14201 <bitOffset>15</bitOffset> 14202 <bitWidth>1</bitWidth> 14203 </field> 14204 </fields> 14205 </register> 14206 <register> 14207 <name>ER_INT_STAT</name> 14208 <description>Error Interrupt Status.</description> 14209 <addressOffset>0x032</addressOffset> 14210 <size>16</size> 14211 <fields> 14212 <field> 14213 <name>CMD_TO</name> 14214 <description>Command Timeout Error.</description> 14215 <bitOffset>0</bitOffset> 14216 <bitWidth>1</bitWidth> 14217 </field> 14218 <field> 14219 <name>CMD_CRC</name> 14220 <description>Command CRC Error.</description> 14221 <bitOffset>1</bitOffset> 14222 <bitWidth>1</bitWidth> 14223 </field> 14224 <field> 14225 <name>CMD_END_BIT</name> 14226 <description>Command End Bit Error.</description> 14227 <bitOffset>2</bitOffset> 14228 <bitWidth>1</bitWidth> 14229 </field> 14230 <field> 14231 <name>CMD_IDX</name> 14232 <description>Command Index Error.</description> 14233 <bitOffset>3</bitOffset> 14234 <bitWidth>1</bitWidth> 14235 </field> 14236 <field> 14237 <name>DATA_TO</name> 14238 <description>Data Timeout Error.</description> 14239 <bitOffset>4</bitOffset> 14240 <bitWidth>1</bitWidth> 14241 </field> 14242 <field> 14243 <name>DATA_CRC</name> 14244 <description>Data CRC Error.</description> 14245 <bitOffset>5</bitOffset> 14246 <bitWidth>1</bitWidth> 14247 </field> 14248 <field> 14249 <name>DATA_END_BIT</name> 14250 <description>Data End Bit Error.</description> 14251 <bitOffset>6</bitOffset> 14252 <bitWidth>1</bitWidth> 14253 </field> 14254 <field> 14255 <name>CURRENT_LIMIT</name> 14256 <description>Current Limit Error.</description> 14257 <bitOffset>7</bitOffset> 14258 <bitWidth>1</bitWidth> 14259 </field> 14260 <field> 14261 <name>AUTO_CMD_12</name> 14262 <description>Auto CMD Error.</description> 14263 <bitOffset>8</bitOffset> 14264 <bitWidth>1</bitWidth> 14265 </field> 14266 <field> 14267 <name>ADMA</name> 14268 <description>ADMA Error.</description> 14269 <bitOffset>9</bitOffset> 14270 <bitWidth>1</bitWidth> 14271 </field> 14272 <field> 14273 <name>DMA</name> 14274 <description>DMA Error.</description> 14275 <bitOffset>12</bitOffset> 14276 <bitWidth>1</bitWidth> 14277 </field> 14278 </fields> 14279 </register> 14280 <register> 14281 <name>INT_EN</name> 14282 <description>Normal Interrupt Status Enable.</description> 14283 <addressOffset>0x034</addressOffset> 14284 <size>16</size> 14285 <fields> 14286 <field> 14287 <name>CMD_COMP</name> 14288 <description>Command Complete Status Enable.</description> 14289 <bitOffset>0</bitOffset> 14290 <bitWidth>1</bitWidth> 14291 </field> 14292 <field> 14293 <name>TRANS_COMP</name> 14294 <description>Transfer Complete Status Enable.</description> 14295 <bitOffset>1</bitOffset> 14296 <bitWidth>1</bitWidth> 14297 </field> 14298 <field> 14299 <name>BLK_GAP</name> 14300 <description>Block Gap Event Status Enable.</description> 14301 <bitOffset>2</bitOffset> 14302 <bitWidth>1</bitWidth> 14303 </field> 14304 <field> 14305 <name>DMA</name> 14306 <description>DMA Interrupt Status Enable.</description> 14307 <bitOffset>3</bitOffset> 14308 <bitWidth>1</bitWidth> 14309 </field> 14310 <field> 14311 <name>BUFFER_WR</name> 14312 <description>Buffer Write Ready Status Enable.</description> 14313 <bitOffset>4</bitOffset> 14314 <bitWidth>1</bitWidth> 14315 </field> 14316 <field> 14317 <name>BUFFER_RD</name> 14318 <description>Buffer Read Ready Status Enable.</description> 14319 <bitOffset>5</bitOffset> 14320 <bitWidth>1</bitWidth> 14321 </field> 14322 <field> 14323 <name>CARD_INSERT</name> 14324 <description>Card Insertion Status Enable.</description> 14325 <bitOffset>6</bitOffset> 14326 <bitWidth>1</bitWidth> 14327 </field> 14328 <field> 14329 <name>CARD_REMOVAL</name> 14330 <description>Card Removal Status Enable.</description> 14331 <bitOffset>7</bitOffset> 14332 <bitWidth>1</bitWidth> 14333 </field> 14334 <field> 14335 <name>CARD_INT</name> 14336 <description>Card Interrupt Status Enable.</description> 14337 <bitOffset>8</bitOffset> 14338 <bitWidth>1</bitWidth> 14339 </field> 14340 <field> 14341 <name>RETUNING</name> 14342 <description>Re-Tuning Event Status Enable.</description> 14343 <bitOffset>12</bitOffset> 14344 <bitWidth>1</bitWidth> 14345 </field> 14346 </fields> 14347 </register> 14348 <register> 14349 <name>ER_INT_EN</name> 14350 <description>Error Interrupt Status Enable.</description> 14351 <addressOffset>0x36</addressOffset> 14352 <size>16</size> 14353 <fields> 14354 <field> 14355 <name>CMD_TO</name> 14356 <description>Command Timeout Error Status Enable.</description> 14357 <bitOffset>0</bitOffset> 14358 <bitWidth>1</bitWidth> 14359 </field> 14360 <field> 14361 <name>CMD_CRC</name> 14362 <description>Command CRC Error Status Enable.</description> 14363 <bitOffset>1</bitOffset> 14364 <bitWidth>1</bitWidth> 14365 </field> 14366 <field> 14367 <name>CMD_END_BIT</name> 14368 <description>Command End Bit Error Status Enable.</description> 14369 <bitOffset>2</bitOffset> 14370 <bitWidth>1</bitWidth> 14371 </field> 14372 <field> 14373 <name>CMD_IDX</name> 14374 <description>Command Index Error Status Enable.</description> 14375 <bitOffset>3</bitOffset> 14376 <bitWidth>1</bitWidth> 14377 </field> 14378 <field> 14379 <name>DATA_TO</name> 14380 <description>Data Timeout Error Status Enable.</description> 14381 <bitOffset>4</bitOffset> 14382 <bitWidth>1</bitWidth> 14383 </field> 14384 <field> 14385 <name>DATA_CRC</name> 14386 <description>Data CRC Error Status Enable.</description> 14387 <bitOffset>5</bitOffset> 14388 <bitWidth>1</bitWidth> 14389 </field> 14390 <field> 14391 <name>DATA_END_BIT</name> 14392 <description>Data End Bit Error Status Enable.</description> 14393 <bitOffset>6</bitOffset> 14394 <bitWidth>1</bitWidth> 14395 </field> 14396 <field> 14397 <name>AUTO_CMD</name> 14398 <description>Auto CMD Error Status Enable.</description> 14399 <bitOffset>8</bitOffset> 14400 <bitWidth>1</bitWidth> 14401 </field> 14402 <field> 14403 <name>ADMA</name> 14404 <description>ADMA Error Status Enable.</description> 14405 <bitOffset>9</bitOffset> 14406 <bitWidth>1</bitWidth> 14407 </field> 14408 <field> 14409 <name>TUNING</name> 14410 <description>Tuning Error Status Enable.</description> 14411 <bitOffset>10</bitOffset> 14412 <bitWidth>1</bitWidth> 14413 </field> 14414 <field> 14415 <name>VENDOR</name> 14416 <description>Vendor Specific Error Status Enable.</description> 14417 <bitOffset>12</bitOffset> 14418 <bitWidth>1</bitWidth> 14419 </field> 14420 </fields> 14421 </register> 14422 <register> 14423 <name>INT_SIGNAL</name> 14424 <description>Normal Interrupt Signal Enable.</description> 14425 <addressOffset>0x038</addressOffset> 14426 <size>16</size> 14427 <fields> 14428 <field> 14429 <name>CMD_COMP</name> 14430 <description>Command Complete Signal Enable.</description> 14431 <bitOffset>0</bitOffset> 14432 <bitWidth>1</bitWidth> 14433 </field> 14434 <field> 14435 <name>TRANS_COMP</name> 14436 <description>Transfer Complete Signal Enable.</description> 14437 <bitOffset>1</bitOffset> 14438 <bitWidth>1</bitWidth> 14439 </field> 14440 <field> 14441 <name>BLK_GAP</name> 14442 <description>Block Gap Event Signal Enable.</description> 14443 <bitOffset>2</bitOffset> 14444 <bitWidth>1</bitWidth> 14445 </field> 14446 <field> 14447 <name>DMA</name> 14448 <description>DMA Interrupt Signal Enable.</description> 14449 <bitOffset>3</bitOffset> 14450 <bitWidth>1</bitWidth> 14451 </field> 14452 <field> 14453 <name>BUFFER_WR</name> 14454 <description>Buffer Write Ready Signal Enable.</description> 14455 <bitOffset>4</bitOffset> 14456 <bitWidth>1</bitWidth> 14457 </field> 14458 <field> 14459 <name>BUFFER_RD</name> 14460 <description>Buffer Read Ready Signal Enable.</description> 14461 <bitOffset>5</bitOffset> 14462 <bitWidth>1</bitWidth> 14463 </field> 14464 <field> 14465 <name>CARD_INSERT</name> 14466 <description>Card Insertion Signal Enable.</description> 14467 <bitOffset>6</bitOffset> 14468 <bitWidth>1</bitWidth> 14469 </field> 14470 <field> 14471 <name>CARD_REMOVAL</name> 14472 <description>Card Removal Signal Enable.</description> 14473 <bitOffset>7</bitOffset> 14474 <bitWidth>1</bitWidth> 14475 </field> 14476 <field> 14477 <name>CARD_INT</name> 14478 <description>Card Interrupt Signal Enable.</description> 14479 <bitOffset>8</bitOffset> 14480 <bitWidth>1</bitWidth> 14481 </field> 14482 <field> 14483 <name>RETUNING</name> 14484 <description>Re-Tuning Event Signal Enable.</description> 14485 <bitOffset>12</bitOffset> 14486 <bitWidth>1</bitWidth> 14487 </field> 14488 </fields> 14489 </register> 14490 <register> 14491 <name>ER_INT_SIGNAL</name> 14492 <description>Error Interrupt Signal Enable.</description> 14493 <addressOffset>0x03A</addressOffset> 14494 <size>16</size> 14495 <fields> 14496 <field> 14497 <name>CMD_TO</name> 14498 <description>Command Timeout Error Signal Enable.</description> 14499 <bitOffset>0</bitOffset> 14500 <bitWidth>1</bitWidth> 14501 </field> 14502 <field> 14503 <name>CMD_CRC</name> 14504 <description>Command CRC Error Signal Enable.</description> 14505 <bitOffset>1</bitOffset> 14506 <bitWidth>1</bitWidth> 14507 </field> 14508 <field> 14509 <name>CMD_END_BIT</name> 14510 <description>Command End Bit Error Signal Enable.</description> 14511 <bitOffset>2</bitOffset> 14512 <bitWidth>1</bitWidth> 14513 </field> 14514 <field> 14515 <name>CMD_IDX</name> 14516 <description>Command Index Error Signal Enable.</description> 14517 <bitOffset>3</bitOffset> 14518 <bitWidth>1</bitWidth> 14519 </field> 14520 <field> 14521 <name>DATA_TO</name> 14522 <description>Data Timeout Error Signal Enable.</description> 14523 <bitOffset>4</bitOffset> 14524 <bitWidth>1</bitWidth> 14525 </field> 14526 <field> 14527 <name>DATA_CRC</name> 14528 <description>Data CRC Error Signal Enable.</description> 14529 <bitOffset>5</bitOffset> 14530 <bitWidth>1</bitWidth> 14531 </field> 14532 <field> 14533 <name>DATA_END_BIT</name> 14534 <description>Data End Bit Error Signal Enable.</description> 14535 <bitOffset>6</bitOffset> 14536 <bitWidth>1</bitWidth> 14537 </field> 14538 <field> 14539 <name>CURR_LIM</name> 14540 <description>Current Limit Error Signal Enable.</description> 14541 <bitOffset>7</bitOffset> 14542 <bitWidth>1</bitWidth> 14543 </field> 14544 <field> 14545 <name>AUTO_CMD</name> 14546 <description>Auto CMD Error Signal Enable.</description> 14547 <bitOffset>8</bitOffset> 14548 <bitWidth>1</bitWidth> 14549 </field> 14550 <field> 14551 <name>ADMA</name> 14552 <description>ADMA Error Signal Enable.</description> 14553 <bitOffset>9</bitOffset> 14554 <bitWidth>1</bitWidth> 14555 </field> 14556 <field> 14557 <name>TUNING</name> 14558 <description>Tuning Error Signal Enable.</description> 14559 <bitOffset>10</bitOffset> 14560 <bitWidth>1</bitWidth> 14561 </field> 14562 <field> 14563 <name>TAR_RESP</name> 14564 <description>Target Response Error Signal Enable.</description> 14565 <bitOffset>12</bitOffset> 14566 <bitWidth>1</bitWidth> 14567 </field> 14568 </fields> 14569 </register> 14570 <register> 14571 <name>AUTO_CMD_ER</name> 14572 <description>Auto CMD Error Status.</description> 14573 <addressOffset>0x03C</addressOffset> 14574 <size>16</size> 14575 <fields> 14576 <field> 14577 <name>NOT_EXCUTED</name> 14578 <description>Auto CMD12 Not Executed.</description> 14579 <bitOffset>0</bitOffset> 14580 <bitWidth>1</bitWidth> 14581 </field> 14582 <field> 14583 <name>TO</name> 14584 <description>Auto CMD Timeout Error.</description> 14585 <bitOffset>1</bitOffset> 14586 <bitWidth>1</bitWidth> 14587 </field> 14588 <field> 14589 <name>CRC</name> 14590 <description>Auto CMD CRC Error.</description> 14591 <bitOffset>2</bitOffset> 14592 <bitWidth>1</bitWidth> 14593 </field> 14594 <field> 14595 <name>END_BIT</name> 14596 <description>Auto CMD End Bit Error.</description> 14597 <bitOffset>3</bitOffset> 14598 <bitWidth>1</bitWidth> 14599 </field> 14600 <field> 14601 <name>INDEX</name> 14602 <description>Auto CMD Index Error.</description> 14603 <bitOffset>4</bitOffset> 14604 <bitWidth>1</bitWidth> 14605 </field> 14606 <field> 14607 <name>NOT_ISSUED</name> 14608 <description>Command Not Issued By Auto CMD12 Error.</description> 14609 <bitOffset>7</bitOffset> 14610 <bitWidth>1</bitWidth> 14611 </field> 14612 </fields> 14613 </register> 14614 <register> 14615 <name>HOST_CN_2</name> 14616 <description>Host Control 2.</description> 14617 <addressOffset>0x03E</addressOffset> 14618 <size>16</size> 14619 <fields> 14620 <field> 14621 <name>UHS</name> 14622 <description>UHS Mode Select.</description> 14623 <bitOffset>0</bitOffset> 14624 <bitWidth>2</bitWidth> 14625 </field> 14626 <field> 14627 <name>SIGNAL_V1_8</name> 14628 <description>1.8V Signaling Enable.</description> 14629 <bitOffset>3</bitOffset> 14630 <bitWidth>1</bitWidth> 14631 </field> 14632 <field> 14633 <name>DRIVER_STRENGTH</name> 14634 <description>Driver Strength Select.</description> 14635 <bitOffset>4</bitOffset> 14636 <bitWidth>2</bitWidth> 14637 </field> 14638 <field> 14639 <name>EXCUTE</name> 14640 <description>Execute Tuning.</description> 14641 <bitOffset>6</bitOffset> 14642 <bitWidth>1</bitWidth> 14643 </field> 14644 <field> 14645 <name>SAMPLING_CLK</name> 14646 <description>Sampling Clock Select.</description> 14647 <bitOffset>7</bitOffset> 14648 <bitWidth>1</bitWidth> 14649 </field> 14650 <field> 14651 <name>ASYNCH_INT</name> 14652 <description>Asynchronous Interrupt Enable.</description> 14653 <bitOffset>14</bitOffset> 14654 <bitWidth>1</bitWidth> 14655 </field> 14656 <field> 14657 <name>PRESET_VAL_EN</name> 14658 <description>Preset Value Enable.</description> 14659 <bitOffset>15</bitOffset> 14660 <bitWidth>1</bitWidth> 14661 </field> 14662 </fields> 14663 </register> 14664 <register> 14665 <name>CFG_0</name> 14666 <description>Capabilities 0-31.</description> 14667 <addressOffset>0x040</addressOffset> 14668 <size>32</size> 14669 <access>read-only</access> 14670 <fields> 14671 <field> 14672 <name>TO_CLK_FREQ</name> 14673 <description>Timeout Clock Frequency.</description> 14674 <bitOffset>0</bitOffset> 14675 <bitWidth>6</bitWidth> 14676 <access>read-only</access> 14677 </field> 14678 <field> 14679 <name>TO_CLK_UNIT</name> 14680 <description>Timeout Clock Unit.</description> 14681 <bitOffset>7</bitOffset> 14682 <bitWidth>1</bitWidth> 14683 <access>read-only</access> 14684 </field> 14685 <field> 14686 <name>CLK_FREQ</name> 14687 <description>Base Clock Frequency For SD Clock.</description> 14688 <bitOffset>8</bitOffset> 14689 <bitWidth>8</bitWidth> 14690 <access>read-only</access> 14691 </field> 14692 <field> 14693 <name>MAX_BLK_LEN</name> 14694 <description>Max Block Length.</description> 14695 <bitOffset>16</bitOffset> 14696 <bitWidth>2</bitWidth> 14697 <access>read-only</access> 14698 </field> 14699 <field> 14700 <name>BIT_8</name> 14701 <description>8-bit Support for Embedded Device.</description> 14702 <bitOffset>18</bitOffset> 14703 <bitWidth>1</bitWidth> 14704 <access>read-only</access> 14705 </field> 14706 <field> 14707 <name>ADMA2</name> 14708 <description>ADMA2 Support.</description> 14709 <bitOffset>19</bitOffset> 14710 <bitWidth>1</bitWidth> 14711 <access>read-only</access> 14712 </field> 14713 <field> 14714 <name>HS</name> 14715 <description>High Speed Support.</description> 14716 <bitOffset>21</bitOffset> 14717 <bitWidth>1</bitWidth> 14718 <access>read-only</access> 14719 </field> 14720 <field> 14721 <name>SDMA</name> 14722 <description>SDMA Support.</description> 14723 <bitOffset>22</bitOffset> 14724 <bitWidth>1</bitWidth> 14725 <access>read-only</access> 14726 </field> 14727 <field> 14728 <name>SUSPEND</name> 14729 <description>Suspend/Resume Support.</description> 14730 <bitOffset>23</bitOffset> 14731 <bitWidth>1</bitWidth> 14732 <access>read-only</access> 14733 </field> 14734 <field> 14735 <name>V3_3</name> 14736 <description>Voltage Support 3.3V.</description> 14737 <bitOffset>24</bitOffset> 14738 <bitWidth>1</bitWidth> 14739 <access>read-only</access> 14740 </field> 14741 <field> 14742 <name>V3_0</name> 14743 <description>Voltage Support 3.0V.</description> 14744 <bitOffset>25</bitOffset> 14745 <bitWidth>1</bitWidth> 14746 <access>read-only</access> 14747 </field> 14748 <field> 14749 <name>V1_8</name> 14750 <description>Voltage Support 1.8V.</description> 14751 <bitOffset>26</bitOffset> 14752 <bitWidth>1</bitWidth> 14753 <access>read-only</access> 14754 </field> 14755 <field> 14756 <name>BIT_64_SYS_BUS</name> 14757 <description>64-bit System Bus Support.</description> 14758 <bitOffset>28</bitOffset> 14759 <bitWidth>1</bitWidth> 14760 <access>read-only</access> 14761 </field> 14762 <field> 14763 <name>ASYNC_INT</name> 14764 <description>Asynchronous Interrupt Support.</description> 14765 <bitOffset>29</bitOffset> 14766 <bitWidth>1</bitWidth> 14767 <access>read-only</access> 14768 </field> 14769 <field> 14770 <name>SLOT_TYPE</name> 14771 <description>Slot Type.</description> 14772 <bitOffset>30</bitOffset> 14773 <bitWidth>2</bitWidth> 14774 <access>read-only</access> 14775 </field> 14776 </fields> 14777 </register> 14778 <register> 14779 <name>CFG_1</name> 14780 <description>Capabilities 32-63.</description> 14781 <addressOffset>0x044</addressOffset> 14782 <size>32</size> 14783 <access>read-only</access> 14784 <fields> 14785 <field> 14786 <name>SDR50</name> 14787 <description>SDR50 Support.</description> 14788 <bitOffset>0</bitOffset> 14789 <bitWidth>1</bitWidth> 14790 <access>read-only</access> 14791 </field> 14792 <field> 14793 <name>SDR104</name> 14794 <description>SDR104 Support.</description> 14795 <bitOffset>1</bitOffset> 14796 <bitWidth>0</bitWidth> 14797 <access>read-only</access> 14798 </field> 14799 <field> 14800 <name>DDR50</name> 14801 <description>DDR50 Support.</description> 14802 <bitOffset>2</bitOffset> 14803 <bitWidth>1</bitWidth> 14804 <access>read-only</access> 14805 </field> 14806 <field> 14807 <name>DRIVER_A</name> 14808 <description>Driver Type A Support.</description> 14809 <bitOffset>4</bitOffset> 14810 <bitWidth>1</bitWidth> 14811 <access>read-only</access> 14812 </field> 14813 <field> 14814 <name>DRIVER_C</name> 14815 <description>Driver Type C Support.</description> 14816 <bitOffset>5</bitOffset> 14817 <bitWidth>1</bitWidth> 14818 <access>read-only</access> 14819 </field> 14820 <field> 14821 <name>DRIVER_D</name> 14822 <description>Driver Type D Support.</description> 14823 <bitOffset>6</bitOffset> 14824 <bitWidth>1</bitWidth> 14825 <access>read-only</access> 14826 </field> 14827 <field> 14828 <name>TIMER_CNT_TUNING</name> 14829 <description>Timer Count for Re-Tuning.</description> 14830 <bitOffset>8</bitOffset> 14831 <bitWidth>4</bitWidth> 14832 <access>read-only</access> 14833 </field> 14834 <field> 14835 <name>TUNING_SDR50</name> 14836 <description>Use Tuning for SDR50.</description> 14837 <bitOffset>13</bitOffset> 14838 <bitWidth>1</bitWidth> 14839 <access>read-only</access> 14840 </field> 14841 <field> 14842 <name>RETUNING</name> 14843 <description>Re-Tuning Modes.</description> 14844 <bitOffset>14</bitOffset> 14845 <bitWidth>2</bitWidth> 14846 <access>read-only</access> 14847 </field> 14848 <field> 14849 <name>CLK_MULTI</name> 14850 <description>Clock Multiplier.</description> 14851 <bitOffset>16</bitOffset> 14852 <bitWidth>8</bitWidth> 14853 <access>read-only</access> 14854 </field> 14855 </fields> 14856 </register> 14857 <register> 14858 <name>MAX_CURR_CFG</name> 14859 <description>Maximum Current Capabilities.</description> 14860 <addressOffset>0x048</addressOffset> 14861 <size>32</size> 14862 <access>read-only</access> 14863 <fields> 14864 <field> 14865 <name>V3_3</name> 14866 <description>Maximum Current for 3.3V.</description> 14867 <bitOffset>0</bitOffset> 14868 <bitWidth>8</bitWidth> 14869 <access>read-only</access> 14870 </field> 14871 <field> 14872 <name>V3_0</name> 14873 <description>Maximum Current for 3.0V.</description> 14874 <bitOffset>8</bitOffset> 14875 <bitWidth>8</bitWidth> 14876 <access>read-only</access> 14877 </field> 14878 <field> 14879 <name>V1_8</name> 14880 <description>Maximum Current for 1.8V.</description> 14881 <bitOffset>16</bitOffset> 14882 <bitWidth>8</bitWidth> 14883 <access>read-only</access> 14884 </field> 14885 </fields> 14886 </register> 14887 <register> 14888 <name>FORCE_CMD</name> 14889 <description>Force Event for Auto CMD Error Status.</description> 14890 <addressOffset>0x050</addressOffset> 14891 <size>16</size> 14892 <access>write-only</access> 14893 <fields> 14894 <field> 14895 <name>NOT_EXCU</name> 14896 <description>Force Event for Auto CMD12 Not Executed.</description> 14897 <bitOffset>0</bitOffset> 14898 <bitWidth>1</bitWidth> 14899 <access>write-only</access> 14900 </field> 14901 <field> 14902 <name>TO</name> 14903 <description>Force Event for Auto CMD Timeout Error.</description> 14904 <bitOffset>1</bitOffset> 14905 <bitWidth>1</bitWidth> 14906 <access>write-only</access> 14907 </field> 14908 <field> 14909 <name>CRC</name> 14910 <description>Force Event for Auto CMD CRC Error.</description> 14911 <bitOffset>2</bitOffset> 14912 <bitWidth>1</bitWidth> 14913 <access>write-only</access> 14914 </field> 14915 <field> 14916 <name>END_BIT</name> 14917 <description>Force Event for Auto CMD End Bit Error.</description> 14918 <bitOffset>3</bitOffset> 14919 <bitWidth>1</bitWidth> 14920 <access>write-only</access> 14921 </field> 14922 <field> 14923 <name>INDEX</name> 14924 <description>Force Event for Auto CMD Index Error.</description> 14925 <bitOffset>4</bitOffset> 14926 <bitWidth>1</bitWidth> 14927 <access>write-only</access> 14928 </field> 14929 <field> 14930 <name>NOT_ISSUED</name> 14931 <description>Force Event for Command Not Issued By Auto CMD12 Error.</description> 14932 <bitOffset>7</bitOffset> 14933 <bitWidth>1</bitWidth> 14934 <access>write-only</access> 14935 </field> 14936 </fields> 14937 </register> 14938 <register> 14939 <name>FORCE_EVENT_INT_STAT</name> 14940 <description>Force Event for Error Interrupt Status.</description> 14941 <addressOffset>0x052</addressOffset> 14942 <size>16</size> 14943 <fields> 14944 <field> 14945 <name>CMD_TO</name> 14946 <description>Force Event for Command Timeout Error.</description> 14947 <bitOffset>0</bitOffset> 14948 <bitWidth>1</bitWidth> 14949 <access>read-only</access> 14950 </field> 14951 <field> 14952 <name>CMD_CRC</name> 14953 <description>Force Event for Command CRC Error.</description> 14954 <bitOffset>1</bitOffset> 14955 <bitWidth>1</bitWidth> 14956 <access>read-only</access> 14957 </field> 14958 <field> 14959 <name>CMD_END_BIT</name> 14960 <description>Force Event for Command End Bit Error.</description> 14961 <bitOffset>2</bitOffset> 14962 <bitWidth>1</bitWidth> 14963 <access>read-only</access> 14964 </field> 14965 <field> 14966 <name>CMD_INDEX</name> 14967 <description>Force Event for Command Index Error.</description> 14968 <bitOffset>3</bitOffset> 14969 <bitWidth>1</bitWidth> 14970 <access>read-only</access> 14971 </field> 14972 <field> 14973 <name>DATA_TO</name> 14974 <description>Force Event for Data Timeout Error.</description> 14975 <bitOffset>4</bitOffset> 14976 <bitWidth>1</bitWidth> 14977 <access>read-only</access> 14978 </field> 14979 <field> 14980 <name>DATA_CRC</name> 14981 <description>Force Event for Data CRC Error.</description> 14982 <bitOffset>5</bitOffset> 14983 <bitWidth>1</bitWidth> 14984 <access>read-only</access> 14985 </field> 14986 <field> 14987 <name>DATA_END_BIT</name> 14988 <description>Force Event for Data End Bit Error.</description> 14989 <bitOffset>6</bitOffset> 14990 <bitWidth>1</bitWidth> 14991 <access>read-only</access> 14992 </field> 14993 <field> 14994 <name>CURR_LIMIT</name> 14995 <description>Force Event for Current Limit Error.</description> 14996 <bitOffset>7</bitOffset> 14997 <bitWidth>1</bitWidth> 14998 <access>read-only</access> 14999 </field> 15000 <field> 15001 <name>AUTO_CMD</name> 15002 <description>Force Event for Auto CMD Error.</description> 15003 <bitOffset>8</bitOffset> 15004 <bitWidth>1</bitWidth> 15005 <access>read-only</access> 15006 </field> 15007 <field> 15008 <name>ADMA</name> 15009 <description>Force Event for ADMA Error.</description> 15010 <bitOffset>9</bitOffset> 15011 <bitWidth>1</bitWidth> 15012 </field> 15013 <field> 15014 <name>VENDOR</name> 15015 <description>Force Event for Vendor Specific Error Status.</description> 15016 <bitOffset>12</bitOffset> 15017 <bitWidth>3</bitWidth> 15018 <access>write-only</access> 15019 </field> 15020 </fields> 15021 </register> 15022 <register> 15023 <name>ADMA_ER</name> 15024 <description>ADMA Error Status.</description> 15025 <addressOffset>0x054</addressOffset> 15026 <size>8</size> 15027 <fields> 15028 <field> 15029 <name>STATE</name> 15030 <description>ADMA Error State.</description> 15031 <bitOffset>0</bitOffset> 15032 <bitWidth>2</bitWidth> 15033 </field> 15034 <field> 15035 <name>LEN_MISMATCH</name> 15036 <description>ADMA Length Mismatch Error.</description> 15037 <bitOffset>2</bitOffset> 15038 <bitWidth>1</bitWidth> 15039 </field> 15040 </fields> 15041 </register> 15042 <register> 15043 <name>ADMA_ADDR_0</name> 15044 <description>ADMA System Address 0-31.</description> 15045 <addressOffset>0x058</addressOffset> 15046 <size>32</size> 15047 <fields> 15048 <field> 15049 <name>ADDR</name> 15050 <description>ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).</description> 15051 <bitOffset>0</bitOffset> 15052 <bitWidth>32</bitWidth> 15053 </field> 15054 </fields> 15055 </register> 15056 <register> 15057 <name>ADMA_ADDR_1</name> 15058 <description>ADMA System Address 32-63.</description> 15059 <addressOffset>0x05C</addressOffset> 15060 <size>32</size> 15061 <fields> 15062 <field> 15063 <name>ADDR</name> 15064 <description>ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).</description> 15065 <bitOffset>0</bitOffset> 15066 <bitWidth>32</bitWidth> 15067 </field> 15068 </fields> 15069 </register> 15070 <register> 15071 <name>PRESET_0</name> 15072 <description>Preset Value for Initialization.</description> 15073 <addressOffset>0x060</addressOffset> 15074 <size>16</size> 15075 <access>read-only</access> 15076 <fields> 15077 <field> 15078 <name>SDCLK_FREQ</name> 15079 <description>SDCLK Frequency Select Value.</description> 15080 <bitOffset>0</bitOffset> 15081 <bitWidth>10</bitWidth> 15082 <access>read-only</access> 15083 </field> 15084 <field> 15085 <name>CLK_GEN</name> 15086 <description>Clock Generator Select Value.</description> 15087 <bitOffset>10</bitOffset> 15088 <bitWidth>1</bitWidth> 15089 <access>read-only</access> 15090 </field> 15091 <field> 15092 <name>DRIVER_STRENGTH</name> 15093 <description>Driver Strength Select Value.</description> 15094 <bitOffset>14</bitOffset> 15095 <bitWidth>2</bitWidth> 15096 <access>read-only</access> 15097 </field> 15098 </fields> 15099 </register> 15100 <register> 15101 <name>PRESET_1</name> 15102 <description>Preset Value for Default Speed.</description> 15103 <addressOffset>0x062</addressOffset> 15104 <size>16</size> 15105 <access>read-only</access> 15106 <fields> 15107 <field> 15108 <name>SDCLK_FREQ</name> 15109 <description>SDCLK Frequency Select Value.</description> 15110 <bitOffset>0</bitOffset> 15111 <bitWidth>10</bitWidth> 15112 <access>read-only</access> 15113 </field> 15114 <field> 15115 <name>CLK_GEN</name> 15116 <description>Clock Generator Select Value.</description> 15117 <bitOffset>10</bitOffset> 15118 <bitWidth>1</bitWidth> 15119 <access>read-only</access> 15120 </field> 15121 <field> 15122 <name>DRIVER_STRENGTH</name> 15123 <description>Driver Strength Select Value.</description> 15124 <bitOffset>14</bitOffset> 15125 <bitWidth>2</bitWidth> 15126 <access>read-only</access> 15127 </field> 15128 </fields> 15129 </register> 15130 <register> 15131 <name>PRESET_2</name> 15132 <description>Preset Value for High Speed.</description> 15133 <addressOffset>0x064</addressOffset> 15134 <size>16</size> 15135 <access>read-only</access> 15136 <fields> 15137 <field> 15138 <name>SDCLK_FREQ</name> 15139 <description>SDCLK Frequency Select Value.</description> 15140 <bitOffset>0</bitOffset> 15141 <bitWidth>10</bitWidth> 15142 <access>read-only</access> 15143 </field> 15144 <field> 15145 <name>CLK_GEN</name> 15146 <description>Clock Generator Select Value.</description> 15147 <bitOffset>10</bitOffset> 15148 <bitWidth>1</bitWidth> 15149 <access>read-only</access> 15150 </field> 15151 <field> 15152 <name>DRIVER_STRENGTH</name> 15153 <description>Driver Strength Select Value.</description> 15154 <bitOffset>14</bitOffset> 15155 <bitWidth>2</bitWidth> 15156 <access>read-only</access> 15157 </field> 15158 </fields> 15159 </register> 15160 <register> 15161 <name>PRESET_3</name> 15162 <description>Preset Value for SDR12.</description> 15163 <addressOffset>0x066</addressOffset> 15164 <size>16</size> 15165 <access>read-only</access> 15166 <fields> 15167 <field> 15168 <name>SDCLK_FREQ</name> 15169 <description>SDCLK Frequency Select Value.</description> 15170 <bitOffset>0</bitOffset> 15171 <bitWidth>10</bitWidth> 15172 <access>read-only</access> 15173 </field> 15174 <field> 15175 <name>CLK_GEN</name> 15176 <description>Clock Generator Select Value.</description> 15177 <bitOffset>10</bitOffset> 15178 <bitWidth>1</bitWidth> 15179 <access>read-only</access> 15180 </field> 15181 <field> 15182 <name>DRIVER_STRENGTH</name> 15183 <description>Driver Strength Select Value.</description> 15184 <bitOffset>14</bitOffset> 15185 <bitWidth>2</bitWidth> 15186 <access>read-only</access> 15187 </field> 15188 </fields> 15189 </register> 15190 <register> 15191 <name>PRESET_4</name> 15192 <description>Preset Value for SDR25.</description> 15193 <addressOffset>0x068</addressOffset> 15194 <size>16</size> 15195 <access>read-only</access> 15196 <fields> 15197 <field> 15198 <name>SDCLK_FREQ</name> 15199 <description>SDCLK Frequency Select Value.</description> 15200 <bitOffset>0</bitOffset> 15201 <bitWidth>10</bitWidth> 15202 <access>read-only</access> 15203 </field> 15204 <field> 15205 <name>CLK_GEN</name> 15206 <description>Clock Generator Select Value.</description> 15207 <bitOffset>10</bitOffset> 15208 <bitWidth>1</bitWidth> 15209 <access>read-only</access> 15210 </field> 15211 <field> 15212 <name>DRIVER_STRENGTH</name> 15213 <description>Driver Strength Select Value.</description> 15214 <bitOffset>14</bitOffset> 15215 <bitWidth>2</bitWidth> 15216 <access>read-only</access> 15217 </field> 15218 </fields> 15219 </register> 15220 <register> 15221 <name>PRESET_5</name> 15222 <description>Preset Value for SDR50.</description> 15223 <addressOffset>0x06A</addressOffset> 15224 <size>16</size> 15225 <access>read-only</access> 15226 <fields> 15227 <field> 15228 <name>SDCLK_FREQ</name> 15229 <description>SDCLK Frequency Select Value.</description> 15230 <bitOffset>0</bitOffset> 15231 <bitWidth>10</bitWidth> 15232 <access>read-only</access> 15233 </field> 15234 <field> 15235 <name>CLK_GEN</name> 15236 <description>Clock Generator Select Value.</description> 15237 <bitOffset>10</bitOffset> 15238 <bitWidth>1</bitWidth> 15239 <access>read-only</access> 15240 </field> 15241 <field> 15242 <name>DRIVER_STRENGTH</name> 15243 <description>Driver Strength Select Value.</description> 15244 <bitOffset>14</bitOffset> 15245 <bitWidth>2</bitWidth> 15246 <access>read-only</access> 15247 </field> 15248 </fields> 15249 </register> 15250 <register> 15251 <name>PRESET_6</name> 15252 <description>Preset Value for SDR104.</description> 15253 <addressOffset>0x06C</addressOffset> 15254 <size>16</size> 15255 <access>read-only</access> 15256 <fields> 15257 <field> 15258 <name>SDCLK_FREQ</name> 15259 <description>SDCLK Frequency Select Value.</description> 15260 <bitOffset>0</bitOffset> 15261 <bitWidth>10</bitWidth> 15262 <access>read-only</access> 15263 </field> 15264 <field> 15265 <name>CLK_GEN</name> 15266 <description>Clock Generator Select Value.</description> 15267 <bitOffset>10</bitOffset> 15268 <bitWidth>1</bitWidth> 15269 <access>read-only</access> 15270 </field> 15271 <field> 15272 <name>DRIVER_STRENGTH</name> 15273 <description>Driver Strength Select Value.</description> 15274 <bitOffset>14</bitOffset> 15275 <bitWidth>2</bitWidth> 15276 <access>read-only</access> 15277 </field> 15278 </fields> 15279 </register> 15280 <register> 15281 <name>PRESET_7</name> 15282 <description>Preset Value for DDR50.</description> 15283 <addressOffset>0x06E</addressOffset> 15284 <size>16</size> 15285 <access>read-only</access> 15286 <fields> 15287 <field> 15288 <name>SDCLK_FREQ</name> 15289 <description>SDCLK Frequency Select Value.</description> 15290 <bitOffset>0</bitOffset> 15291 <bitWidth>10</bitWidth> 15292 <access>read-only</access> 15293 </field> 15294 <field> 15295 <name>CLK_GEN</name> 15296 <description>Clock Generator Select Value.</description> 15297 <bitOffset>10</bitOffset> 15298 <bitWidth>1</bitWidth> 15299 <access>read-only</access> 15300 </field> 15301 <field> 15302 <name>DRIVER_STRENGTH</name> 15303 <description>Driver Strength Select Value.</description> 15304 <bitOffset>14</bitOffset> 15305 <bitWidth>2</bitWidth> 15306 <access>read-only</access> 15307 </field> 15308 </fields> 15309 </register> 15310 <register> 15311 <name>SLOT_INT</name> 15312 <description>Slot Interrupt Status.</description> 15313 <addressOffset>0x0FC</addressOffset> 15314 <size>16</size> 15315 <access>read-only</access> 15316 <fields> 15317 <field> 15318 <name>INT_SIGNALS</name> 15319 <description>Interrupt Signal For Each Slot.</description> 15320 <bitOffset>0</bitOffset> 15321 <bitWidth>1</bitWidth> 15322 <access>read-only</access> 15323 </field> 15324 </fields> 15325 </register> 15326 <register> 15327 <name>HOST_CN_VER</name> 15328 <description>Host Controller Version.</description> 15329 <addressOffset>0x0FE</addressOffset> 15330 <size>16</size> 15331 <fields> 15332 <field> 15333 <name>SPEC_VER</name> 15334 <description>Specification Version Number.</description> 15335 <bitOffset>0</bitOffset> 15336 <bitWidth>8</bitWidth> 15337 </field> 15338 <field> 15339 <name>VEND_VER</name> 15340 <description>Vendor Version Number.</description> 15341 <bitOffset>8</bitOffset> 15342 <bitWidth>8</bitWidth> 15343 </field> 15344 </fields> 15345 </register> 15346 </registers> 15347 </peripheral> 15348<!--SDHC SDHC/SDIO Controller--> 15349 <peripheral> 15350 <name>SEMA</name> 15351 <description>The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 15352 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 15353 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 15354 15355 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.</description> 15356 <baseAddress>0x4003E000</baseAddress> 15357 <addressBlock> 15358 <offset>0x00</offset> 15359 <size>0x1000</size> 15360 <usage>registers</usage> 15361 </addressBlock> 15362 <registers> 15363 <register> 15364 <dim>8</dim> 15365 <dimIncrement>0x04</dimIncrement> 15366 <name>SEMAPHORES[%s]</name> 15367 <description>Read to test and set, returns prior value. Write 0 to clear semaphore.</description> 15368 <addressOffset>0x000</addressOffset> 15369 <size>32</size> 15370 <fields> 15371 <field> 15372 <name>sema</name> 15373 <bitOffset>0</bitOffset> 15374 <bitWidth>1</bitWidth> 15375 </field> 15376 </fields> 15377 </register> 15378 <register> 15379 <name>status</name> 15380 <description>Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken.</description> 15381 <addressOffset>0x100</addressOffset> 15382 <size>32</size> 15383 <fields> 15384 <field> 15385 <name>STATUS</name> 15386 <bitOffset>0</bitOffset> 15387 <bitWidth>8</bitWidth> 15388 </field> 15389 </fields> 15390 </register> 15391 </registers> 15392 </peripheral> 15393<!--SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 15394 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 15395 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 15396 15397 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.--> 15398 <peripheral> 15399 <name>SIR</name> 15400 <description>System Initialization Registers.</description> 15401 <baseAddress>0x40000400</baseAddress> 15402 <access>read-only</access> 15403 <addressBlock> 15404 <offset>0x00</offset> 15405 <size>0x400</size> 15406 <usage>registers</usage> 15407 </addressBlock> 15408 <registers> 15409 <register> 15410 <name>SISTAT</name> 15411 <description>System Initialization Status Register.</description> 15412 <addressOffset>0x00</addressOffset> 15413 <access>read-only</access> 15414 <fields> 15415 <field> 15416 <name>MAGIC</name> 15417 <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> 15418 <bitOffset>0</bitOffset> 15419 <bitWidth>1</bitWidth> 15420 <access>read-only</access> 15421 <enumeratedValues> 15422 <usage>read</usage> 15423 <enumeratedValue> 15424 <name>magicNotSet</name> 15425 <description>Magic word was not set (OTP has not been initialized properly).</description> 15426 <value>0</value> 15427 </enumeratedValue> 15428 <enumeratedValue> 15429 <name>magicSet</name> 15430 <description>Magic word was set (OTP contains valid settings).</description> 15431 <value>1</value> 15432 </enumeratedValue> 15433 </enumeratedValues> 15434 </field> 15435 <field> 15436 <name>CRCERR</name> 15437 <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> 15438 <bitOffset>1</bitOffset> 15439 <bitWidth>1</bitWidth> 15440 <access>read-only</access> 15441 <enumeratedValues> 15442 <usage>read</usage> 15443 <enumeratedValue> 15444 <name>noError</name> 15445 <description>No CRC errors occurred during the read of the OTP memory block.</description> 15446 <value>0</value> 15447 </enumeratedValue> 15448 <enumeratedValue> 15449 <name>error</name> 15450 <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> 15451 <value>1</value> 15452 </enumeratedValue> 15453 </enumeratedValues> 15454 </field> 15455 </fields> 15456 </register> 15457 <register> 15458 <name>ERRADDR</name> 15459 <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> 15460 <addressOffset>0x04</addressOffset> 15461 <access>read-only</access> 15462 <fields> 15463 <field> 15464 <name>ERRADDR</name> 15465 <bitOffset>0</bitOffset> 15466 <bitWidth>32</bitWidth> 15467 </field> 15468 </fields> 15469 </register> 15470 <register> 15471 <name>FSTAT</name> 15472 <description>funcstat register.</description> 15473 <addressOffset>0x100</addressOffset> 15474 <access>read-only</access> 15475 <fields> 15476 <field> 15477 <name>FPU</name> 15478 <description>FPU Function.</description> 15479 <bitOffset>0</bitOffset> 15480 <bitWidth>1</bitWidth> 15481 <enumeratedValues> 15482 <enumeratedValue> 15483 <name>no</name> 15484 <value>0</value> 15485 </enumeratedValue> 15486 <enumeratedValue> 15487 <name>yes</name> 15488 <value>1</value> 15489 </enumeratedValue> 15490 </enumeratedValues> 15491 </field> 15492 <field> 15493 <name>USB</name> 15494 <description>USB Device.</description> 15495 <bitOffset>1</bitOffset> 15496 <bitWidth>1</bitWidth> 15497 <enumeratedValues> 15498 <enumeratedValue> 15499 <name>no</name> 15500 <value>0</value> 15501 </enumeratedValue> 15502 <enumeratedValue> 15503 <name>yes</name> 15504 <value>1</value> 15505 </enumeratedValue> 15506 </enumeratedValues> 15507 </field> 15508 <field> 15509 <name>ADC</name> 15510 <description>10-bit Sigma Delta ADC.</description> 15511 <bitOffset>2</bitOffset> 15512 <bitWidth>1</bitWidth> 15513 <enumeratedValues> 15514 <enumeratedValue> 15515 <name>no</name> 15516 <value>0</value> 15517 </enumeratedValue> 15518 <enumeratedValue> 15519 <name>yes</name> 15520 <value>1</value> 15521 </enumeratedValue> 15522 </enumeratedValues> 15523 </field> 15524 <field> 15525 <name>XIP</name> 15526 <description>XiP function.</description> 15527 <bitOffset>3</bitOffset> 15528 <bitWidth>1</bitWidth> 15529 <enumeratedValues> 15530 <enumeratedValue> 15531 <name>no</name> 15532 <value>0</value> 15533 </enumeratedValue> 15534 <enumeratedValue> 15535 <name>yes</name> 15536 <value>1</value> 15537 </enumeratedValue> 15538 </enumeratedValues> 15539 </field> 15540 <field> 15541 <name>SDHC</name> 15542 <description>SDHC function.</description> 15543 <bitOffset>6</bitOffset> 15544 <bitWidth>1</bitWidth> 15545 <enumeratedValues> 15546 <enumeratedValue> 15547 <name>no</name> 15548 <value>0</value> 15549 </enumeratedValue> 15550 <enumeratedValue> 15551 <name>yes</name> 15552 <value>1</value> 15553 </enumeratedValue> 15554 </enumeratedValues> 15555 </field> 15556 <field> 15557 <name>SMPHR</name> 15558 <description>SMPHR function.</description> 15559 <bitOffset>7</bitOffset> 15560 <bitWidth>1</bitWidth> 15561 <enumeratedValues> 15562 <enumeratedValue> 15563 <name>no</name> 15564 <value>0</value> 15565 </enumeratedValue> 15566 <enumeratedValue> 15567 <name>yes</name> 15568 <value>1</value> 15569 </enumeratedValue> 15570 </enumeratedValues> 15571 </field> 15572 <field> 15573 <name>SRCC</name> 15574 <description>SRCC function.</description> 15575 <bitOffset>8</bitOffset> 15576 <bitWidth>1</bitWidth> 15577 <enumeratedValues> 15578 <enumeratedValue> 15579 <name>no</name> 15580 <value>0</value> 15581 </enumeratedValue> 15582 <enumeratedValue> 15583 <name>yes</name> 15584 <value>1</value> 15585 </enumeratedValue> 15586 </enumeratedValues> 15587 </field> 15588 <field> 15589 <name>ADC9</name> 15590 <description>ADC9 function.</description> 15591 <bitOffset>9</bitOffset> 15592 <bitWidth>1</bitWidth> 15593 <enumeratedValues> 15594 <enumeratedValue> 15595 <name>no</name> 15596 <value>0</value> 15597 </enumeratedValue> 15598 <enumeratedValue> 15599 <name>yes</name> 15600 <value>1</value> 15601 </enumeratedValue> 15602 </enumeratedValues> 15603 </field> 15604 <field> 15605 <name>SC</name> 15606 <description>SC function.</description> 15607 <bitOffset>10</bitOffset> 15608 <bitWidth>1</bitWidth> 15609 <enumeratedValues> 15610 <enumeratedValue> 15611 <name>no</name> 15612 <value>0</value> 15613 </enumeratedValue> 15614 <enumeratedValue> 15615 <name>yes</name> 15616 <value>1</value> 15617 </enumeratedValue> 15618 </enumeratedValues> 15619 </field> 15620 <field> 15621 <name>NMI</name> 15622 <description>NMI function.</description> 15623 <bitOffset>12</bitOffset> 15624 <bitWidth>1</bitWidth> 15625 <enumeratedValues> 15626 <enumeratedValue> 15627 <name>no</name> 15628 <value>0</value> 15629 </enumeratedValue> 15630 <enumeratedValue> 15631 <name>yes</name> 15632 <value>1</value> 15633 </enumeratedValue> 15634 </enumeratedValues> 15635 </field> 15636 </fields> 15637 </register> 15638 <register> 15639 <name>SFSTAT</name> 15640 <description>secfuncstat register.</description> 15641 <addressOffset>0x104</addressOffset> 15642 <access>read-only</access> 15643 <fields> 15644 <field> 15645 <name>SBD</name> 15646 <description>SBD function.</description> 15647 <bitOffset>0</bitOffset> 15648 <bitWidth>1</bitWidth> 15649 <enumeratedValues> 15650 <enumeratedValue> 15651 <name>no</name> 15652 <value>0</value> 15653 </enumeratedValue> 15654 <enumeratedValue> 15655 <name>yes</name> 15656 <value>1</value> 15657 </enumeratedValue> 15658 </enumeratedValues> 15659 </field> 15660 <field> 15661 <name>SLD</name> 15662 <description>SLD function.</description> 15663 <bitOffset>1</bitOffset> 15664 <bitWidth>1</bitWidth> 15665 <enumeratedValues> 15666 <enumeratedValue> 15667 <name>no</name> 15668 <value>0</value> 15669 </enumeratedValue> 15670 <enumeratedValue> 15671 <name>yes</name> 15672 <value>1</value> 15673 </enumeratedValue> 15674 </enumeratedValues> 15675 </field> 15676 <field> 15677 <name>TRNGD</name> 15678 <description>TRNG function.</description> 15679 <bitOffset>2</bitOffset> 15680 <bitWidth>1</bitWidth> 15681 <enumeratedValues> 15682 <enumeratedValue> 15683 <name>no</name> 15684 <value>0</value> 15685 </enumeratedValue> 15686 <enumeratedValue> 15687 <name>yes</name> 15688 <value>1</value> 15689 </enumeratedValue> 15690 </enumeratedValues> 15691 </field> 15692 <field> 15693 <name>AESD</name> 15694 <description>AES function.</description> 15695 <bitOffset>3</bitOffset> 15696 <bitWidth>1</bitWidth> 15697 <enumeratedValues> 15698 <enumeratedValue> 15699 <name>no</name> 15700 <value>0</value> 15701 </enumeratedValue> 15702 <enumeratedValue> 15703 <name>yes</name> 15704 <value>1</value> 15705 </enumeratedValue> 15706 </enumeratedValues> 15707 </field> 15708 <field> 15709 <name>SHAD</name> 15710 <description>SHA function.</description> 15711 <bitOffset>4</bitOffset> 15712 <bitWidth>1</bitWidth> 15713 <enumeratedValues> 15714 <enumeratedValue> 15715 <name>no</name> 15716 <value>0</value> 15717 </enumeratedValue> 15718 <enumeratedValue> 15719 <name>yes</name> 15720 <value>1</value> 15721 </enumeratedValue> 15722 </enumeratedValues> 15723 </field> 15724 <field> 15725 <name>SMD</name> 15726 <description>SMD function.</description> 15727 <bitOffset>7</bitOffset> 15728 <bitWidth>1</bitWidth> 15729 <enumeratedValues> 15730 <enumeratedValue> 15731 <name>no</name> 15732 <value>0</value> 15733 </enumeratedValue> 15734 <enumeratedValue> 15735 <name>yes</name> 15736 <value>1</value> 15737 </enumeratedValue> 15738 </enumeratedValues> 15739 </field> 15740 </fields> 15741 </register> 15742 </registers> 15743 </peripheral> 15744<!--SIR System Initialization Registers.--> 15745 <peripheral> 15746 <name>SKBD</name> 15747 <description>Secure Keyboard</description> 15748 <baseAddress>0x40032000</baseAddress> 15749 <addressBlock> 15750 <offset>0x00</offset> 15751 <size>0x1000</size> 15752 <usage>registers</usage> 15753 </addressBlock> 15754 <interrupt> 15755 <name>Secure_Keypad</name> 15756 <description>Secure Keypad interrupt</description> 15757 <value>19</value> 15758 </interrupt> 15759 <registers> 15760 <register> 15761 <name>CR0</name> 15762 <description>Input Output Select Bits. Each bit of IOSEL selects the pin direction for the corresponding KBDIO pin. If IOSEL[0] = 1, KBDIO0 is an output.</description> 15763 <addressOffset>0x00</addressOffset> 15764 <fields> 15765 <field> 15766 <name>KBDIO_0</name> 15767 <description>Input Output Select for KBDIO0 pin.</description> 15768 <bitOffset>0</bitOffset> 15769 <bitWidth>10</bitWidth> 15770 <enumeratedValues> 15771 <enumeratedValue> 15772 <name>input</name> 15773 <description>Input</description> 15774 <value>0</value> 15775 </enumeratedValue> 15776 <enumeratedValue> 15777 <name>output</name> 15778 <description>Output</description> 15779 <value>1</value> 15780 </enumeratedValue> 15781 </enumeratedValues> 15782 </field> 15783 </fields> 15784 </register> 15785 <register> 15786 <name>CR1</name> 15787 <description>Control Register 1</description> 15788 <addressOffset>0x04</addressOffset> 15789 <fields> 15790 <field> 15791 <name>AUTOEN</name> 15792 <description>Automatic Keyboard Scan Enable</description> 15793 <bitOffset>0</bitOffset> 15794 <bitWidth>1</bitWidth> 15795 <enumeratedValues> 15796 <enumeratedValue> 15797 <name>disable</name> 15798 <description>Disable</description> 15799 <value>0</value> 15800 </enumeratedValue> 15801 <enumeratedValue> 15802 <name>enable</name> 15803 <description>Enable</description> 15804 <value>1</value> 15805 </enumeratedValue> 15806 </enumeratedValues> 15807 </field> 15808 <field derivedFrom="AUTOEN"> 15809 <name>CLEAR</name> 15810 <description>Auto Clear Bit</description> 15811 <bitOffset>1</bitOffset> 15812 <bitWidth>1</bitWidth> 15813 </field> 15814 <field> 15815 <name>OUTNB</name> 15816 <description>Output Number. Number of KBDIO pins selected as outputs. NOTE: 15817 Output pins must be allocated contiguously starting with KBDIO0 and continuing through to KBDIO7.</description> 15818 <bitOffset>8</bitOffset> 15819 <bitWidth>3</bitWidth> 15820 </field> 15821 <field> 15822 <name>DBTM</name> 15823 <description>Debounce Time. Number of milliseconds a keypress event must be active before it is considered actual. NOTE: 15824 Debounce time values based on system running from an external 12MHz clock source with PLL0 enabled. Other external crystal values will cause the debounce time to scale linearly.</description> 15825 <bitOffset>13</bitOffset> 15826 <bitWidth>3</bitWidth> 15827 <enumeratedValues> 15828 <enumeratedValue> 15829 <name>time4ms</name> 15830 <description>4.1 ms</description> 15831 <value>0</value> 15832 </enumeratedValue> 15833 <enumeratedValue> 15834 <name>time5ms</name> 15835 <description>5.3 ms</description> 15836 <value>1</value> 15837 </enumeratedValue> 15838 <enumeratedValue> 15839 <name>time6ms</name> 15840 <description>6.5 ms</description> 15841 <value>2</value> 15842 </enumeratedValue> 15843 <enumeratedValue> 15844 <name>time7ms</name> 15845 <description>7.6 ms</description> 15846 <value>3</value> 15847 </enumeratedValue> 15848 <enumeratedValue> 15849 <name>time8ms</name> 15850 <description>8.8 ms</description> 15851 <value>4</value> 15852 </enumeratedValue> 15853 <enumeratedValue> 15854 <name>time10ms</name> 15855 <description>10.0 ms</description> 15856 <value>5</value> 15857 </enumeratedValue> 15858 <enumeratedValue> 15859 <name>time11ms</name> 15860 <description>11.2 ms</description> 15861 <value>6</value> 15862 </enumeratedValue> 15863 <enumeratedValue> 15864 <name>time12ms</name> 15865 <description>12.3 ms</description> 15866 <value>7</value> 15867 </enumeratedValue> 15868 </enumeratedValues> 15869 </field> 15870 </fields> 15871 </register> 15872 <register> 15873 <name>SR</name> 15874 <description>Status Register</description> 15875 <addressOffset>0x08</addressOffset> 15876 <access>read-only</access> 15877 <fields> 15878 <field> 15879 <name>BUSY</name> 15880 <description>Busy bit. This bit is set by hardware when the automatic keyboard scan is enabled and running. This bit is clear at all other times.</description> 15881 <bitOffset>0</bitOffset> 15882 <bitWidth>1</bitWidth> 15883 <enumeratedValues> 15884 <enumeratedValue> 15885 <name>idle</name> 15886 <description>Idle</description> 15887 <value>0</value> 15888 </enumeratedValue> 15889 <enumeratedValue> 15890 <name>busy</name> 15891 <description>Busy</description> 15892 <value>1</value> 15893 </enumeratedValue> 15894 </enumeratedValues> 15895 </field> 15896 </fields> 15897 </register> 15898 <register> 15899 <name>IER</name> 15900 <description>Interrupt Enable Register</description> 15901 <addressOffset>0x0C</addressOffset> 15902 <fields> 15903 <field> 15904 <name>PUSHIE</name> 15905 <description>Push Event Enable Bit. When set, this bit enables an interrupt to be generated on a key push event. Automatic keyboard scan must be enabled.</description> 15906 <bitOffset>0</bitOffset> 15907 <bitWidth>1</bitWidth> 15908 <enumeratedValues> 15909 <enumeratedValue> 15910 <name>disable</name> 15911 <description>Disable</description> 15912 <value>0</value> 15913 </enumeratedValue> 15914 <enumeratedValue> 15915 <name>enable</name> 15916 <description>Enable</description> 15917 <value>1</value> 15918 </enumeratedValue> 15919 </enumeratedValues> 15920 </field> 15921 <field derivedFrom="PUSHIE"> 15922 <name>RELEASEIE</name> 15923 <description>Release Event Enable Bit. When set, this bit enables an interrupt to be generated on a key release event. Automatic keyboard scan must be enabled.</description> 15924 <bitOffset>1</bitOffset> 15925 <bitWidth>1</bitWidth> 15926 </field> 15927 <field derivedFrom="PUSHIE"> 15928 <name>OVERIE</name> 15929 <description>Overrun Event Enable Bit. When set, this bit enables an interrupt to be generated on an overrun event. Automatic keyboard scan must be enabled.</description> 15930 <bitOffset>2</bitOffset> 15931 <bitWidth>1</bitWidth> 15932 </field> 15933 </fields> 15934 </register> 15935 <register> 15936 <name>ISR</name> 15937 <description>Interrupt Status Register</description> 15938 <addressOffset>0x10</addressOffset> 15939 <fields> 15940 <field> 15941 <name>PUSHIS</name> 15942 <description>Push Interrupt Flag. This bit is set by hardware when a key has been pushed. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software.</description> 15943 <bitOffset>0</bitOffset> 15944 <bitWidth>1</bitWidth> 15945 <enumeratedValues> 15946 <enumeratedValue> 15947 <name>inactive</name> 15948 <description>No interrupt is pending.</description> 15949 <value>0</value> 15950 </enumeratedValue> 15951 <enumeratedValue> 15952 <name>pending</name> 15953 <description>An interrupt is pending.</description> 15954 <value>1</value> 15955 </enumeratedValue> 15956 </enumeratedValues> 15957 </field> 15958 <field derivedFrom="PUSHIS"> 15959 <name>RELEASEIS</name> 15960 <description>Release Interrupt Flag. This bit is set by hardware when a key has been released. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software.</description> 15961 <bitOffset>1</bitOffset> 15962 <bitWidth>1</bitWidth> 15963 </field> 15964 <field derivedFrom="PUSHIS"> 15965 <name>OVERIS</name> 15966 <description>Overrun Event Enable Bit. This bit is set by hardware when an overrun event has occurred. If the interrupt is enabled for this flag, a system interrupt will be fired. If the interrupt enable is not set, the flag will be set, but no interrupt will fire. This bit must be cleared by software.</description> 15967 <bitOffset>2</bitOffset> 15968 <bitWidth>1</bitWidth> 15969 </field> 15970 </fields> 15971 </register> 15972 <register> 15973 <dim>4</dim> 15974 <dimIncrement>4</dimIncrement> 15975 <name>EVENT[%s]</name> 15976 <description>Key Register</description> 15977 <addressOffset>0x14</addressOffset> 15978 <access>read-only</access> 15979 <resetValue>0x00000C00</resetValue> 15980 <fields> 15981 <field> 15982 <name>IOIN</name> 15983 <description>IO Input. Input pin of key event.</description> 15984 <bitOffset>0</bitOffset> 15985 <bitWidth>3</bitWidth> 15986 </field> 15987 <field> 15988 <name>IOOUT</name> 15989 <description>IO Output. Output pin of key event.</description> 15990 <bitOffset>5</bitOffset> 15991 <bitWidth>3</bitWidth> 15992 </field> 15993 <field> 15994 <name>PUSH</name> 15995 <description>If set to 1 the key has been released. If set to 0 the key has been pushed.</description> 15996 <bitOffset>10</bitOffset> 15997 <bitWidth>1</bitWidth> 15998 <enumeratedValues> 15999 <enumeratedValue> 16000 <name>pushed</name> 16001 <description>Pushed</description> 16002 <value>0</value> 16003 </enumeratedValue> 16004 <enumeratedValue> 16005 <name>released</name> 16006 <description>Released</description> 16007 <value>1</value> 16008 </enumeratedValue> 16009 </enumeratedValues> 16010 </field> 16011 <field> 16012 <name>READ</name> 16013 <description>If set to 1 this register has been read. If set to 0 the key register has not been read since its last change.</description> 16014 <bitOffset>11</bitOffset> 16015 <bitWidth>1</bitWidth> 16016 <enumeratedValues> 16017 <enumeratedValue> 16018 <name>notRead</name> 16019 <description>This register has not been read since its last change.</description> 16020 <value>0</value> 16021 </enumeratedValue> 16022 <enumeratedValue> 16023 <name>read</name> 16024 <description>This register has been read.</description> 16025 <value>1</value> 16026 </enumeratedValue> 16027 </enumeratedValues> 16028 </field> 16029 <field> 16030 <name>NEXT</name> 16031 <description>If set to 1 one of the next key registers (x+1 to 3) contains a key event.</description> 16032 <bitOffset>12</bitOffset> 16033 <bitWidth>1</bitWidth> 16034 <enumeratedValues> 16035 <enumeratedValue> 16036 <name>none</name> 16037 <description>No more key register contain a key event.</description> 16038 <value>0</value> 16039 </enumeratedValue> 16040 <enumeratedValue> 16041 <name>more</name> 16042 <description>Other key registers contain a key event.</description> 16043 <value>1</value> 16044 </enumeratedValue> 16045 </enumeratedValues> 16046 </field> 16047 </fields> 16048 </register> 16049 </registers> 16050 </peripheral> 16051<!--SKBD Secure Keyboard--> 16052 <peripheral> 16053 <name>SMON</name> 16054 <description>The Security Monitor block used to monitor system threat conditions.</description> 16055 <baseAddress>0x40004000</baseAddress> 16056 <addressBlock> 16057 <offset>0x00</offset> 16058 <size>0x400</size> 16059 <usage>registers</usage> 16060 </addressBlock> 16061 <registers> 16062 <register> 16063 <name>EXTSCN</name> 16064 <description>External Sensor Control Register.</description> 16065 <addressOffset>0x00</addressOffset> 16066 <resetMask>0x3800FFC0</resetMask> 16067 <fields> 16068 <field> 16069 <name>EXTS_EN0</name> 16070 <description>External Sensor Enable for input/output pair 0.</description> 16071 <bitOffset>0</bitOffset> 16072 <bitWidth>1</bitWidth> 16073 <enumeratedValues> 16074 <enumeratedValue> 16075 <name>dis</name> 16076 <description>Disable.</description> 16077 <value>0</value> 16078 </enumeratedValue> 16079 <enumeratedValue> 16080 <name>en</name> 16081 <description>Enable.</description> 16082 <value>1</value> 16083 </enumeratedValue> 16084 </enumeratedValues> 16085 </field> 16086 <field> 16087 <name>EXTS_EN1</name> 16088 <description>External Sensor Enable for input/output pair 1.</description> 16089 <bitOffset>1</bitOffset> 16090 <bitWidth>1</bitWidth> 16091 <enumeratedValues> 16092 <enumeratedValue> 16093 <name>dis</name> 16094 <description>Disable.</description> 16095 <value>0</value> 16096 </enumeratedValue> 16097 <enumeratedValue> 16098 <name>en</name> 16099 <description>Enable.</description> 16100 <value>1</value> 16101 </enumeratedValue> 16102 </enumeratedValues> 16103 </field> 16104 <field> 16105 <name>EXTS_EN2</name> 16106 <description>External Sensor Enable for input/output pair 2.</description> 16107 <bitOffset>2</bitOffset> 16108 <bitWidth>1</bitWidth> 16109 <enumeratedValues> 16110 <enumeratedValue> 16111 <name>dis</name> 16112 <description>Disable.</description> 16113 <value>0</value> 16114 </enumeratedValue> 16115 <enumeratedValue> 16116 <name>en</name> 16117 <description>Enable.</description> 16118 <value>1</value> 16119 </enumeratedValue> 16120 </enumeratedValues> 16121 </field> 16122 <field> 16123 <name>EXTS_EN3</name> 16124 <description>External Sensor Enable for input/output pair 3.</description> 16125 <bitOffset>3</bitOffset> 16126 <bitWidth>1</bitWidth> 16127 <enumeratedValues> 16128 <enumeratedValue> 16129 <name>dis</name> 16130 <description>Disable.</description> 16131 <value>0</value> 16132 </enumeratedValue> 16133 <enumeratedValue> 16134 <name>en</name> 16135 <description>Enable.</description> 16136 <value>1</value> 16137 </enumeratedValue> 16138 </enumeratedValues> 16139 </field> 16140 <field> 16141 <name>EXTS_EN4</name> 16142 <description>External Sensor Enable for input/output pair 4.</description> 16143 <bitOffset>4</bitOffset> 16144 <bitWidth>1</bitWidth> 16145 <enumeratedValues> 16146 <enumeratedValue> 16147 <name>dis</name> 16148 <description>Disable.</description> 16149 <value>0</value> 16150 </enumeratedValue> 16151 <enumeratedValue> 16152 <name>en</name> 16153 <description>Enable.</description> 16154 <value>1</value> 16155 </enumeratedValue> 16156 </enumeratedValues> 16157 </field> 16158 <field> 16159 <name>EXTS_EN5</name> 16160 <description>External Sensor Enable for input/output pair 5.</description> 16161 <bitOffset>5</bitOffset> 16162 <bitWidth>1</bitWidth> 16163 <enumeratedValues> 16164 <enumeratedValue> 16165 <name>dis</name> 16166 <description>Disable.</description> 16167 <value>0</value> 16168 </enumeratedValue> 16169 <enumeratedValue> 16170 <name>en</name> 16171 <description>Enable.</description> 16172 <value>1</value> 16173 </enumeratedValue> 16174 </enumeratedValues> 16175 </field> 16176 <field> 16177 <name>EXTCNT</name> 16178 <description>External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.</description> 16179 <bitOffset>16</bitOffset> 16180 <bitWidth>5</bitWidth> 16181 </field> 16182 <field> 16183 <name>EXTFRQ</name> 16184 <description>External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.</description> 16185 <bitOffset>21</bitOffset> 16186 <bitWidth>3</bitWidth> 16187 <enumeratedValues> 16188 <enumeratedValue> 16189 <name>freq2000Hz</name> 16190 <description>Div 4 (2000Hz).</description> 16191 <value>0</value> 16192 </enumeratedValue> 16193 <enumeratedValue> 16194 <name>freq1000Hz</name> 16195 <description>Div 8 (1000Hz).</description> 16196 <value>1</value> 16197 </enumeratedValue> 16198 <enumeratedValue> 16199 <name>freq500Hz</name> 16200 <description>Div 16 (500Hz).</description> 16201 <value>2</value> 16202 </enumeratedValue> 16203 <enumeratedValue> 16204 <name>freq250Hz</name> 16205 <description>Div 32 (250Hz).</description> 16206 <value>3</value> 16207 </enumeratedValue> 16208 <enumeratedValue> 16209 <name>freq125Hz</name> 16210 <description>Div 64 (125Hz).</description> 16211 <value>4</value> 16212 </enumeratedValue> 16213 <enumeratedValue> 16214 <name>freq63Hz</name> 16215 <description>Div 128 (63Hz).</description> 16216 <value>5</value> 16217 </enumeratedValue> 16218 <enumeratedValue> 16219 <name>freq31Hz</name> 16220 <description>Div 256 (31Hz).</description> 16221 <value>6</value> 16222 </enumeratedValue> 16223 <enumeratedValue> 16224 <name>RFU</name> 16225 <description>Reserved. Do not use.</description> 16226 <value>7</value> 16227 </enumeratedValue> 16228 </enumeratedValues> 16229 </field> 16230 <field> 16231 <name>DIVCLK</name> 16232 <description>Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: 16233 If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.</description> 16234 <bitOffset>24</bitOffset> 16235 <bitWidth>3</bitWidth> 16236 <enumeratedValues> 16237 <enumeratedValue> 16238 <name>div1</name> 16239 <description>Divide by 1 (8000 Hz).</description> 16240 <value>0</value> 16241 </enumeratedValue> 16242 <enumeratedValue> 16243 <name>div2</name> 16244 <description>Divide by 2 (4000 Hz).</description> 16245 <value>1</value> 16246 </enumeratedValue> 16247 <enumeratedValue> 16248 <name>div4</name> 16249 <description>Divide by 4 (2000 Hz).</description> 16250 <value>2</value> 16251 </enumeratedValue> 16252 <enumeratedValue> 16253 <name>div8</name> 16254 <description>Divide by 8 (1000 Hz).</description> 16255 <value>3</value> 16256 </enumeratedValue> 16257 <enumeratedValue> 16258 <name>div16</name> 16259 <description>Divide by 16 (500 Hz).</description> 16260 <value>4</value> 16261 </enumeratedValue> 16262 <enumeratedValue> 16263 <name>div32</name> 16264 <description>Divide by 32 (250 Hz).</description> 16265 <value>5</value> 16266 </enumeratedValue> 16267 <enumeratedValue> 16268 <name>div64</name> 16269 <description>Divide by 64 (125 Hz).</description> 16270 <value>6</value> 16271 </enumeratedValue> 16272 </enumeratedValues> 16273 </field> 16274 <field> 16275 <name>BUSY</name> 16276 <description>Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.</description> 16277 <bitOffset>30</bitOffset> 16278 <bitWidth>1</bitWidth> 16279 <access>read-only</access> 16280 <enumeratedValues> 16281 <enumeratedValue> 16282 <name>idle</name> 16283 <description>Idle.</description> 16284 <value>0</value> 16285 </enumeratedValue> 16286 <enumeratedValue> 16287 <name>busy</name> 16288 <description>Update in Progress.</description> 16289 <value>1</value> 16290 </enumeratedValue> 16291 </enumeratedValues> 16292 </field> 16293 <field> 16294 <name>LOCK</name> 16295 <description>Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 16296 <bitOffset>31</bitOffset> 16297 <bitWidth>1</bitWidth> 16298 <enumeratedValues> 16299 <enumeratedValue> 16300 <name>unlocked</name> 16301 <description>Unlocked.</description> 16302 <value>0</value> 16303 </enumeratedValue> 16304 <enumeratedValue> 16305 <name>locked</name> 16306 <description>Locked.</description> 16307 <value>1</value> 16308 </enumeratedValue> 16309 </enumeratedValues> 16310 </field> 16311 </fields> 16312 </register> 16313 <register> 16314 <name>INTSCN</name> 16315 <description>Internal Sensor Control Register.</description> 16316 <addressOffset>0x04</addressOffset> 16317 <resetMask>0x7F00FFF7</resetMask> 16318 <fields> 16319 <field> 16320 <name>SHIELD_EN</name> 16321 <description>Die Shield Enable.</description> 16322 <bitOffset>0</bitOffset> 16323 <bitWidth>1</bitWidth> 16324 <enumeratedValues> 16325 <enumeratedValue> 16326 <name>dis</name> 16327 <description>Disable.</description> 16328 <value>0</value> 16329 </enumeratedValue> 16330 <enumeratedValue> 16331 <name>en</name> 16332 <description>Enable.</description> 16333 <value>1</value> 16334 </enumeratedValue> 16335 </enumeratedValues> 16336 </field> 16337 <field> 16338 <name>TEMP_EN</name> 16339 <description>Temperature Sensor Enable.</description> 16340 <bitOffset>1</bitOffset> 16341 <bitWidth>1</bitWidth> 16342 <enumeratedValues> 16343 <enumeratedValue> 16344 <name>dis</name> 16345 <description>Disable.</description> 16346 <value>0</value> 16347 </enumeratedValue> 16348 <enumeratedValue> 16349 <name>en</name> 16350 <description>Enable.</description> 16351 <value>1</value> 16352 </enumeratedValue> 16353 </enumeratedValues> 16354 </field> 16355 <field> 16356 <name>VBAT_EN</name> 16357 <description>Battery Monitor Enable.</description> 16358 <bitOffset>2</bitOffset> 16359 <bitWidth>1</bitWidth> 16360 <enumeratedValues> 16361 <enumeratedValue> 16362 <name>dis</name> 16363 <description>Disable.</description> 16364 <value>0</value> 16365 </enumeratedValue> 16366 <enumeratedValue> 16367 <name>en</name> 16368 <description>Enable.</description> 16369 <value>1</value> 16370 </enumeratedValue> 16371 </enumeratedValues> 16372 </field> 16373 <field> 16374 <name>DFD_EN</name> 16375 <description>Digital Fault Dector Enable</description> 16376 <bitOffset>3</bitOffset> 16377 <bitWidth>1</bitWidth> 16378 </field> 16379 <field> 16380 <name>DFD_NMI</name> 16381 <description>Digital Fault NMI Enable</description> 16382 <bitOffset>4</bitOffset> 16383 <bitWidth>1</bitWidth> 16384 </field> 16385 <field> 16386 <name>DFD_STDBY</name> 16387 <description>Digital Fault Dector Stand by Enable</description> 16388 <bitOffset>8</bitOffset> 16389 <bitWidth>1</bitWidth> 16390 </field> 16391 <field> 16392 <name>LOTEMP_SEL</name> 16393 <description>Low Temperature Detection Select.</description> 16394 <bitOffset>16</bitOffset> 16395 <bitWidth>1</bitWidth> 16396 <enumeratedValues> 16397 <enumeratedValue> 16398 <name>neg50C</name> 16399 <description>-50 degrees C.</description> 16400 <value>0</value> 16401 </enumeratedValue> 16402 <enumeratedValue> 16403 <name>neg30C</name> 16404 <description>-30 degrees C.</description> 16405 <value>1</value> 16406 </enumeratedValue> 16407 </enumeratedValues> 16408 </field> 16409 <field> 16410 <name>VTM_LOTHSEL</name> 16411 <description>VTM Low Threshold Detection</description> 16412 <bitOffset>18</bitOffset> 16413 <bitWidth>2</bitWidth> 16414 <enumeratedValues> 16415 <enumeratedValue> 16416 <name>1_6V</name> 16417 <description>1.6V</description> 16418 <value>0</value> 16419 </enumeratedValue> 16420 <enumeratedValue> 16421 <name>2_2V</name> 16422 <description>2.2V</description> 16423 <value>1</value> 16424 </enumeratedValue> 16425 <enumeratedValue> 16426 <name>2_8V</name> 16427 <description>2.8V</description> 16428 <value>2</value> 16429 </enumeratedValue> 16430 </enumeratedValues> 16431 </field> 16432 <field> 16433 <name>LOCK</name> 16434 <description>Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 16435 <bitOffset>31</bitOffset> 16436 <bitWidth>1</bitWidth> 16437 <enumeratedValues> 16438 <enumeratedValue> 16439 <name>unlocked</name> 16440 <description>Unlocked.</description> 16441 <value>0</value> 16442 </enumeratedValue> 16443 <enumeratedValue> 16444 <name>locked</name> 16445 <description>Locked.</description> 16446 <value>1</value> 16447 </enumeratedValue> 16448 </enumeratedValues> 16449 </field> 16450 </fields> 16451 </register> 16452 <register> 16453 <name>SECALM</name> 16454 <description>Security Alarm Register.</description> 16455 <addressOffset>0x08</addressOffset> 16456 <resetValue>0x00000000</resetValue> 16457 <resetMask>0x00000000</resetMask> 16458 <fields> 16459 <field> 16460 <name>DRS</name> 16461 <description>Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.</description> 16462 <bitOffset>0</bitOffset> 16463 <bitWidth>1</bitWidth> 16464 <enumeratedValues> 16465 <enumeratedValue> 16466 <name>complete</name> 16467 <description>No operation/complete.</description> 16468 <value>0</value> 16469 </enumeratedValue> 16470 <enumeratedValue> 16471 <name>start</name> 16472 <description>Start operation.</description> 16473 <value>1</value> 16474 </enumeratedValue> 16475 </enumeratedValues> 16476 </field> 16477 <field> 16478 <name>KEYWIPE</name> 16479 <description>Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.</description> 16480 <bitOffset>1</bitOffset> 16481 <bitWidth>1</bitWidth> 16482 <enumeratedValues> 16483 <enumeratedValue> 16484 <name>complete</name> 16485 <description>No operation/complete.</description> 16486 <value>0</value> 16487 </enumeratedValue> 16488 <enumeratedValue> 16489 <name>start</name> 16490 <description>Start operation.</description> 16491 <value>1</value> 16492 </enumeratedValue> 16493 </enumeratedValues> 16494 </field> 16495 <field> 16496 <name>SHIELDF</name> 16497 <description>Die Shield Flag.</description> 16498 <bitOffset>2</bitOffset> 16499 <bitWidth>1</bitWidth> 16500 <enumeratedValues> 16501 <enumeratedValue> 16502 <name>noEvent</name> 16503 <description>The event has not occurred.</description> 16504 <value>0</value> 16505 </enumeratedValue> 16506 <enumeratedValue> 16507 <name>occurred</name> 16508 <description>The event has occurred.</description> 16509 <value>1</value> 16510 </enumeratedValue> 16511 </enumeratedValues> 16512 </field> 16513 <field> 16514 <name>LOTEMP</name> 16515 <description>Low Temperature Detect.</description> 16516 <bitOffset>3</bitOffset> 16517 <bitWidth>1</bitWidth> 16518 <enumeratedValues> 16519 <enumeratedValue> 16520 <name>noEvent</name> 16521 <description>The event has not occurred.</description> 16522 <value>0</value> 16523 </enumeratedValue> 16524 <enumeratedValue> 16525 <name>occurred</name> 16526 <description>The event has occurred.</description> 16527 <value>1</value> 16528 </enumeratedValue> 16529 </enumeratedValues> 16530 </field> 16531 <field> 16532 <name>HITEMP</name> 16533 <description>High Temperature Detect.</description> 16534 <bitOffset>4</bitOffset> 16535 <bitWidth>1</bitWidth> 16536 <enumeratedValues> 16537 <enumeratedValue> 16538 <name>noEvent</name> 16539 <description>The event has not occurred.</description> 16540 <value>0</value> 16541 </enumeratedValue> 16542 <enumeratedValue> 16543 <name>occurred</name> 16544 <description>The event has occurred.</description> 16545 <value>1</value> 16546 </enumeratedValue> 16547 </enumeratedValues> 16548 </field> 16549 <field> 16550 <name>BATLO</name> 16551 <description>Battery Undervoltage Detect.</description> 16552 <bitOffset>5</bitOffset> 16553 <bitWidth>1</bitWidth> 16554 <enumeratedValues> 16555 <enumeratedValue> 16556 <name>noEvent</name> 16557 <description>The event has not occurred.</description> 16558 <value>0</value> 16559 </enumeratedValue> 16560 <enumeratedValue> 16561 <name>occurred</name> 16562 <description>The event has occurred.</description> 16563 <value>1</value> 16564 </enumeratedValue> 16565 </enumeratedValues> 16566 </field> 16567 <field> 16568 <name>BATHI</name> 16569 <description>Battery Overvoltage Detect.</description> 16570 <bitOffset>6</bitOffset> 16571 <bitWidth>1</bitWidth> 16572 <enumeratedValues> 16573 <enumeratedValue> 16574 <name>noEvent</name> 16575 <description>The event has not occurred.</description> 16576 <value>0</value> 16577 </enumeratedValue> 16578 <enumeratedValue> 16579 <name>occurred</name> 16580 <description>The event has occurred.</description> 16581 <value>1</value> 16582 </enumeratedValue> 16583 </enumeratedValues> 16584 </field> 16585 <field> 16586 <name>EXTF</name> 16587 <description>External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 16588 <bitOffset>7</bitOffset> 16589 <bitWidth>1</bitWidth> 16590 <enumeratedValues> 16591 <enumeratedValue> 16592 <name>noEvent</name> 16593 <description>The event has not occurred.</description> 16594 <value>0</value> 16595 </enumeratedValue> 16596 <enumeratedValue> 16597 <name>occurred</name> 16598 <description>The event has occurred.</description> 16599 <value>1</value> 16600 </enumeratedValue> 16601 </enumeratedValues> 16602 </field> 16603 <field> 16604 <name>DFD</name> 16605 <description>Digital Fault Detector.</description> 16606 <bitOffset>8</bitOffset> 16607 <bitWidth>1</bitWidth> 16608 <enumeratedValues> 16609 <enumeratedValue> 16610 <name>noEvent</name> 16611 <description>The event has not occurred.</description> 16612 <value>0</value> 16613 </enumeratedValue> 16614 <enumeratedValue> 16615 <name>occurred</name> 16616 <description>The event has occurred.</description> 16617 <value>1</value> 16618 </enumeratedValue> 16619 </enumeratedValues> 16620 </field> 16621 <field> 16622 <name>VMAINPF</name> 16623 <description>VMAIN Power Fail Flag.</description> 16624 <bitOffset>9</bitOffset> 16625 <bitWidth>1</bitWidth> 16626 <enumeratedValues> 16627 <enumeratedValue> 16628 <name>noEvent</name> 16629 <description>The event has not occurred.</description> 16630 <value>0</value> 16631 </enumeratedValue> 16632 <enumeratedValue> 16633 <name>occurred</name> 16634 <description>The event has occurred.</description> 16635 <value>1</value> 16636 </enumeratedValue> 16637 </enumeratedValues> 16638 </field> 16639 <field> 16640 <name>EXTSTAT0</name> 16641 <description>External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 16642 <bitOffset>16</bitOffset> 16643 <bitWidth>1</bitWidth> 16644 <enumeratedValues> 16645 <enumeratedValue> 16646 <name>noEvent</name> 16647 <description>The event has not occurred.</description> 16648 <value>0</value> 16649 </enumeratedValue> 16650 <enumeratedValue> 16651 <name>occurred</name> 16652 <description>The event has occurred.</description> 16653 <value>1</value> 16654 </enumeratedValue> 16655 </enumeratedValues> 16656 </field> 16657 <field> 16658 <name>EXTSTAT1</name> 16659 <description>External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 16660 <bitOffset>17</bitOffset> 16661 <bitWidth>1</bitWidth> 16662 <enumeratedValues> 16663 <enumeratedValue> 16664 <name>noEvent</name> 16665 <description>The event has not occurred.</description> 16666 <value>0</value> 16667 </enumeratedValue> 16668 <enumeratedValue> 16669 <name>occurred</name> 16670 <description>The event has occurred.</description> 16671 <value>1</value> 16672 </enumeratedValue> 16673 </enumeratedValues> 16674 </field> 16675 <field> 16676 <name>EXTSTAT2</name> 16677 <description>External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 16678 <bitOffset>18</bitOffset> 16679 <bitWidth>1</bitWidth> 16680 <enumeratedValues> 16681 <enumeratedValue> 16682 <name>noEvent</name> 16683 <description>The event has not occurred.</description> 16684 <value>0</value> 16685 </enumeratedValue> 16686 <enumeratedValue> 16687 <name>occurred</name> 16688 <description>The event has occurred.</description> 16689 <value>1</value> 16690 </enumeratedValue> 16691 </enumeratedValues> 16692 </field> 16693 <field> 16694 <name>EXTSTAT3</name> 16695 <description>External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 16696 <bitOffset>19</bitOffset> 16697 <bitWidth>1</bitWidth> 16698 <enumeratedValues> 16699 <enumeratedValue> 16700 <name>noEvent</name> 16701 <description>The event has not occurred.</description> 16702 <value>0</value> 16703 </enumeratedValue> 16704 <enumeratedValue> 16705 <name>occurred</name> 16706 <description>The event has occurred.</description> 16707 <value>1</value> 16708 </enumeratedValue> 16709 </enumeratedValues> 16710 </field> 16711 <field> 16712 <name>EXTSTAT4</name> 16713 <description>External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 16714 <bitOffset>20</bitOffset> 16715 <bitWidth>1</bitWidth> 16716 <enumeratedValues> 16717 <enumeratedValue> 16718 <name>noEvent</name> 16719 <description>The event has not occurred.</description> 16720 <value>0</value> 16721 </enumeratedValue> 16722 <enumeratedValue> 16723 <name>occurred</name> 16724 <description>The event has occurred.</description> 16725 <value>1</value> 16726 </enumeratedValue> 16727 </enumeratedValues> 16728 </field> 16729 <field> 16730 <name>EXTSTAT5</name> 16731 <description>External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 16732 <bitOffset>21</bitOffset> 16733 <bitWidth>1</bitWidth> 16734 <enumeratedValues> 16735 <enumeratedValue> 16736 <name>noEvent</name> 16737 <description>The event has not occurred.</description> 16738 <value>0</value> 16739 </enumeratedValue> 16740 <enumeratedValue> 16741 <name>occurred</name> 16742 <description>The event has occurred.</description> 16743 <value>1</value> 16744 </enumeratedValue> 16745 </enumeratedValues> 16746 </field> 16747 <field> 16748 <name>EXTSWARN0</name> 16749 <description>External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 16750 <bitOffset>24</bitOffset> 16751 <bitWidth>1</bitWidth> 16752 <enumeratedValues> 16753 <enumeratedValue> 16754 <name>noEvent</name> 16755 <description>The event has not occurred.</description> 16756 <value>0</value> 16757 </enumeratedValue> 16758 <enumeratedValue> 16759 <name>occurred</name> 16760 <description>The event has occurred.</description> 16761 <value>1</value> 16762 </enumeratedValue> 16763 </enumeratedValues> 16764 </field> 16765 <field> 16766 <name>EXTSWARN1</name> 16767 <description>External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 16768 <bitOffset>25</bitOffset> 16769 <bitWidth>1</bitWidth> 16770 <enumeratedValues> 16771 <enumeratedValue> 16772 <name>noEvent</name> 16773 <description>The event has not occurred.</description> 16774 <value>0</value> 16775 </enumeratedValue> 16776 <enumeratedValue> 16777 <name>occurred</name> 16778 <description>The event has occurred.</description> 16779 <value>1</value> 16780 </enumeratedValue> 16781 </enumeratedValues> 16782 </field> 16783 <field> 16784 <name>EXTSWARN2</name> 16785 <description>External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 16786 <bitOffset>26</bitOffset> 16787 <bitWidth>1</bitWidth> 16788 <enumeratedValues> 16789 <enumeratedValue> 16790 <name>noEvent</name> 16791 <description>The event has not occurred.</description> 16792 <value>0</value> 16793 </enumeratedValue> 16794 <enumeratedValue> 16795 <name>occurred</name> 16796 <description>The event has occurred.</description> 16797 <value>1</value> 16798 </enumeratedValue> 16799 </enumeratedValues> 16800 </field> 16801 <field> 16802 <name>EXTSWARN3</name> 16803 <description>External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 16804 <bitOffset>27</bitOffset> 16805 <bitWidth>1</bitWidth> 16806 <enumeratedValues> 16807 <enumeratedValue> 16808 <name>noEvent</name> 16809 <description>The event has not occurred.</description> 16810 <value>0</value> 16811 </enumeratedValue> 16812 <enumeratedValue> 16813 <name>occurred</name> 16814 <description>The event has occurred.</description> 16815 <value>1</value> 16816 </enumeratedValue> 16817 </enumeratedValues> 16818 </field> 16819 <field> 16820 <name>EXTSWARN4</name> 16821 <description>External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 16822 <bitOffset>28</bitOffset> 16823 <bitWidth>1</bitWidth> 16824 <enumeratedValues> 16825 <enumeratedValue> 16826 <name>noEvent</name> 16827 <description>The event has not occurred.</description> 16828 <value>0</value> 16829 </enumeratedValue> 16830 <enumeratedValue> 16831 <name>occurred</name> 16832 <description>The event has occurred.</description> 16833 <value>1</value> 16834 </enumeratedValue> 16835 </enumeratedValues> 16836 </field> 16837 <field> 16838 <name>EXTSWARN5</name> 16839 <description>External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 16840 <bitOffset>29</bitOffset> 16841 <bitWidth>1</bitWidth> 16842 <enumeratedValues> 16843 <enumeratedValue> 16844 <name>noEvent</name> 16845 <description>The event has not occurred.</description> 16846 <value>0</value> 16847 </enumeratedValue> 16848 <enumeratedValue> 16849 <name>occurred</name> 16850 <description>The event has occurred.</description> 16851 <value>1</value> 16852 </enumeratedValue> 16853 </enumeratedValues> 16854 </field> 16855 </fields> 16856 </register> 16857 <register> 16858 <name>SECDIAG</name> 16859 <description>Security Diagnostic Register.</description> 16860 <addressOffset>0x0C</addressOffset> 16861 <access>read-write</access> 16862 <resetValue>0x00000001</resetValue> 16863 <resetMask>0xFFC0FE02</resetMask> 16864 <fields> 16865 <field> 16866 <name>PORF</name> 16867 <description>Power-On-Reset Flag. This bit is set once the power supply is conneted.</description> 16868 <bitOffset>0</bitOffset> 16869 <bitWidth>1</bitWidth> 16870 <enumeratedValues> 16871 <enumeratedValue> 16872 <name>noEvent</name> 16873 <description>The event has not occurred.</description> 16874 <value>0</value> 16875 </enumeratedValue> 16876 <enumeratedValue> 16877 <name>occurred</name> 16878 <description>The event has occurred.</description> 16879 <value>1</value> 16880 </enumeratedValue> 16881 </enumeratedValues> 16882 </field> 16883 <field> 16884 <name>SHIELDF</name> 16885 <description>Die Shield Flag.</description> 16886 <bitOffset>2</bitOffset> 16887 <bitWidth>1</bitWidth> 16888 <access>read-only</access> 16889 <enumeratedValues> 16890 <enumeratedValue> 16891 <name>noEvent</name> 16892 <description>The event has not occurred.</description> 16893 <value>0</value> 16894 </enumeratedValue> 16895 <enumeratedValue> 16896 <name>occurred</name> 16897 <description>The event has occurred.</description> 16898 <value>1</value> 16899 </enumeratedValue> 16900 </enumeratedValues> 16901 </field> 16902 <field> 16903 <name>LOTEMP</name> 16904 <description>Low Temperature Detect.</description> 16905 <bitOffset>3</bitOffset> 16906 <bitWidth>1</bitWidth> 16907 <access>read-only</access> 16908 <enumeratedValues> 16909 <enumeratedValue> 16910 <name>noEvent</name> 16911 <description>The event has not occurred.</description> 16912 <value>0</value> 16913 </enumeratedValue> 16914 <enumeratedValue> 16915 <name>occurred</name> 16916 <description>The event has occurred.</description> 16917 <value>1</value> 16918 </enumeratedValue> 16919 </enumeratedValues> 16920 </field> 16921 <field> 16922 <name>HITEMP</name> 16923 <description>High Temperature Detect.</description> 16924 <bitOffset>4</bitOffset> 16925 <bitWidth>1</bitWidth> 16926 <access>read-only</access> 16927 <enumeratedValues> 16928 <enumeratedValue> 16929 <name>noEvent</name> 16930 <description>The event has not occurred.</description> 16931 <value>0</value> 16932 </enumeratedValue> 16933 <enumeratedValue> 16934 <name>occurred</name> 16935 <description>The event has occurred.</description> 16936 <value>1</value> 16937 </enumeratedValue> 16938 </enumeratedValues> 16939 </field> 16940 <field> 16941 <name>BATLO</name> 16942 <description>Battery Undervoltage Detect.</description> 16943 <bitOffset>5</bitOffset> 16944 <bitWidth>1</bitWidth> 16945 <access>read-only</access> 16946 <enumeratedValues> 16947 <enumeratedValue> 16948 <name>noEvent</name> 16949 <description>The event has not occurred.</description> 16950 <value>0</value> 16951 </enumeratedValue> 16952 <enumeratedValue> 16953 <name>occurred</name> 16954 <description>The event has occurred.</description> 16955 <value>1</value> 16956 </enumeratedValue> 16957 </enumeratedValues> 16958 </field> 16959 <field> 16960 <name>BATHI</name> 16961 <description>Battery Overvoltage Detect.</description> 16962 <bitOffset>6</bitOffset> 16963 <bitWidth>1</bitWidth> 16964 <access>read-only</access> 16965 <enumeratedValues> 16966 <enumeratedValue> 16967 <name>noEvent</name> 16968 <description>The event has not occurred.</description> 16969 <value>0</value> 16970 </enumeratedValue> 16971 <enumeratedValue> 16972 <name>occurred</name> 16973 <description>The event has occurred.</description> 16974 <value>1</value> 16975 </enumeratedValue> 16976 </enumeratedValues> 16977 </field> 16978 <field> 16979 <name>DYNF</name> 16980 <description>Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 16981 <bitOffset>7</bitOffset> 16982 <bitWidth>1</bitWidth> 16983 <access>read-only</access> 16984 <enumeratedValues> 16985 <enumeratedValue> 16986 <name>noEvent</name> 16987 <description>The event has not occurred.</description> 16988 <value>0</value> 16989 </enumeratedValue> 16990 <enumeratedValue> 16991 <name>occurred</name> 16992 <description>The event has occurred.</description> 16993 <value>1</value> 16994 </enumeratedValue> 16995 </enumeratedValues> 16996 </field> 16997 <field> 16998 <name>AESK_MDU</name> 16999 <description>AES Key Transfer. This bit is set to 1 when AES MDU Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.</description> 17000 <bitOffset>9</bitOffset> 17001 <bitWidth>1</bitWidth> 17002 <access>read-only</access> 17003 <enumeratedValues> 17004 <enumeratedValue> 17005 <name>incomplete</name> 17006 <description>Key has not been transferred.</description> 17007 <value>0</value> 17008 </enumeratedValue> 17009 <enumeratedValue> 17010 <name>complete</name> 17011 <description>Key has been transferred.</description> 17012 <value>1</value> 17013 </enumeratedValue> 17014 </enumeratedValues> 17015 </field> 17016 <field> 17017 <name>AESK_NVSRAM</name> 17018 <description>NVSRAM 256-bit AES Key Cleared. This field is set to 1 by hardware if the NVSRAM AES key is zero. This field resets to 1 on a POR.</description> 17019 <bitOffset>10</bitOffset> 17020 <bitWidth>1</bitWidth> 17021 <access>read-only</access> 17022 <enumeratedValues> 17023 <enumeratedValue> 17024 <name>nonzero</name> 17025 <description>Key is non-zero.</description> 17026 <value>0</value> 17027 </enumeratedValue> 17028 <enumeratedValue> 17029 <name>zero</name> 17030 <description>Key is zero.</description> 17031 <value>1</value> 17032 </enumeratedValue> 17033 </enumeratedValues> 17034 </field> 17035 <field> 17036 <name>AESK_SPIXF</name> 17037 <description>SPIXF 128-Bit AES Key Cleared. This field is set to 1 by hardware if the SPIXR 128-bit AES key is zero. This field resets to 1 on a POR.</description> 17038 <bitOffset>11</bitOffset> 17039 <bitWidth>1</bitWidth> 17040 <access>read-only</access> 17041 <enumeratedValues> 17042 <enumeratedValue> 17043 <name>nonzero</name> 17044 <description>Key is non-zero.</description> 17045 <value>0</value> 17046 </enumeratedValue> 17047 <enumeratedValue> 17048 <name>zero</name> 17049 <description>Key is zero.</description> 17050 <value>1</value> 17051 </enumeratedValue> 17052 </enumeratedValues> 17053 </field> 17054 <field> 17055 <name>AESK_SPIXR</name> 17056 <description>SPIXR 128-Bit AES Key Cleared. This field is set to 1 by hardware if the SPIXR 128-bit AES key is zero. This field resets to 1 on a POR.</description> 17057 <bitOffset>12</bitOffset> 17058 <bitWidth>1</bitWidth> 17059 <access>read-only</access> 17060 <enumeratedValues> 17061 <enumeratedValue> 17062 <name>nonzero</name> 17063 <description>Key is non-zero.</description> 17064 <value>0</value> 17065 </enumeratedValue> 17066 <enumeratedValue> 17067 <name>zero</name> 17068 <description>Key is zero.</description> 17069 <value>1</value> 17070 </enumeratedValue> 17071 </enumeratedValues> 17072 </field> 17073 <field> 17074 <name>EXTSTAT0</name> 17075 <description>External Sensor 0 Detect.</description> 17076 <bitOffset>16</bitOffset> 17077 <bitWidth>1</bitWidth> 17078 <access>read-only</access> 17079 <enumeratedValues> 17080 <enumeratedValue> 17081 <name>noEvent</name> 17082 <description>The event has not occurred.</description> 17083 <value>0</value> 17084 </enumeratedValue> 17085 <enumeratedValue> 17086 <name>occurred</name> 17087 <description>The event has occurred.</description> 17088 <value>1</value> 17089 </enumeratedValue> 17090 </enumeratedValues> 17091 </field> 17092 <field> 17093 <name>EXTSTAT1</name> 17094 <description>External Sensor 1 Detect.</description> 17095 <bitOffset>17</bitOffset> 17096 <bitWidth>1</bitWidth> 17097 <access>read-only</access> 17098 <enumeratedValues> 17099 <enumeratedValue> 17100 <name>noEvent</name> 17101 <description>The event has not occurred.</description> 17102 <value>0</value> 17103 </enumeratedValue> 17104 <enumeratedValue> 17105 <name>occurred</name> 17106 <description>The event has occurred.</description> 17107 <value>1</value> 17108 </enumeratedValue> 17109 </enumeratedValues> 17110 </field> 17111 <field> 17112 <name>EXTSTAT2</name> 17113 <description>External Sensor 2 Detect.</description> 17114 <bitOffset>18</bitOffset> 17115 <bitWidth>1</bitWidth> 17116 <access>read-only</access> 17117 <enumeratedValues> 17118 <enumeratedValue> 17119 <name>noEvent</name> 17120 <description>The event has not occurred.</description> 17121 <value>0</value> 17122 </enumeratedValue> 17123 <enumeratedValue> 17124 <name>occurred</name> 17125 <description>The event has occurred.</description> 17126 <value>1</value> 17127 </enumeratedValue> 17128 </enumeratedValues> 17129 </field> 17130 <field> 17131 <name>EXTSTAT3</name> 17132 <description>External Sensor 3 Detect.</description> 17133 <bitOffset>19</bitOffset> 17134 <bitWidth>1</bitWidth> 17135 <access>read-only</access> 17136 <enumeratedValues> 17137 <enumeratedValue> 17138 <name>noEvent</name> 17139 <description>The event has not occurred.</description> 17140 <value>0</value> 17141 </enumeratedValue> 17142 <enumeratedValue> 17143 <name>occurred</name> 17144 <description>The event has occurred.</description> 17145 <value>1</value> 17146 </enumeratedValue> 17147 </enumeratedValues> 17148 </field> 17149 <field> 17150 <name>EXTSTAT4</name> 17151 <description>External Sensor 4 Detect.</description> 17152 <bitOffset>20</bitOffset> 17153 <bitWidth>1</bitWidth> 17154 <access>read-only</access> 17155 <enumeratedValues> 17156 <enumeratedValue> 17157 <name>noEvent</name> 17158 <description>The event has not occurred.</description> 17159 <value>0</value> 17160 </enumeratedValue> 17161 <enumeratedValue> 17162 <name>occurred</name> 17163 <description>The event has occurred.</description> 17164 <value>1</value> 17165 </enumeratedValue> 17166 </enumeratedValues> 17167 </field> 17168 <field> 17169 <name>EXTSTAT5</name> 17170 <description>External Sensor 5 Detect.</description> 17171 <bitOffset>21</bitOffset> 17172 <bitWidth>1</bitWidth> 17173 <access>read-only</access> 17174 <enumeratedValues> 17175 <enumeratedValue> 17176 <name>noEvent</name> 17177 <description>The event has not occurred.</description> 17178 <value>0</value> 17179 </enumeratedValue> 17180 <enumeratedValue> 17181 <name>occurred</name> 17182 <description>The event has occurred.</description> 17183 <value>1</value> 17184 </enumeratedValue> 17185 </enumeratedValues> 17186 </field> 17187 </fields> 17188 </register> 17189 <register> 17190 <name>DLRTC</name> 17191 <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred.</description> 17192 <addressOffset>0x10</addressOffset> 17193 <access>read-only</access> 17194 <resetMask>0x00000000</resetMask> 17195 <fields> 17196 <field> 17197 <name>DLRTC</name> 17198 <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured.</description> 17199 <bitOffset>0</bitOffset> 17200 <bitWidth>32</bitWidth> 17201 </field> 17202 </fields> 17203 </register> 17204 <register> 17205 <name>MEUCFG</name> 17206 <description>MEU Configuration</description> 17207 <addressOffset>0x24</addressOffset> 17208 <resetMask>0x00000000</resetMask> 17209 <fields> 17210 <field> 17211 <name>ENC_REG0</name> 17212 <description> NVSRAM Encryption Enable Region 0. Setting this field to 1 enables encryption using the MEU of region 0 of the NVSRAM.</description> 17213 <bitOffset>0</bitOffset> 17214 <bitWidth>1</bitWidth> 17215 <enumeratedValues> 17216 <enumeratedValue> 17217 <name>plaintext</name> 17218 <description>Plain text.</description> 17219 <value>0</value> 17220 </enumeratedValue> 17221 <enumeratedValue> 17222 <name>encrypted</name> 17223 <description>Encrypted.</description> 17224 <value>1</value> 17225 </enumeratedValue> 17226 </enumeratedValues> 17227 </field> 17228 <field> 17229 <name>ENC_REG1</name> 17230 <description> NVSRAM Encryption Enable Region 1. Setting this field to 1 enables encryption using the MEU of region 1 of the NVSRAM.</description> 17231 <bitOffset>1</bitOffset> 17232 <bitWidth>1</bitWidth> 17233 <enumeratedValues> 17234 <enumeratedValue> 17235 <name>plaintext</name> 17236 <description>Plain text.</description> 17237 <value>0</value> 17238 </enumeratedValue> 17239 <enumeratedValue> 17240 <name>encrypted</name> 17241 <description>Encrypted.</description> 17242 <value>1</value> 17243 </enumeratedValue> 17244 </enumeratedValues> 17245 </field> 17246 <field> 17247 <name>ENC_REG2</name> 17248 <description> NVSRAM Encryption Enable Region 2. Setting this field to 1 enables encryption using the MEU of region 2 of the NVSRAM.</description> 17249 <bitOffset>2</bitOffset> 17250 <bitWidth>1</bitWidth> 17251 <enumeratedValues> 17252 <enumeratedValue> 17253 <name>plaintext</name> 17254 <description>Plain text.</description> 17255 <value>0</value> 17256 </enumeratedValue> 17257 <enumeratedValue> 17258 <name>encrypted</name> 17259 <description>Encrypted.</description> 17260 <value>1</value> 17261 </enumeratedValue> 17262 </enumeratedValues> 17263 </field> 17264 <field> 17265 <name>ENC_REG3</name> 17266 <description> NVSRAM Encryption Enable Region 3. Setting this field to 1 enables encryption using the MEU of region 3 of the NVSRAM.</description> 17267 <bitOffset>3</bitOffset> 17268 <bitWidth>1</bitWidth> 17269 <enumeratedValues> 17270 <enumeratedValue> 17271 <name>plaintext</name> 17272 <description>Plain text.</description> 17273 <value>0</value> 17274 </enumeratedValue> 17275 <enumeratedValue> 17276 <name>encrypted</name> 17277 <description>Encrypted.</description> 17278 <value>1</value> 17279 </enumeratedValue> 17280 </enumeratedValues> 17281 </field> 17282 <field> 17283 <name>ENC_REG4</name> 17284 <description> NVSRAM Encryption Enable Region 4. Setting this field to 1 enables encryption using the MEU of region 4 of the NVSRAM.</description> 17285 <bitOffset>4</bitOffset> 17286 <bitWidth>1</bitWidth> 17287 <enumeratedValues> 17288 <enumeratedValue> 17289 <name>plaintext</name> 17290 <description>Plain text.</description> 17291 <value>0</value> 17292 </enumeratedValue> 17293 <enumeratedValue> 17294 <name>encrypted</name> 17295 <description>Encrypted.</description> 17296 <value>1</value> 17297 </enumeratedValue> 17298 </enumeratedValues> 17299 </field> 17300 <field> 17301 <name>ENC_REG5</name> 17302 <description> NVSRAM Encryption Enable Region 5. Setting this field to 1 enables encryption using the MEU of region 5 of the NVSRAM.</description> 17303 <bitOffset>5</bitOffset> 17304 <bitWidth>1</bitWidth> 17305 <enumeratedValues> 17306 <enumeratedValue> 17307 <name>plaintext</name> 17308 <description>Plain text.</description> 17309 <value>0</value> 17310 </enumeratedValue> 17311 <enumeratedValue> 17312 <name>encrypted</name> 17313 <description>Encrypted.</description> 17314 <value>1</value> 17315 </enumeratedValue> 17316 </enumeratedValues> 17317 </field> 17318 <field> 17319 <name>ENC_REG6</name> 17320 <description> NVSRAM Encryption Enable Region 6. Setting this field to 1 enables encryption using the MEU of region 6 of the NVSRAM.</description> 17321 <bitOffset>6</bitOffset> 17322 <bitWidth>1</bitWidth> 17323 <enumeratedValues> 17324 <enumeratedValue> 17325 <name>plaintext</name> 17326 <description>Plain text.</description> 17327 <value>0</value> 17328 </enumeratedValue> 17329 <enumeratedValue> 17330 <name>encrypted</name> 17331 <description>Encrypted.</description> 17332 <value>1</value> 17333 </enumeratedValue> 17334 </enumeratedValues> 17335 </field> 17336 <field> 17337 <name>ENC_REG7</name> 17338 <description> NVSRAM Encryption Enable Region 7. Setting this field to 1 enables encryption using the MEU of region 7 of the NVSRAM.</description> 17339 <bitOffset>7</bitOffset> 17340 <bitWidth>1</bitWidth> 17341 <enumeratedValues> 17342 <enumeratedValue> 17343 <name>plaintext</name> 17344 <description>Plain text.</description> 17345 <value>0</value> 17346 </enumeratedValue> 17347 <enumeratedValue> 17348 <name>encrypted</name> 17349 <description>Encrypted.</description> 17350 <value>1</value> 17351 </enumeratedValue> 17352 </enumeratedValues> 17353 </field> 17354 <field> 17355 <name>LOCK</name> 17356 <description>Lock.</description> 17357 <bitOffset>31</bitOffset> 17358 <bitWidth>1</bitWidth> 17359 </field> 17360 </fields> 17361 </register> 17362 <register> 17363 <name>SECST</name> 17364 <description>Security Monitor Status Register.</description> 17365 <addressOffset>0x34</addressOffset> 17366 <access>read-only</access> 17367 <fields> 17368 <field> 17369 <name>EXTSRS</name> 17370 <description>External Sensor Control Register Status.</description> 17371 <bitOffset>0</bitOffset> 17372 <bitWidth>1</bitWidth> 17373 <enumeratedValues> 17374 <enumeratedValue> 17375 <name>allowed</name> 17376 <description>Access authorized.</description> 17377 <value>0</value> 17378 </enumeratedValue> 17379 <enumeratedValue> 17380 <name>notAllowed</name> 17381 <description>Access not authorized.</description> 17382 <value>1</value> 17383 </enumeratedValue> 17384 </enumeratedValues> 17385 </field> 17386 <field> 17387 <name>INTSRS</name> 17388 <description>Internal Sensor Control Register Status.</description> 17389 <bitOffset>1</bitOffset> 17390 <bitWidth>1</bitWidth> 17391 <enumeratedValues> 17392 <enumeratedValue> 17393 <name>allowed</name> 17394 <description>Access authorized.</description> 17395 <value>0</value> 17396 </enumeratedValue> 17397 <enumeratedValue> 17398 <name>notAllowed</name> 17399 <description>Access not authorized.</description> 17400 <value>1</value> 17401 </enumeratedValue> 17402 </enumeratedValues> 17403 </field> 17404 <field> 17405 <name>SECALRS</name> 17406 <description>Security Alarm Register Status.</description> 17407 <bitOffset>2</bitOffset> 17408 <bitWidth>1</bitWidth> 17409 <enumeratedValues> 17410 <enumeratedValue> 17411 <name>allowed</name> 17412 <description>Access authorized.</description> 17413 <value>0</value> 17414 </enumeratedValue> 17415 <enumeratedValue> 17416 <name>notAllowed</name> 17417 <description>Access not authorized.</description> 17418 <value>1</value> 17419 </enumeratedValue> 17420 </enumeratedValues> 17421 </field> 17422 <field> 17423 <name>MEUCFG</name> 17424 <description>MEU Configuration Register Status.</description> 17425 <bitOffset>4</bitOffset> 17426 <bitWidth>1</bitWidth> 17427 <enumeratedValues> 17428 <enumeratedValue> 17429 <name>normal</name> 17430 <description>Normal Operation.</description> 17431 <value>0</value> 17432 </enumeratedValue> 17433 <enumeratedValue> 17434 <name>busy</name> 17435 <description>Busy.</description> 17436 <value>1</value> 17437 </enumeratedValue> 17438 </enumeratedValues> 17439 </field> 17440 </fields> 17441 </register> 17442 <register> 17443 <name>SDBE</name> 17444 <description>Security Monitor Self Destruct Byte.</description> 17445 <addressOffset>0x38</addressOffset> 17446 <fields> 17447 <field> 17448 <name>DBYTE</name> 17449 <description>Self Destruct Byte</description> 17450 <bitOffset>0</bitOffset> 17451 <bitWidth>8</bitWidth> 17452 <access>read-only</access> 17453 </field> 17454 <field> 17455 <name>SBDEN</name> 17456 <description>Self-Destruct Byte Enable.</description> 17457 <bitOffset>31</bitOffset> 17458 <bitWidth>1</bitWidth> 17459 </field> 17460 </fields> 17461 </register> 17462 </registers> 17463 </peripheral> 17464<!--SMON The Security Monitor block used to monitor system threat conditions.--> 17465 <peripheral> 17466 <name>SPI</name> 17467 <description>SPI peripheral.</description> 17468 <baseAddress>0x40046000</baseAddress> 17469 <addressBlock> 17470 <offset>0x00</offset> 17471 <size>0x1000</size> 17472 <usage>registers</usage> 17473 </addressBlock> 17474 <interrupt> 17475 <name>SPI0</name> 17476 <value>16</value> 17477 </interrupt> 17478 <registers> 17479 <register> 17480 <name>DATA32</name> 17481 <description>Register for reading and writing the FIFO.</description> 17482 <addressOffset>0x00</addressOffset> 17483 <size>32</size> 17484 <access>read-write</access> 17485 <fields> 17486 <field> 17487 <name>QSPIFIFO</name> 17488 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 17489 <bitOffset>0</bitOffset> 17490 <bitWidth>32</bitWidth> 17491 </field> 17492 </fields> 17493 </register> 17494 <register> 17495 <dim>2</dim> 17496 <dimIncrement>2</dimIncrement> 17497 <name>DATA16[%s]</name> 17498 <description>Register for reading and writing the FIFO.</description> 17499 <alternateRegister>DATA32</alternateRegister> 17500 <addressOffset>0x00</addressOffset> 17501 <size>16</size> 17502 <access>read-write</access> 17503 <fields> 17504 <field> 17505 <name>QSPIFIFO</name> 17506 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 17507 <bitOffset>0</bitOffset> 17508 <bitWidth>16</bitWidth> 17509 </field> 17510 </fields> 17511 </register> 17512 <register> 17513 <dim>4</dim> 17514 <dimIncrement>1</dimIncrement> 17515 <name>DATA8[%s]</name> 17516 <description>Register for reading and writing the FIFO.</description> 17517 <alternateRegister>DATA32</alternateRegister> 17518 <addressOffset>0x00</addressOffset> 17519 <size>8</size> 17520 <access>read-write</access> 17521 <fields> 17522 <field> 17523 <name>QSPIFIFO</name> 17524 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 17525 <bitOffset>0</bitOffset> 17526 <bitWidth>8</bitWidth> 17527 </field> 17528 </fields> 17529 </register> 17530 <register> 17531 <name>CTRL0</name> 17532 <description>Register for controlling SPI peripheral.</description> 17533 <addressOffset>0x04</addressOffset> 17534 <access>read-write</access> 17535 <fields> 17536 <field> 17537 <name>EN</name> 17538 <description>SPI Enable.</description> 17539 <bitOffset>0</bitOffset> 17540 <bitWidth>1</bitWidth> 17541 <enumeratedValues> 17542 <enumeratedValue> 17543 <name>dis</name> 17544 <description>SPI is disabled.</description> 17545 <value>0</value> 17546 </enumeratedValue> 17547 <enumeratedValue> 17548 <name>en</name> 17549 <description>SPI is enabled.</description> 17550 <value>1</value> 17551 </enumeratedValue> 17552 </enumeratedValues> 17553 </field> 17554 <field> 17555 <name>MASTER</name> 17556 <description>Master Mode Enable.</description> 17557 <bitOffset>1</bitOffset> 17558 <bitWidth>1</bitWidth> 17559 <enumeratedValues> 17560 <enumeratedValue> 17561 <name>dis</name> 17562 <description>SPI is Slave mode.</description> 17563 <value>0</value> 17564 </enumeratedValue> 17565 <enumeratedValue> 17566 <name>en</name> 17567 <description>SPI is Master mode.</description> 17568 <value>1</value> 17569 </enumeratedValue> 17570 </enumeratedValues> 17571 </field> 17572 <field> 17573 <name>SS_IO</name> 17574 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 17575 <bitOffset>4</bitOffset> 17576 <bitWidth>1</bitWidth> 17577 <enumeratedValues> 17578 <enumeratedValue> 17579 <name>output</name> 17580 <description>Slave select 0 is output.</description> 17581 <value>0</value> 17582 </enumeratedValue> 17583 <enumeratedValue> 17584 <name>input</name> 17585 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 17586 <value>1</value> 17587 </enumeratedValue> 17588 </enumeratedValues> 17589 </field> 17590 <field> 17591 <name>START</name> 17592 <description>Start Transmit.</description> 17593 <bitOffset>5</bitOffset> 17594 <bitWidth>1</bitWidth> 17595 <enumeratedValues> 17596 <enumeratedValue> 17597 <name>start</name> 17598 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 17599 <value>1</value> 17600 </enumeratedValue> 17601 </enumeratedValues> 17602 </field> 17603 <field> 17604 <name>SS_CTRL</name> 17605 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 17606 <bitOffset>8</bitOffset> 17607 <bitWidth>1</bitWidth> 17608 <enumeratedValues> 17609 <enumeratedValue> 17610 <name>DEASSERT</name> 17611 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 17612 <value>0</value> 17613 </enumeratedValue> 17614 <enumeratedValue> 17615 <name>ASSERT</name> 17616 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 17617 <value>1</value> 17618 </enumeratedValue> 17619 </enumeratedValues> 17620 </field> 17621 <field> 17622 <name>SS</name> 17623 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 17624 <bitOffset>16</bitOffset> 17625 <bitWidth>4</bitWidth> 17626 <enumeratedValues> 17627 <enumeratedValue> 17628 <name>SS0</name> 17629 <description>SS0 is selected.</description> 17630 <value>0x1</value> 17631 </enumeratedValue> 17632 <enumeratedValue> 17633 <name>SS1</name> 17634 <description>SS1 is selected.</description> 17635 <value>0x2</value> 17636 </enumeratedValue> 17637 <enumeratedValue> 17638 <name>SS2</name> 17639 <description>SS2 is selected.</description> 17640 <value>0x4</value> 17641 </enumeratedValue> 17642 <enumeratedValue> 17643 <name>SS3</name> 17644 <description>SS3 is selected.</description> 17645 <value>0x8</value> 17646 </enumeratedValue> 17647 </enumeratedValues> 17648 </field> 17649 </fields> 17650 </register> 17651 <register> 17652 <name>CTRL1</name> 17653 <description>Register for controlling SPI peripheral.</description> 17654 <addressOffset>0x08</addressOffset> 17655 <access>read-write</access> 17656 <fields> 17657 <field> 17658 <name>TX_NUM_CHAR</name> 17659 <description>Nubmer of Characters to transmit.</description> 17660 <bitOffset>0</bitOffset> 17661 <bitWidth>16</bitWidth> 17662 </field> 17663 <field> 17664 <name>RX_NUM_CHAR</name> 17665 <description>Nubmer of Characters to receive.</description> 17666 <bitOffset>16</bitOffset> 17667 <bitWidth>16</bitWidth> 17668 </field> 17669 </fields> 17670 </register> 17671 <register> 17672 <name>CTRL2</name> 17673 <description>Register for controlling SPI peripheral.</description> 17674 <addressOffset>0x0C</addressOffset> 17675 <access>read-write</access> 17676 <fields> 17677 <field> 17678 <name>CPHA</name> 17679 <description>Clock Phase.</description> 17680 <bitOffset>0</bitOffset> 17681 <bitWidth>1</bitWidth> 17682 <enumeratedValues> 17683 <enumeratedValue> 17684 <name>Rising_Edge</name> 17685 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 17686 <value>0</value> 17687 </enumeratedValue> 17688 <enumeratedValue> 17689 <name>Falling_Edge</name> 17690 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 17691 <value>1</value> 17692 </enumeratedValue> 17693 </enumeratedValues> 17694 </field> 17695 <field> 17696 <name>CPOL</name> 17697 <description>Clock Polarity.</description> 17698 <bitOffset>1</bitOffset> 17699 <bitWidth>1</bitWidth> 17700 <enumeratedValues> 17701 <enumeratedValue> 17702 <name>Normal</name> 17703 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 17704 <value>0</value> 17705 </enumeratedValue> 17706 <enumeratedValue> 17707 <name>Inverted</name> 17708 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 17709 <value>1</value> 17710 </enumeratedValue> 17711 </enumeratedValues> 17712 </field> 17713 <field> 17714 <name>NUMBITS</name> 17715 <description>Number of Bits per character.</description> 17716 <bitOffset>8</bitOffset> 17717 <bitWidth>4</bitWidth> 17718 <enumeratedValues> 17719 <enumeratedValue> 17720 <name>0</name> 17721 <description>16 bits per character.</description> 17722 <value>0</value> 17723 </enumeratedValue> 17724 </enumeratedValues> 17725 </field> 17726 <field> 17727 <name>DATA_WIDTH</name> 17728 <description>SPI Data width.</description> 17729 <bitOffset>12</bitOffset> 17730 <bitWidth>2</bitWidth> 17731 <enumeratedValues> 17732 <enumeratedValue> 17733 <name>Mono</name> 17734 <description>1 data pin.</description> 17735 <value>0</value> 17736 </enumeratedValue> 17737 <enumeratedValue> 17738 <name>Dual</name> 17739 <description>2 data pins.</description> 17740 <value>1</value> 17741 </enumeratedValue> 17742 <enumeratedValue> 17743 <name>Quad</name> 17744 <description>4 data pins.</description> 17745 <value>2</value> 17746 </enumeratedValue> 17747 </enumeratedValues> 17748 </field> 17749 <field> 17750 <name>THREE_WIRE</name> 17751 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 17752 <bitOffset>15</bitOffset> 17753 <bitWidth>1</bitWidth> 17754 <enumeratedValues> 17755 <enumeratedValue> 17756 <name>dis</name> 17757 <description>Use four wire mode (Mono only).</description> 17758 <value>0</value> 17759 </enumeratedValue> 17760 <enumeratedValue> 17761 <name>en</name> 17762 <description>Use three wire mode.</description> 17763 <value>1</value> 17764 </enumeratedValue> 17765 </enumeratedValues> 17766 </field> 17767 <field> 17768 <name>SS_POL</name> 17769 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 17770 <bitOffset>16</bitOffset> 17771 <bitWidth>4</bitWidth> 17772 <enumeratedValues> 17773 <enumeratedValue> 17774 <name>SS0_high</name> 17775 <description>SS0 active high.</description> 17776 <value>0x1</value> 17777 </enumeratedValue> 17778 <enumeratedValue> 17779 <name>SS1_high</name> 17780 <description>SS1 active high.</description> 17781 <value>0x2</value> 17782 </enumeratedValue> 17783 <enumeratedValue> 17784 <name>SS2_high</name> 17785 <description>SS2 active high.</description> 17786 <value>0x4</value> 17787 </enumeratedValue> 17788 <enumeratedValue> 17789 <name>SS3_high</name> 17790 <description>SS3 active high.</description> 17791 <value>0x8</value> 17792 </enumeratedValue> 17793 </enumeratedValues> 17794 </field> 17795 </fields> 17796 </register> 17797 <register> 17798 <name>SS_TIME</name> 17799 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 17800 <addressOffset>0x10</addressOffset> 17801 <access>read-write</access> 17802 <fields> 17803 <field> 17804 <name>PRE</name> 17805 <description>Slave Select Pre delay 1.</description> 17806 <bitOffset>0</bitOffset> 17807 <bitWidth>8</bitWidth> 17808 <enumeratedValues> 17809 <enumeratedValue> 17810 <name>256</name> 17811 <description>256 system clocks between SS active and first serial clock edge.</description> 17812 <value>0</value> 17813 </enumeratedValue> 17814 </enumeratedValues> 17815 </field> 17816 <field> 17817 <name>POST</name> 17818 <description>Slave Select Post delay 2.</description> 17819 <bitOffset>8</bitOffset> 17820 <bitWidth>8</bitWidth> 17821 <enumeratedValues> 17822 <enumeratedValue> 17823 <name>256</name> 17824 <description>256 system clocks between last serial clock edge and SS inactive.</description> 17825 <value>0</value> 17826 </enumeratedValue> 17827 </enumeratedValues> 17828 </field> 17829 <field> 17830 <name>INACT</name> 17831 <description>Slave Select Inactive delay.</description> 17832 <bitOffset>16</bitOffset> 17833 <bitWidth>8</bitWidth> 17834 <enumeratedValues> 17835 <enumeratedValue> 17836 <name>256</name> 17837 <description>256 system clocks between transactions.</description> 17838 <value>0</value> 17839 </enumeratedValue> 17840 </enumeratedValues> 17841 </field> 17842 </fields> 17843 </register> 17844 <register> 17845 <name>CLK_CFG</name> 17846 <description>Register for controlling SPI clock rate.</description> 17847 <addressOffset>0x14</addressOffset> 17848 <access>read-write</access> 17849 <fields> 17850 <field> 17851 <name>LO</name> 17852 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 17853 <bitOffset>0</bitOffset> 17854 <bitWidth>8</bitWidth> 17855 <enumeratedValues> 17856 <enumeratedValue> 17857 <name>Dis</name> 17858 <description>Duty cycle control of serial clock generation is disabled.</description> 17859 <value>0</value> 17860 </enumeratedValue> 17861 </enumeratedValues> 17862 </field> 17863 <field> 17864 <name>HI</name> 17865 <description>High duty cycle control. In timer mode, reload[15:8].</description> 17866 <bitOffset>8</bitOffset> 17867 <bitWidth>8</bitWidth> 17868 <enumeratedValues> 17869 <enumeratedValue> 17870 <name>Dis</name> 17871 <description>Duty cycle control of serial clock generation is disabled.</description> 17872 <value>0</value> 17873 </enumeratedValue> 17874 </enumeratedValues> 17875 </field> 17876 <field> 17877 <name>SCALE</name> 17878 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 17879 <bitOffset>16</bitOffset> 17880 <bitWidth>4</bitWidth> 17881 </field> 17882 </fields> 17883 </register> 17884 <register> 17885 <name>DMA</name> 17886 <description>Register for controlling DMA.</description> 17887 <addressOffset>0x1C</addressOffset> 17888 <access>read-write</access> 17889 <fields> 17890 <field> 17891 <name>TX_FIFO_LEVEL</name> 17892 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 17893 <bitOffset>0</bitOffset> 17894 <bitWidth>5</bitWidth> 17895 </field> 17896 <field> 17897 <name>TX_FIFO_EN</name> 17898 <description>Transmit FIFO enabled for SPI transactions.</description> 17899 <bitOffset>6</bitOffset> 17900 <bitWidth>1</bitWidth> 17901 <enumeratedValues> 17902 <enumeratedValue> 17903 <name>dis</name> 17904 <description>Transmit FIFO is not enabled.</description> 17905 <value>0</value> 17906 </enumeratedValue> 17907 <enumeratedValue> 17908 <name>en</name> 17909 <description>Transmit FIFO is enabled.</description> 17910 <value>1</value> 17911 </enumeratedValue> 17912 </enumeratedValues> 17913 </field> 17914 <field> 17915 <name>TX_FIFO_CLEAR</name> 17916 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 17917 pointers. This should be done when FIFO is not being accessed on the SPI side. 17918 .</description> 17919 <bitOffset>7</bitOffset> 17920 <bitWidth>1</bitWidth> 17921 <enumeratedValues> 17922 <enumeratedValue> 17923 <name>CLEAR</name> 17924 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 17925 <value>1</value> 17926 </enumeratedValue> 17927 </enumeratedValues> 17928 </field> 17929 <field> 17930 <name>TX_FIFO_CNT</name> 17931 <description>Count of entries in TX FIFO.</description> 17932 <bitOffset>8</bitOffset> 17933 <bitWidth>6</bitWidth> 17934 <access>read-only</access> 17935 </field> 17936 <field> 17937 <name>TX_DMA_EN</name> 17938 <description>TX DMA Enable.</description> 17939 <bitOffset>15</bitOffset> 17940 <bitWidth>1</bitWidth> 17941 <enumeratedValues> 17942 <enumeratedValue> 17943 <name>DIS</name> 17944 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 17945 <value>0</value> 17946 </enumeratedValue> 17947 <enumeratedValue> 17948 <name>en</name> 17949 <description>TX DMA requests are enabled.</description> 17950 <value>1</value> 17951 </enumeratedValue> 17952 </enumeratedValues> 17953 </field> 17954 <field> 17955 <name>RX_FIFO_LEVEL</name> 17956 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 17957 <bitOffset>16</bitOffset> 17958 <bitWidth>5</bitWidth> 17959 </field> 17960 <field> 17961 <name>RX_FIFO_EN</name> 17962 <description>Receive FIFO enabled for SPI transactions.</description> 17963 <bitOffset>22</bitOffset> 17964 <bitWidth>1</bitWidth> 17965 <enumeratedValues> 17966 <enumeratedValue> 17967 <name>DIS</name> 17968 <description>Receive FIFO is not enabled.</description> 17969 <value>0</value> 17970 </enumeratedValue> 17971 <enumeratedValue> 17972 <name>en</name> 17973 <description>Receive FIFO is enabled.</description> 17974 <value>1</value> 17975 </enumeratedValue> 17976 </enumeratedValues> 17977 </field> 17978 <field> 17979 <name>RX_FIFO_CLEAR</name> 17980 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 17981 <bitOffset>23</bitOffset> 17982 <bitWidth>1</bitWidth> 17983 <enumeratedValues> 17984 <enumeratedValue> 17985 <name>CLEAR</name> 17986 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 17987 <value>1</value> 17988 </enumeratedValue> 17989 </enumeratedValues> 17990 </field> 17991 <field> 17992 <name>RX_FIFO_CNT</name> 17993 <description>Count of entries in RX FIFO.</description> 17994 <bitOffset>24</bitOffset> 17995 <bitWidth>6</bitWidth> 17996 <access>read-only</access> 17997 </field> 17998 <field> 17999 <name>RX_DMA_EN</name> 18000 <description>RX DMA Enable.</description> 18001 <bitOffset>31</bitOffset> 18002 <bitWidth>1</bitWidth> 18003 <enumeratedValues> 18004 <enumeratedValue> 18005 <name>dis</name> 18006 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 18007 <value>0</value> 18008 </enumeratedValue> 18009 <enumeratedValue> 18010 <name>en</name> 18011 <description>RX DMA requests are enabled.</description> 18012 <value>1</value> 18013 </enumeratedValue> 18014 </enumeratedValues> 18015 </field> 18016 </fields> 18017 </register> 18018 <register> 18019 <name>INT_FL</name> 18020 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 18021 <addressOffset>0x20</addressOffset> 18022 <access>read-write</access> 18023 <fields> 18024 <field> 18025 <name>TX_THRESH</name> 18026 <description>TX FIFO Threshold Crossed.</description> 18027 <bitOffset>0</bitOffset> 18028 <bitWidth>1</bitWidth> 18029 <enumeratedValues> 18030 <enumeratedValue> 18031 <name>clear</name> 18032 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18033 <value>1</value> 18034 </enumeratedValue> 18035 </enumeratedValues> 18036 </field> 18037 <field> 18038 <name>TX_EMPTY</name> 18039 <description>TX FIFO Empty.</description> 18040 <bitOffset>1</bitOffset> 18041 <bitWidth>1</bitWidth> 18042 <enumeratedValues> 18043 <enumeratedValue> 18044 <name>clear</name> 18045 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18046 <value>1</value> 18047 </enumeratedValue> 18048 </enumeratedValues> 18049 </field> 18050 <field> 18051 <name>RX_THRESH</name> 18052 <description>RX FIFO Threshold Crossed.</description> 18053 <bitOffset>2</bitOffset> 18054 <bitWidth>1</bitWidth> 18055 <enumeratedValues> 18056 <enumeratedValue> 18057 <name>clear</name> 18058 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18059 <value>1</value> 18060 </enumeratedValue> 18061 </enumeratedValues> 18062 </field> 18063 <field> 18064 <name>RX_FULL</name> 18065 <description>RX FIFO FULL.</description> 18066 <bitOffset>3</bitOffset> 18067 <bitWidth>1</bitWidth> 18068 <enumeratedValues> 18069 <enumeratedValue> 18070 <name>clear</name> 18071 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18072 <value>1</value> 18073 </enumeratedValue> 18074 </enumeratedValues> 18075 </field> 18076 <field> 18077 <name>SSA</name> 18078 <description>Slave Select Asserted.</description> 18079 <bitOffset>4</bitOffset> 18080 <bitWidth>1</bitWidth> 18081 <enumeratedValues> 18082 <enumeratedValue> 18083 <name>clear</name> 18084 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18085 <value>1</value> 18086 </enumeratedValue> 18087 </enumeratedValues> 18088 </field> 18089 <field> 18090 <name>SSD</name> 18091 <description>Slave Select Deasserted.</description> 18092 <bitOffset>5</bitOffset> 18093 <bitWidth>1</bitWidth> 18094 <enumeratedValues> 18095 <enumeratedValue> 18096 <name>clear</name> 18097 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18098 <value>1</value> 18099 </enumeratedValue> 18100 </enumeratedValues> 18101 </field> 18102 <field> 18103 <name>FAULT</name> 18104 <description>Multi-Master Mode Fault.</description> 18105 <bitOffset>8</bitOffset> 18106 <bitWidth>1</bitWidth> 18107 <enumeratedValues> 18108 <enumeratedValue> 18109 <name>clear</name> 18110 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18111 <value>1</value> 18112 </enumeratedValue> 18113 </enumeratedValues> 18114 </field> 18115 <field> 18116 <name>ABORT</name> 18117 <description>Slave Abort Detected.</description> 18118 <bitOffset>9</bitOffset> 18119 <bitWidth>1</bitWidth> 18120 <enumeratedValues> 18121 <enumeratedValue> 18122 <name>clear</name> 18123 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18124 <value>1</value> 18125 </enumeratedValue> 18126 </enumeratedValues> 18127 </field> 18128 <field> 18129 <name>M_DONE</name> 18130 <description>Master Done, set when SPI Master has completed any transactions.</description> 18131 <bitOffset>11</bitOffset> 18132 <bitWidth>1</bitWidth> 18133 <enumeratedValues> 18134 <enumeratedValue> 18135 <name>clear</name> 18136 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18137 <value>1</value> 18138 </enumeratedValue> 18139 </enumeratedValues> 18140 </field> 18141 <field> 18142 <name>TX_OVR</name> 18143 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 18144 <bitOffset>12</bitOffset> 18145 <bitWidth>1</bitWidth> 18146 <enumeratedValues> 18147 <enumeratedValue> 18148 <name>clear</name> 18149 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18150 <value>1</value> 18151 </enumeratedValue> 18152 </enumeratedValues> 18153 </field> 18154 <field> 18155 <name>TX_UND</name> 18156 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 18157 <bitOffset>13</bitOffset> 18158 <bitWidth>1</bitWidth> 18159 <enumeratedValues> 18160 <enumeratedValue> 18161 <name>clear</name> 18162 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18163 <value>1</value> 18164 </enumeratedValue> 18165 </enumeratedValues> 18166 </field> 18167 <field> 18168 <name>RX_OVR</name> 18169 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 18170 <bitOffset>14</bitOffset> 18171 <bitWidth>1</bitWidth> 18172 <enumeratedValues> 18173 <enumeratedValue> 18174 <name>clear</name> 18175 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18176 <value>1</value> 18177 </enumeratedValue> 18178 </enumeratedValues> 18179 </field> 18180 <field> 18181 <name>RX_UND</name> 18182 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 18183 <bitOffset>15</bitOffset> 18184 <bitWidth>1</bitWidth> 18185 <enumeratedValues> 18186 <enumeratedValue> 18187 <name>clear</name> 18188 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18189 <value>1</value> 18190 </enumeratedValue> 18191 </enumeratedValues> 18192 </field> 18193 </fields> 18194 </register> 18195 <register> 18196 <name>INT_EN</name> 18197 <description>Register for enabling interrupts.</description> 18198 <addressOffset>0x24</addressOffset> 18199 <access>read-write</access> 18200 <fields> 18201 <field> 18202 <name>TX_THRESH</name> 18203 <description>TX FIFO Threshold interrupt enable.</description> 18204 <bitOffset>0</bitOffset> 18205 <bitWidth>1</bitWidth> 18206 <enumeratedValues> 18207 <enumeratedValue> 18208 <name>dis</name> 18209 <description>Interrupt is disabled.</description> 18210 <value>0</value> 18211 </enumeratedValue> 18212 <enumeratedValue> 18213 <name>en</name> 18214 <description>Interrupt is enabled.</description> 18215 <value>1</value> 18216 </enumeratedValue> 18217 </enumeratedValues> 18218 </field> 18219 <field> 18220 <name>TX_EMPTY</name> 18221 <description>TX FIFO Empty interrupt enable.</description> 18222 <bitOffset>1</bitOffset> 18223 <bitWidth>1</bitWidth> 18224 <enumeratedValues> 18225 <enumeratedValue> 18226 <name>dis</name> 18227 <description>Interrupt is disabled.</description> 18228 <value>0</value> 18229 </enumeratedValue> 18230 <enumeratedValue> 18231 <name>en</name> 18232 <description>Interrupt is enabled.</description> 18233 <value>1</value> 18234 </enumeratedValue> 18235 </enumeratedValues> 18236 </field> 18237 <field> 18238 <name>RX_THRESH</name> 18239 <description>RX FIFO Threshold Crossed interrupt enable.</description> 18240 <bitOffset>2</bitOffset> 18241 <bitWidth>1</bitWidth> 18242 <enumeratedValues> 18243 <enumeratedValue> 18244 <name>dis</name> 18245 <description>Interrupt is disabled.</description> 18246 <value>0</value> 18247 </enumeratedValue> 18248 <enumeratedValue> 18249 <name>en</name> 18250 <description>Interrupt is enabled.</description> 18251 <value>1</value> 18252 </enumeratedValue> 18253 </enumeratedValues> 18254 </field> 18255 <field> 18256 <name>RX_FULL</name> 18257 <description>RX FIFO FULL interrupt enable.</description> 18258 <bitOffset>3</bitOffset> 18259 <bitWidth>1</bitWidth> 18260 <enumeratedValues> 18261 <enumeratedValue> 18262 <name>dis</name> 18263 <description>Interrupt is disabled.</description> 18264 <value>0</value> 18265 </enumeratedValue> 18266 <enumeratedValue> 18267 <name>en</name> 18268 <description>Interrupt is enabled.</description> 18269 <value>1</value> 18270 </enumeratedValue> 18271 </enumeratedValues> 18272 </field> 18273 <field> 18274 <name>SSA</name> 18275 <description>Slave Select Asserted interrupt enable.</description> 18276 <bitOffset>4</bitOffset> 18277 <bitWidth>1</bitWidth> 18278 <enumeratedValues> 18279 <enumeratedValue> 18280 <name>dis</name> 18281 <description>Interrupt is disabled.</description> 18282 <value>0</value> 18283 </enumeratedValue> 18284 <enumeratedValue> 18285 <name>en</name> 18286 <description>Interrupt is enabled.</description> 18287 <value>1</value> 18288 </enumeratedValue> 18289 </enumeratedValues> 18290 </field> 18291 <field> 18292 <name>SSD</name> 18293 <description>Slave Select Deasserted interrupt enable.</description> 18294 <bitOffset>5</bitOffset> 18295 <bitWidth>1</bitWidth> 18296 <enumeratedValues> 18297 <enumeratedValue> 18298 <name>dis</name> 18299 <description>Interrupt is disabled.</description> 18300 <value>0</value> 18301 </enumeratedValue> 18302 <enumeratedValue> 18303 <name>en</name> 18304 <description>Interrupt is enabled.</description> 18305 <value>1</value> 18306 </enumeratedValue> 18307 </enumeratedValues> 18308 </field> 18309 <field> 18310 <name>FAULT</name> 18311 <description>Multi-Master Mode Fault interrupt enable.</description> 18312 <bitOffset>8</bitOffset> 18313 <bitWidth>1</bitWidth> 18314 <enumeratedValues> 18315 <enumeratedValue> 18316 <name>dis</name> 18317 <description>Interrupt is disabled.</description> 18318 <value>0</value> 18319 </enumeratedValue> 18320 <enumeratedValue> 18321 <name>en</name> 18322 <description>Interrupt is enabled.</description> 18323 <value>1</value> 18324 </enumeratedValue> 18325 </enumeratedValues> 18326 </field> 18327 <field> 18328 <name>ABORT</name> 18329 <description>Slave Abort Detected interrupt enable.</description> 18330 <bitOffset>9</bitOffset> 18331 <bitWidth>1</bitWidth> 18332 <enumeratedValues> 18333 <enumeratedValue> 18334 <name>dis</name> 18335 <description>Interrupt is disabled.</description> 18336 <value>0</value> 18337 </enumeratedValue> 18338 <enumeratedValue> 18339 <name>en</name> 18340 <description>Interrupt is enabled.</description> 18341 <value>1</value> 18342 </enumeratedValue> 18343 </enumeratedValues> 18344 </field> 18345 <field> 18346 <name>M_DONE</name> 18347 <description>Master Done interrupt enable.</description> 18348 <bitOffset>11</bitOffset> 18349 <bitWidth>1</bitWidth> 18350 <enumeratedValues> 18351 <enumeratedValue> 18352 <name>dis</name> 18353 <description>Interrupt is disabled.</description> 18354 <value>0</value> 18355 </enumeratedValue> 18356 <enumeratedValue> 18357 <name>en</name> 18358 <description>Interrupt is enabled.</description> 18359 <value>1</value> 18360 </enumeratedValue> 18361 </enumeratedValues> 18362 </field> 18363 <field> 18364 <name>TX_OVR</name> 18365 <description>Transmit FIFO Overrun interrupt enable.</description> 18366 <bitOffset>12</bitOffset> 18367 <bitWidth>1</bitWidth> 18368 <enumeratedValues> 18369 <enumeratedValue> 18370 <name>dis</name> 18371 <description>Interrupt is disabled.</description> 18372 <value>0</value> 18373 </enumeratedValue> 18374 <enumeratedValue> 18375 <name>en</name> 18376 <description>Interrupt is enabled.</description> 18377 <value>1</value> 18378 </enumeratedValue> 18379 </enumeratedValues> 18380 </field> 18381 <field> 18382 <name>TX_UND</name> 18383 <description>Transmit FIFO Underrun interrupt enable.</description> 18384 <bitOffset>13</bitOffset> 18385 <bitWidth>1</bitWidth> 18386 <enumeratedValues> 18387 <enumeratedValue> 18388 <name>dis</name> 18389 <description>Interrupt is disabled.</description> 18390 <value>0</value> 18391 </enumeratedValue> 18392 <enumeratedValue> 18393 <name>en</name> 18394 <description>Interrupt is enabled.</description> 18395 <value>1</value> 18396 </enumeratedValue> 18397 </enumeratedValues> 18398 </field> 18399 <field> 18400 <name>RX_OVR</name> 18401 <description>Receive FIFO Overrun interrupt enable.</description> 18402 <bitOffset>14</bitOffset> 18403 <bitWidth>1</bitWidth> 18404 <enumeratedValues> 18405 <enumeratedValue> 18406 <name>dis</name> 18407 <description>Interrupt is disabled.</description> 18408 <value>0</value> 18409 </enumeratedValue> 18410 <enumeratedValue> 18411 <name>en</name> 18412 <description>Interrupt is enabled.</description> 18413 <value>1</value> 18414 </enumeratedValue> 18415 </enumeratedValues> 18416 </field> 18417 <field> 18418 <name>RX_UND</name> 18419 <description>Receive FIFO Underrun interrupt enable.</description> 18420 <bitOffset>15</bitOffset> 18421 <bitWidth>1</bitWidth> 18422 <enumeratedValues> 18423 <enumeratedValue> 18424 <name>dis</name> 18425 <description>Interrupt is disabled.</description> 18426 <value>0</value> 18427 </enumeratedValue> 18428 <enumeratedValue> 18429 <name>en</name> 18430 <description>Interrupt is enabled.</description> 18431 <value>1</value> 18432 </enumeratedValue> 18433 </enumeratedValues> 18434 </field> 18435 </fields> 18436 </register> 18437 <register> 18438 <name>WAKE_FL</name> 18439 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 18440 <addressOffset>0x28</addressOffset> 18441 <access>read-write</access> 18442 <fields> 18443 <field> 18444 <name>TX_THRESH</name> 18445 <description>Wake on TX FIFO Threshold Crossed.</description> 18446 <bitOffset>0</bitOffset> 18447 <bitWidth>1</bitWidth> 18448 <enumeratedValues> 18449 <enumeratedValue> 18450 <name>clear</name> 18451 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18452 <value>1</value> 18453 </enumeratedValue> 18454 </enumeratedValues> 18455 </field> 18456 <field> 18457 <name>TX_EMPTY</name> 18458 <description>Wake on TX FIFO Empty.</description> 18459 <bitOffset>1</bitOffset> 18460 <bitWidth>1</bitWidth> 18461 <enumeratedValues> 18462 <enumeratedValue> 18463 <name>clear</name> 18464 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18465 <value>1</value> 18466 </enumeratedValue> 18467 </enumeratedValues> 18468 </field> 18469 <field> 18470 <name>RX_THRESH</name> 18471 <description>Wake on RX FIFO Threshold Crossed.</description> 18472 <bitOffset>2</bitOffset> 18473 <bitWidth>1</bitWidth> 18474 <enumeratedValues> 18475 <enumeratedValue> 18476 <name>clear</name> 18477 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18478 <value>1</value> 18479 </enumeratedValue> 18480 </enumeratedValues> 18481 </field> 18482 <field> 18483 <name>RX_FULL</name> 18484 <description>Wake on RX FIFO Full.</description> 18485 <bitOffset>3</bitOffset> 18486 <bitWidth>1</bitWidth> 18487 <enumeratedValues> 18488 <enumeratedValue> 18489 <name>clear</name> 18490 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 18491 <value>1</value> 18492 </enumeratedValue> 18493 </enumeratedValues> 18494 </field> 18495 </fields> 18496 </register> 18497 <register> 18498 <name>WAKE_EN</name> 18499 <description>Register for wake up enable.</description> 18500 <addressOffset>0x2C</addressOffset> 18501 <access>read-write</access> 18502 <fields> 18503 <field> 18504 <name>TX_THRESH</name> 18505 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 18506 <bitOffset>0</bitOffset> 18507 <bitWidth>1</bitWidth> 18508 <enumeratedValues> 18509 <enumeratedValue> 18510 <name>dis</name> 18511 <description>Wakeup source disabled.</description> 18512 <value>0</value> 18513 </enumeratedValue> 18514 <enumeratedValue> 18515 <name>en</name> 18516 <description>Wakeup source enabled.</description> 18517 <value>1</value> 18518 </enumeratedValue> 18519 </enumeratedValues> 18520 </field> 18521 <field> 18522 <name>TX_EMPTY</name> 18523 <description>Wake on TX FIFO Empty Enable.</description> 18524 <bitOffset>1</bitOffset> 18525 <bitWidth>1</bitWidth> 18526 <enumeratedValues> 18527 <enumeratedValue> 18528 <name>dis</name> 18529 <description>Wakeup source disabled.</description> 18530 <value>0</value> 18531 </enumeratedValue> 18532 <enumeratedValue> 18533 <name>en</name> 18534 <description>Wakeup source enabled.</description> 18535 <value>1</value> 18536 </enumeratedValue> 18537 </enumeratedValues> 18538 </field> 18539 <field> 18540 <name>RX_THRESH</name> 18541 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 18542 <bitOffset>2</bitOffset> 18543 <bitWidth>1</bitWidth> 18544 <enumeratedValues> 18545 <enumeratedValue> 18546 <name>dis</name> 18547 <description>Wakeup source disabled.</description> 18548 <value>0</value> 18549 </enumeratedValue> 18550 <enumeratedValue> 18551 <name>en</name> 18552 <description>Wakeup source enabled.</description> 18553 <value>1</value> 18554 </enumeratedValue> 18555 </enumeratedValues> 18556 </field> 18557 <field> 18558 <name>RX_FULL</name> 18559 <description>Wake on RX FIFO Full Enable.</description> 18560 <bitOffset>3</bitOffset> 18561 <bitWidth>1</bitWidth> 18562 <enumeratedValues> 18563 <enumeratedValue> 18564 <name>dis</name> 18565 <description>Wakeup source disabled.</description> 18566 <value>0</value> 18567 </enumeratedValue> 18568 <enumeratedValue> 18569 <name>en</name> 18570 <description>Wakeup source enabled.</description> 18571 <value>1</value> 18572 </enumeratedValue> 18573 </enumeratedValues> 18574 </field> 18575 </fields> 18576 </register> 18577 <register> 18578 <name>STAT</name> 18579 <description>SPI Status register.</description> 18580 <addressOffset>0x30</addressOffset> 18581 <access>read-only</access> 18582 <fields> 18583 <field> 18584 <name>BUSY</name> 18585 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 18586 <bitOffset>0</bitOffset> 18587 <bitWidth>1</bitWidth> 18588 <enumeratedValues> 18589 <enumeratedValue> 18590 <name>not</name> 18591 <description>SPI not active.</description> 18592 <value>0</value> 18593 </enumeratedValue> 18594 <enumeratedValue> 18595 <name>active</name> 18596 <description>SPI active.</description> 18597 <value>1</value> 18598 </enumeratedValue> 18599 </enumeratedValues> 18600 </field> 18601 </fields> 18602 </register> 18603 </registers> 18604 </peripheral> 18605<!--SPI SPI peripheral.--> 18606 <peripheral derivedFrom="SPI"> 18607 <name>SPI1</name> 18608 <description>SPI peripheral. 1</description> 18609 <baseAddress>0x40047000</baseAddress> 18610 <interrupt> 18611 <name>SPI1</name> 18612 <description>SPI1 IRQ</description> 18613 <value>17</value> 18614 </interrupt> 18615 </peripheral> 18616<!--SPI1 SPI peripheral. 1--> 18617 <peripheral derivedFrom="SPI"> 18618 <name>SPI2</name> 18619 <description>SPI peripheral. 2</description> 18620 <baseAddress>0x40048000</baseAddress> 18621 <interrupt> 18622 <name>SPI2</name> 18623 <description>SPI2 IRQ</description> 18624 <value>18</value> 18625 </interrupt> 18626 </peripheral> 18627<!--SPI2 SPI peripheral. 2--> 18628 <peripheral> 18629 <name>SPIXR</name> 18630 <description>SPIXR peripheral.</description> 18631 <baseAddress>0x4003A000</baseAddress> 18632 <addressBlock> 18633 <offset>0x00</offset> 18634 <size>0x1000</size> 18635 <usage>registers</usage> 18636 </addressBlock> 18637 <registers> 18638 <register> 18639 <name>DATA32</name> 18640 <description>Register for reading and writing the FIFO.</description> 18641 <addressOffset>0x00</addressOffset> 18642 <size>32</size> 18643 <access>read-write</access> 18644 <fields> 18645 <field> 18646 <name>DATA</name> 18647 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 18648 <bitOffset>0</bitOffset> 18649 <bitWidth>32</bitWidth> 18650 </field> 18651 </fields> 18652 </register> 18653 <register> 18654 <dim>2</dim> 18655 <dimIncrement>2</dimIncrement> 18656 <name>DATA16[%s]</name> 18657 <description>Register for reading and writing the FIFO.</description> 18658 <alternateRegister>DATA32</alternateRegister> 18659 <addressOffset>0x00</addressOffset> 18660 <size>16</size> 18661 <access>read-write</access> 18662 <fields> 18663 <field> 18664 <name>DATA</name> 18665 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 18666 <bitOffset>0</bitOffset> 18667 <bitWidth>16</bitWidth> 18668 </field> 18669 </fields> 18670 </register> 18671 <register> 18672 <dim>4</dim> 18673 <dimIncrement>1</dimIncrement> 18674 <name>DATA8[%s]</name> 18675 <description>Register for reading and writing the FIFO.</description> 18676 <alternateRegister>DATA32</alternateRegister> 18677 <addressOffset>0x00</addressOffset> 18678 <size>8</size> 18679 <access>read-write</access> 18680 <fields> 18681 <field> 18682 <name>DATA</name> 18683 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 18684 <bitOffset>0</bitOffset> 18685 <bitWidth>8</bitWidth> 18686 </field> 18687 </fields> 18688 </register> 18689 <register> 18690 <name>CTRL1</name> 18691 <description>Register for controlling SPI peripheral.</description> 18692 <addressOffset>0x04</addressOffset> 18693 <access>read-write</access> 18694 <fields> 18695 <field> 18696 <name>SPIEN</name> 18697 <description>SPI Enable.</description> 18698 <bitOffset>0</bitOffset> 18699 <bitWidth>1</bitWidth> 18700 <enumeratedValues> 18701 <enumeratedValue> 18702 <name>dis</name> 18703 <description>SPI is disabled.</description> 18704 <value>0</value> 18705 </enumeratedValue> 18706 <enumeratedValue> 18707 <name>en</name> 18708 <description>SPI is enabled.</description> 18709 <value>1</value> 18710 </enumeratedValue> 18711 </enumeratedValues> 18712 </field> 18713 <field> 18714 <name>MMEN</name> 18715 <description>Master Mode Enable.</description> 18716 <bitOffset>1</bitOffset> 18717 <bitWidth>1</bitWidth> 18718 <enumeratedValues> 18719 <enumeratedValue> 18720 <name>dis</name> 18721 <description>SPI is Slave mode.</description> 18722 <value>0</value> 18723 </enumeratedValue> 18724 <enumeratedValue> 18725 <name>en</name> 18726 <description>SPI is Master mode.</description> 18727 <value>1</value> 18728 </enumeratedValue> 18729 </enumeratedValues> 18730 </field> 18731 <field> 18732 <name>SSIO</name> 18733 <description>Slave Select 0, IO direction, to support Multi-Master mode, 18734 Slave Select 0 can be input in Master mode. This bit has no 18735 effect in slave mode.</description> 18736 <bitOffset>4</bitOffset> 18737 <bitWidth>1</bitWidth> 18738 <enumeratedValues> 18739 <enumeratedValue> 18740 <name>output</name> 18741 <description>Slave select 0 is output.</description> 18742 <value>0</value> 18743 </enumeratedValue> 18744 <enumeratedValue> 18745 <name>input</name> 18746 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 18747 <value>1</value> 18748 </enumeratedValue> 18749 </enumeratedValues> 18750 </field> 18751 <field> 18752 <name>TX_START</name> 18753 <description>Start Transmit.</description> 18754 <bitOffset>5</bitOffset> 18755 <bitWidth>1</bitWidth> 18756 <enumeratedValues> 18757 <enumeratedValue> 18758 <name>start</name> 18759 <description>Master Initiates a transaction, this bit is 18760 self clearing when transactions are done. If 18761 a transaction completes, and the TX FIFO 18762 is empty, the Master halts, if a transaction 18763 completes, and the TX FIFO is not empty, 18764 the Master initiates another transaction.</description> 18765 <value>1</value> 18766 </enumeratedValue> 18767 </enumeratedValues> 18768 </field> 18769 <field> 18770 <name>SS_CTRL</name> 18771 <description>Slave Select Control.</description> 18772 <bitOffset>8</bitOffset> 18773 <bitWidth>1</bitWidth> 18774 <enumeratedValues> 18775 <enumeratedValue> 18776 <name>deassert</name> 18777 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 18778 <value>0</value> 18779 </enumeratedValue> 18780 <enumeratedValue> 18781 <name>assert</name> 18782 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 18783 <value>1</value> 18784 </enumeratedValue> 18785 </enumeratedValues> 18786 </field> 18787 <field> 18788 <name>SS</name> 18789 <description>Slave Select, when in Master mode selects which Slave devices are 18790 selected. More than one Slave device can be selected.</description> 18791 <bitOffset>16</bitOffset> 18792 <bitWidth>8</bitWidth> 18793 <enumeratedValues> 18794 <enumeratedValue> 18795 <name>SS0</name> 18796 <description>SS0 is selected.</description> 18797 <value>0x1</value> 18798 </enumeratedValue> 18799 <enumeratedValue> 18800 <name>SS1</name> 18801 <description>SS1 is selected.</description> 18802 <value>0x2</value> 18803 </enumeratedValue> 18804 <enumeratedValue> 18805 <name>SS2</name> 18806 <description>SS2 is selected.</description> 18807 <value>0x4</value> 18808 </enumeratedValue> 18809 <enumeratedValue> 18810 <name>SS3</name> 18811 <description>SS3 is selected.</description> 18812 <value>0x8</value> 18813 </enumeratedValue> 18814 <enumeratedValue> 18815 <name>SS4</name> 18816 <description>SS4 is selected.</description> 18817 <value>0x10</value> 18818 </enumeratedValue> 18819 <enumeratedValue> 18820 <name>SS5</name> 18821 <description>SS5 is selected.</description> 18822 <value>0x20</value> 18823 </enumeratedValue> 18824 <enumeratedValue> 18825 <name>SS6</name> 18826 <description>SS6 is selected.</description> 18827 <value>0x40</value> 18828 </enumeratedValue> 18829 <enumeratedValue> 18830 <name>SS7</name> 18831 <description>SS7 is selected.</description> 18832 <value>0x80</value> 18833 </enumeratedValue> 18834 </enumeratedValues> 18835 </field> 18836 </fields> 18837 </register> 18838 <register> 18839 <name>CTRL2</name> 18840 <description>Register for controlling SPI peripheral.</description> 18841 <addressOffset>0x08</addressOffset> 18842 <access>read-write</access> 18843 <fields> 18844 <field> 18845 <name>TX_NUM_CHAR</name> 18846 <description>Nubmer of Characters to transmit.</description> 18847 <bitOffset>0</bitOffset> 18848 <bitWidth>16</bitWidth> 18849 </field> 18850 <field> 18851 <name>RX_NUM_CHAR</name> 18852 <description>Nubmer of Characters to receive.</description> 18853 <bitOffset>16</bitOffset> 18854 <bitWidth>16</bitWidth> 18855 </field> 18856 </fields> 18857 </register> 18858 <register> 18859 <name>CTRL3</name> 18860 <description>Register for controlling SPI peripheral.</description> 18861 <addressOffset>0x0C</addressOffset> 18862 <access>read-write</access> 18863 <fields> 18864 <field> 18865 <name>CPHA</name> 18866 <description>Clock Phase.</description> 18867 <bitOffset>0</bitOffset> 18868 <bitWidth>1</bitWidth> 18869 </field> 18870 <field> 18871 <name>CPOL</name> 18872 <description>Clock Polarity.</description> 18873 <bitOffset>1</bitOffset> 18874 <bitWidth>1</bitWidth> 18875 </field> 18876 <field> 18877 <name>SCLK_FB_INV</name> 18878 <description>Invert SCLK Feedback in Master Mode.</description> 18879 <bitOffset>4</bitOffset> 18880 <bitWidth>1</bitWidth> 18881 <enumeratedValues> 18882 <enumeratedValue> 18883 <name>NON_INV</name> 18884 <description>SCLK is not inverted to Line Receiver.</description> 18885 <value>0</value> 18886 </enumeratedValue> 18887 <enumeratedValue> 18888 <name>INV</name> 18889 <description>SCLK is inverted to Line Receiver.</description> 18890 <value>1</value> 18891 </enumeratedValue> 18892 </enumeratedValues> 18893 </field> 18894 <field> 18895 <name>NUMBITS</name> 18896 <description>Number of Bits per character.</description> 18897 <bitOffset>8</bitOffset> 18898 <bitWidth>4</bitWidth> 18899 <enumeratedValues> 18900 <enumeratedValue> 18901 <name>0</name> 18902 <description>16 bits per character.</description> 18903 <value>0</value> 18904 </enumeratedValue> 18905 </enumeratedValues> 18906 </field> 18907 <field> 18908 <name>DATA_WIDTH</name> 18909 <description>SPI Data width.</description> 18910 <bitOffset>12</bitOffset> 18911 <bitWidth>2</bitWidth> 18912 <enumeratedValues> 18913 <enumeratedValue> 18914 <name>Mono</name> 18915 <description>1 data pin.</description> 18916 <value>0</value> 18917 </enumeratedValue> 18918 <enumeratedValue> 18919 <name>Dual</name> 18920 <description>2 data pins.</description> 18921 <value>1</value> 18922 </enumeratedValue> 18923 <enumeratedValue> 18924 <name>Quad</name> 18925 <description>4 data pins.</description> 18926 <value>2</value> 18927 </enumeratedValue> 18928 </enumeratedValues> 18929 </field> 18930 <field> 18931 <name>THREE_WIRE</name> 18932 <description>Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.</description> 18933 <bitOffset>15</bitOffset> 18934 <bitWidth>1</bitWidth> 18935 <enumeratedValues> 18936 <enumeratedValue> 18937 <name>dis</name> 18938 <description>Use four wire mode (Mono only).</description> 18939 <value>0</value> 18940 </enumeratedValue> 18941 <enumeratedValue> 18942 <name>en</name> 18943 <description>Use three wire mode.</description> 18944 <value>1</value> 18945 </enumeratedValue> 18946 </enumeratedValues> 18947 </field> 18948 <field> 18949 <name>SSPOL</name> 18950 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 18951 <bitOffset>16</bitOffset> 18952 <bitWidth>8</bitWidth> 18953 <enumeratedValues> 18954 <enumeratedValue> 18955 <name>SS0_high</name> 18956 <description>SS0 active high.</description> 18957 <value>0x1</value> 18958 </enumeratedValue> 18959 <enumeratedValue> 18960 <name>SS1_high</name> 18961 <description>SS1 active high.</description> 18962 <value>0x2</value> 18963 </enumeratedValue> 18964 <enumeratedValue> 18965 <name>SS2_high</name> 18966 <description>SS2 active high.</description> 18967 <value>0x4</value> 18968 </enumeratedValue> 18969 <enumeratedValue> 18970 <name>SS3_high</name> 18971 <description>SS3 active high.</description> 18972 <value>0x8</value> 18973 </enumeratedValue> 18974 <enumeratedValue> 18975 <name>SS4_high</name> 18976 <description>SS4 active high.</description> 18977 <value>0x10</value> 18978 </enumeratedValue> 18979 <enumeratedValue> 18980 <name>SS5_high</name> 18981 <description>SS5 active high.</description> 18982 <value>0x20</value> 18983 </enumeratedValue> 18984 <enumeratedValue> 18985 <name>SS6_high</name> 18986 <description>SS6 active high.</description> 18987 <value>0x40</value> 18988 </enumeratedValue> 18989 <enumeratedValue> 18990 <name>SS7_high</name> 18991 <description>SS7 active high.</description> 18992 <value>0x80</value> 18993 </enumeratedValue> 18994 </enumeratedValues> 18995 </field> 18996 </fields> 18997 </register> 18998 <register> 18999 <name>SS_TIME</name> 19000 <description>Register for controlling SPI peripheral.</description> 19001 <addressOffset>0x10</addressOffset> 19002 <access>read-write</access> 19003 <fields> 19004 <field> 19005 <name>SSACT1</name> 19006 <description>Slave Select Action delay 1.</description> 19007 <bitOffset>0</bitOffset> 19008 <bitWidth>8</bitWidth> 19009 <enumeratedValues> 19010 <enumeratedValue> 19011 <name>256</name> 19012 <description>256 system clocks between SS active and first serial clock edge.</description> 19013 <value>0</value> 19014 </enumeratedValue> 19015 </enumeratedValues> 19016 </field> 19017 <field> 19018 <name>SSACT2</name> 19019 <description>Slave Select Action delay 2.</description> 19020 <bitOffset>8</bitOffset> 19021 <bitWidth>8</bitWidth> 19022 <enumeratedValues> 19023 <enumeratedValue> 19024 <name>256</name> 19025 <description>256 system clocks between last serial clock edge and SS inactive.</description> 19026 <value>0</value> 19027 </enumeratedValue> 19028 </enumeratedValues> 19029 </field> 19030 <field> 19031 <name>SSINACT</name> 19032 <description>Slave Select Inactive delay.</description> 19033 <bitOffset>16</bitOffset> 19034 <bitWidth>8</bitWidth> 19035 <enumeratedValues> 19036 <enumeratedValue> 19037 <name>256</name> 19038 <description>256 system clocks between transactions.</description> 19039 <value>0</value> 19040 </enumeratedValue> 19041 </enumeratedValues> 19042 </field> 19043 </fields> 19044 </register> 19045 <register> 19046 <name>BRG_CTRL</name> 19047 <description>Register for controlling SPI clock rate.</description> 19048 <addressOffset>0x14</addressOffset> 19049 <access>read-write</access> 19050 <fields> 19051 <field> 19052 <name>LOW</name> 19053 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 19054 <bitOffset>0</bitOffset> 19055 <bitWidth>8</bitWidth> 19056 <enumeratedValues> 19057 <enumeratedValue> 19058 <name>Dis</name> 19059 <description>Duty cycle control of serial clock generation is disabled.</description> 19060 <value>0</value> 19061 </enumeratedValue> 19062 </enumeratedValues> 19063 </field> 19064 <field> 19065 <name>HI</name> 19066 <description>High duty cycle control. In timer mode, reload[15:8].</description> 19067 <bitOffset>8</bitOffset> 19068 <bitWidth>8</bitWidth> 19069 <enumeratedValues> 19070 <enumeratedValue> 19071 <name>Dis</name> 19072 <description>Duty cycle control of serial clock generation is disabled.</description> 19073 <value>0</value> 19074 </enumeratedValue> 19075 </enumeratedValues> 19076 </field> 19077 <field> 19078 <name>SCALE</name> 19079 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 19080 <bitOffset>16</bitOffset> 19081 <bitWidth>4</bitWidth> 19082 </field> 19083 </fields> 19084 </register> 19085 <register> 19086 <name>DMA</name> 19087 <description>Register for controlling DMA.</description> 19088 <addressOffset>0x1C</addressOffset> 19089 <access>read-write</access> 19090 <fields> 19091 <field> 19092 <name>TX_FIFO_LEVEL</name> 19093 <description>Transmit FIFO level that will trigger a DMA request, also level for 19094 threshold status. When TX FIFO has fewer than this many bytes, the 19095 associated events and conditions are triggered.</description> 19096 <bitOffset>0</bitOffset> 19097 <bitWidth>5</bitWidth> 19098 </field> 19099 <field> 19100 <name>TX_FIFO_EN</name> 19101 <description>Transmit FIFO enabled for SPI transactions.</description> 19102 <bitOffset>6</bitOffset> 19103 <bitWidth>1</bitWidth> 19104 <enumeratedValues> 19105 <enumeratedValue> 19106 <name>dis</name> 19107 <description>Transmit FIFO is not enabled.</description> 19108 <value>0</value> 19109 </enumeratedValue> 19110 <enumeratedValue> 19111 <name>en</name> 19112 <description>Transmit FIFO is enabled.</description> 19113 <value>1</value> 19114 </enumeratedValue> 19115 </enumeratedValues> 19116 </field> 19117 <field> 19118 <name>TX_FIFO_CLEAR</name> 19119 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 19120 pointers. This should be done when FIFO is not being accessed on the SPI side. 19121 </description> 19122 <bitOffset>7</bitOffset> 19123 <bitWidth>1</bitWidth> 19124 <enumeratedValues> 19125 <enumeratedValue> 19126 <name>CLEAR</name> 19127 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 19128 <value>1</value> 19129 </enumeratedValue> 19130 </enumeratedValues> 19131 </field> 19132 <field> 19133 <name>TX_FIFO_CNT</name> 19134 <description>Count of entries in TX FIFO.</description> 19135 <bitOffset>8</bitOffset> 19136 <bitWidth>5</bitWidth> 19137 </field> 19138 <field> 19139 <name>TX_DMA_EN</name> 19140 <description>TX DMA Enable.</description> 19141 <bitOffset>15</bitOffset> 19142 <bitWidth>1</bitWidth> 19143 <enumeratedValues> 19144 <enumeratedValue> 19145 <name>DIS</name> 19146 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 19147 <value>0</value> 19148 </enumeratedValue> 19149 <enumeratedValue> 19150 <name>en</name> 19151 <description>TX DMA requests are enabled.</description> 19152 <value>1</value> 19153 </enumeratedValue> 19154 </enumeratedValues> 19155 </field> 19156 <field> 19157 <name>RX_FIFO_LEVEL</name> 19158 <description>Receive FIFO level that will trigger a DMA request, also level for 19159 threshold status. When RX FIFO has more than this many bytes, the 19160 associated events and conditions are triggered.</description> 19161 <bitOffset>16</bitOffset> 19162 <bitWidth>6</bitWidth> 19163 </field> 19164 <field> 19165 <name>RX_FIFO_EN</name> 19166 <description>Receive FIFO enabled for SPI transactions.</description> 19167 <bitOffset>22</bitOffset> 19168 <bitWidth>1</bitWidth> 19169 <enumeratedValues> 19170 <enumeratedValue> 19171 <name>DIS</name> 19172 <description>Receive FIFO is not enabled.</description> 19173 <value>0</value> 19174 </enumeratedValue> 19175 <enumeratedValue> 19176 <name>en</name> 19177 <description>Receive FIFO is enabled.</description> 19178 <value>1</value> 19179 </enumeratedValue> 19180 </enumeratedValues> 19181 </field> 19182 <field> 19183 <name>RX_FIFO_CLEAR</name> 19184 <description>Clear RX FIFO, clear is accomplished by resetting the read and write 19185 pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 19186 <bitOffset>23</bitOffset> 19187 <bitWidth>1</bitWidth> 19188 <enumeratedValues> 19189 <enumeratedValue> 19190 <name>CLEAR</name> 19191 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 19192 <value>1</value> 19193 </enumeratedValue> 19194 </enumeratedValues> 19195 </field> 19196 <field> 19197 <name>RX_FIFO_CNT</name> 19198 <description>Count of entries in RX FIFO.</description> 19199 <bitOffset>24</bitOffset> 19200 <bitWidth>6</bitWidth> 19201 </field> 19202 <field> 19203 <name>RX_DMA_EN</name> 19204 <description>RX DMA Enable.</description> 19205 <bitOffset>31</bitOffset> 19206 <bitWidth>1</bitWidth> 19207 <enumeratedValues> 19208 <enumeratedValue> 19209 <name>dis</name> 19210 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 19211 <value>0</value> 19212 </enumeratedValue> 19213 <enumeratedValue> 19214 <name>en</name> 19215 <description>RX DMA requests are enabled.</description> 19216 <value>1</value> 19217 </enumeratedValue> 19218 </enumeratedValues> 19219 </field> 19220 </fields> 19221 </register> 19222 <register> 19223 <name>INT_FL</name> 19224 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 19225 <addressOffset>0x20</addressOffset> 19226 <access>read-write</access> 19227 <fields> 19228 <field> 19229 <name>TX_THRESH</name> 19230 <description>TX FIFO Threshold Crossed.</description> 19231 <bitOffset>0</bitOffset> 19232 <bitWidth>1</bitWidth> 19233 <enumeratedValues> 19234 <enumeratedValue> 19235 <name>clear</name> 19236 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19237 <value>1</value> 19238 </enumeratedValue> 19239 </enumeratedValues> 19240 </field> 19241 <field> 19242 <name>TX_EMPTY</name> 19243 <description>TX FIFO Empty.</description> 19244 <bitOffset>1</bitOffset> 19245 <bitWidth>1</bitWidth> 19246 <enumeratedValues> 19247 <enumeratedValue> 19248 <name>clear</name> 19249 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19250 <value>1</value> 19251 </enumeratedValue> 19252 </enumeratedValues> 19253 </field> 19254 <field> 19255 <name>RX_THRESH</name> 19256 <description>RX FIFO Threshold Crossed.</description> 19257 <bitOffset>2</bitOffset> 19258 <bitWidth>1</bitWidth> 19259 <enumeratedValues> 19260 <enumeratedValue> 19261 <name>clear</name> 19262 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19263 <value>1</value> 19264 </enumeratedValue> 19265 </enumeratedValues> 19266 </field> 19267 <field> 19268 <name>RX_FULL</name> 19269 <description>RX FIFO FULL.</description> 19270 <bitOffset>3</bitOffset> 19271 <bitWidth>1</bitWidth> 19272 <enumeratedValues> 19273 <enumeratedValue> 19274 <name>clear</name> 19275 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19276 <value>1</value> 19277 </enumeratedValue> 19278 </enumeratedValues> 19279 </field> 19280 <field> 19281 <name>SSA</name> 19282 <description>Slave Select Asserted.</description> 19283 <bitOffset>4</bitOffset> 19284 <bitWidth>1</bitWidth> 19285 <enumeratedValues> 19286 <enumeratedValue> 19287 <name>clear</name> 19288 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19289 <value>1</value> 19290 </enumeratedValue> 19291 </enumeratedValues> 19292 </field> 19293 <field> 19294 <name>SSD</name> 19295 <description>Slave Select Deasserted.</description> 19296 <bitOffset>5</bitOffset> 19297 <bitWidth>1</bitWidth> 19298 <enumeratedValues> 19299 <enumeratedValue> 19300 <name>clear</name> 19301 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19302 <value>1</value> 19303 </enumeratedValue> 19304 </enumeratedValues> 19305 </field> 19306 <field> 19307 <name>FAULT</name> 19308 <description>Multi-Master Mode Fault.</description> 19309 <bitOffset>8</bitOffset> 19310 <bitWidth>1</bitWidth> 19311 <enumeratedValues> 19312 <enumeratedValue> 19313 <name>clear</name> 19314 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19315 <value>1</value> 19316 </enumeratedValue> 19317 </enumeratedValues> 19318 </field> 19319 <field> 19320 <name>ABORT</name> 19321 <description>Slave Abort Detected.</description> 19322 <bitOffset>9</bitOffset> 19323 <bitWidth>1</bitWidth> 19324 <enumeratedValues> 19325 <enumeratedValue> 19326 <name>clear</name> 19327 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19328 <value>1</value> 19329 </enumeratedValue> 19330 </enumeratedValues> 19331 </field> 19332 <field> 19333 <name>M_DONE</name> 19334 <description>Master Done, set when SPI Master has completed any transactions.</description> 19335 <bitOffset>11</bitOffset> 19336 <bitWidth>1</bitWidth> 19337 <enumeratedValues> 19338 <enumeratedValue> 19339 <name>clear</name> 19340 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19341 <value>1</value> 19342 </enumeratedValue> 19343 </enumeratedValues> 19344 </field> 19345 <field> 19346 <name>TX_OVR</name> 19347 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data 19348 to a full transmit FIFO.</description> 19349 <bitOffset>12</bitOffset> 19350 <bitWidth>1</bitWidth> 19351 <enumeratedValues> 19352 <enumeratedValue> 19353 <name>clear</name> 19354 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19355 <value>1</value> 19356 </enumeratedValue> 19357 </enumeratedValues> 19358 </field> 19359 <field> 19360 <name>TX_UND</name> 19361 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data 19362 from an empty transmit FIFO.</description> 19363 <bitOffset>13</bitOffset> 19364 <bitWidth>1</bitWidth> 19365 <enumeratedValues> 19366 <enumeratedValue> 19367 <name>clear</name> 19368 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19369 <value>1</value> 19370 </enumeratedValue> 19371 </enumeratedValues> 19372 </field> 19373 <field> 19374 <name>RX_OVR</name> 19375 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 19376 <bitOffset>14</bitOffset> 19377 <bitWidth>1</bitWidth> 19378 <enumeratedValues> 19379 <enumeratedValue> 19380 <name>clear</name> 19381 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19382 <value>1</value> 19383 </enumeratedValue> 19384 </enumeratedValues> 19385 </field> 19386 <field> 19387 <name>RX_UND</name> 19388 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 19389 <bitOffset>15</bitOffset> 19390 <bitWidth>1</bitWidth> 19391 <enumeratedValues> 19392 <enumeratedValue> 19393 <name>clear</name> 19394 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19395 <value>1</value> 19396 </enumeratedValue> 19397 </enumeratedValues> 19398 </field> 19399 </fields> 19400 </register> 19401 <register> 19402 <name>INT_EN</name> 19403 <description>Register for enabling interrupts.</description> 19404 <addressOffset>0x24</addressOffset> 19405 <access>read-write</access> 19406 <fields> 19407 <field> 19408 <name>TX_THRESH</name> 19409 <description>TX FIFO Threshold interrupt enable.</description> 19410 <bitOffset>0</bitOffset> 19411 <bitWidth>1</bitWidth> 19412 <enumeratedValues> 19413 <enumeratedValue> 19414 <name>dis</name> 19415 <description>Interrupt is disabled.</description> 19416 <value>0</value> 19417 </enumeratedValue> 19418 <enumeratedValue> 19419 <name>en</name> 19420 <description>Interrupt is enabled.</description> 19421 <value>1</value> 19422 </enumeratedValue> 19423 </enumeratedValues> 19424 </field> 19425 <field> 19426 <name>TX_EMPTY</name> 19427 <description>TX FIFO Empty interrupt enable.</description> 19428 <bitOffset>1</bitOffset> 19429 <bitWidth>1</bitWidth> 19430 <enumeratedValues> 19431 <enumeratedValue> 19432 <name>dis</name> 19433 <description>Interrupt is disabled.</description> 19434 <value>0</value> 19435 </enumeratedValue> 19436 <enumeratedValue> 19437 <name>en</name> 19438 <description>Interrupt is enabled.</description> 19439 <value>1</value> 19440 </enumeratedValue> 19441 </enumeratedValues> 19442 </field> 19443 <field> 19444 <name>RX_THRESH</name> 19445 <description>RX FIFO Threshold Crossed interrupt enable.</description> 19446 <bitOffset>2</bitOffset> 19447 <bitWidth>1</bitWidth> 19448 <enumeratedValues> 19449 <enumeratedValue> 19450 <name>dis</name> 19451 <description>Interrupt is disabled.</description> 19452 <value>0</value> 19453 </enumeratedValue> 19454 <enumeratedValue> 19455 <name>en</name> 19456 <description>Interrupt is enabled.</description> 19457 <value>1</value> 19458 </enumeratedValue> 19459 </enumeratedValues> 19460 </field> 19461 <field> 19462 <name>RX_FULL</name> 19463 <description>RX FIFO FULL interrupt enable.</description> 19464 <bitOffset>3</bitOffset> 19465 <bitWidth>1</bitWidth> 19466 <enumeratedValues> 19467 <enumeratedValue> 19468 <name>dis</name> 19469 <description>Interrupt is disabled.</description> 19470 <value>0</value> 19471 </enumeratedValue> 19472 <enumeratedValue> 19473 <name>en</name> 19474 <description>Interrupt is enabled.</description> 19475 <value>1</value> 19476 </enumeratedValue> 19477 </enumeratedValues> 19478 </field> 19479 <field> 19480 <name>SSA</name> 19481 <description>Slave Select Asserted interrupt enable.</description> 19482 <bitOffset>4</bitOffset> 19483 <bitWidth>1</bitWidth> 19484 <enumeratedValues> 19485 <enumeratedValue> 19486 <name>dis</name> 19487 <description>Interrupt is disabled.</description> 19488 <value>0</value> 19489 </enumeratedValue> 19490 <enumeratedValue> 19491 <name>en</name> 19492 <description>Interrupt is enabled.</description> 19493 <value>1</value> 19494 </enumeratedValue> 19495 </enumeratedValues> 19496 </field> 19497 <field> 19498 <name>SSD</name> 19499 <description>Slave Select Deasserted interrupt enable.</description> 19500 <bitOffset>5</bitOffset> 19501 <bitWidth>1</bitWidth> 19502 <enumeratedValues> 19503 <enumeratedValue> 19504 <name>dis</name> 19505 <description>Interrupt is disabled.</description> 19506 <value>0</value> 19507 </enumeratedValue> 19508 <enumeratedValue> 19509 <name>en</name> 19510 <description>Interrupt is enabled.</description> 19511 <value>1</value> 19512 </enumeratedValue> 19513 </enumeratedValues> 19514 </field> 19515 <field> 19516 <name>FAULT</name> 19517 <description>Multi-Master Mode Fault interrupt enable.</description> 19518 <bitOffset>8</bitOffset> 19519 <bitWidth>1</bitWidth> 19520 <enumeratedValues> 19521 <enumeratedValue> 19522 <name>dis</name> 19523 <description>Interrupt is disabled.</description> 19524 <value>0</value> 19525 </enumeratedValue> 19526 <enumeratedValue> 19527 <name>en</name> 19528 <description>Interrupt is enabled.</description> 19529 <value>1</value> 19530 </enumeratedValue> 19531 </enumeratedValues> 19532 </field> 19533 <field> 19534 <name>ABORT</name> 19535 <description>Slave Abort Detected interrupt enable.</description> 19536 <bitOffset>9</bitOffset> 19537 <bitWidth>1</bitWidth> 19538 <enumeratedValues> 19539 <enumeratedValue> 19540 <name>dis</name> 19541 <description>Interrupt is disabled.</description> 19542 <value>0</value> 19543 </enumeratedValue> 19544 <enumeratedValue> 19545 <name>en</name> 19546 <description>Interrupt is enabled.</description> 19547 <value>1</value> 19548 </enumeratedValue> 19549 </enumeratedValues> 19550 </field> 19551 <field> 19552 <name>M_DONE</name> 19553 <description>Master Done interrupt enable.</description> 19554 <bitOffset>11</bitOffset> 19555 <bitWidth>1</bitWidth> 19556 <enumeratedValues> 19557 <enumeratedValue> 19558 <name>dis</name> 19559 <description>Interrupt is disabled.</description> 19560 <value>0</value> 19561 </enumeratedValue> 19562 <enumeratedValue> 19563 <name>en</name> 19564 <description>Interrupt is enabled.</description> 19565 <value>1</value> 19566 </enumeratedValue> 19567 </enumeratedValues> 19568 </field> 19569 <field> 19570 <name>TX_OVR</name> 19571 <description>Transmit FIFO Overrun interrupt enable.</description> 19572 <bitOffset>12</bitOffset> 19573 <bitWidth>1</bitWidth> 19574 <enumeratedValues> 19575 <enumeratedValue> 19576 <name>dis</name> 19577 <description>Interrupt is disabled.</description> 19578 <value>0</value> 19579 </enumeratedValue> 19580 <enumeratedValue> 19581 <name>en</name> 19582 <description>Interrupt is enabled.</description> 19583 <value>1</value> 19584 </enumeratedValue> 19585 </enumeratedValues> 19586 </field> 19587 <field> 19588 <name>TX_UND</name> 19589 <description>Transmit FIFO Underrun interrupt enable.</description> 19590 <bitOffset>13</bitOffset> 19591 <bitWidth>1</bitWidth> 19592 <enumeratedValues> 19593 <enumeratedValue> 19594 <name>dis</name> 19595 <description>Interrupt is disabled.</description> 19596 <value>0</value> 19597 </enumeratedValue> 19598 <enumeratedValue> 19599 <name>en</name> 19600 <description>Interrupt is enabled.</description> 19601 <value>1</value> 19602 </enumeratedValue> 19603 </enumeratedValues> 19604 </field> 19605 <field> 19606 <name>RX_OVR</name> 19607 <description>Receive FIFO Overrun interrupt enable.</description> 19608 <bitOffset>14</bitOffset> 19609 <bitWidth>1</bitWidth> 19610 <enumeratedValues> 19611 <enumeratedValue> 19612 <name>dis</name> 19613 <description>Interrupt is disabled.</description> 19614 <value>0</value> 19615 </enumeratedValue> 19616 <enumeratedValue> 19617 <name>en</name> 19618 <description>Interrupt is enabled.</description> 19619 <value>1</value> 19620 </enumeratedValue> 19621 </enumeratedValues> 19622 </field> 19623 <field> 19624 <name>RX_UND</name> 19625 <description>Receive FIFO Underrun interrupt enable.</description> 19626 <bitOffset>15</bitOffset> 19627 <bitWidth>1</bitWidth> 19628 <enumeratedValues> 19629 <enumeratedValue> 19630 <name>dis</name> 19631 <description>Interrupt is disabled.</description> 19632 <value>0</value> 19633 </enumeratedValue> 19634 <enumeratedValue> 19635 <name>en</name> 19636 <description>Interrupt is enabled.</description> 19637 <value>1</value> 19638 </enumeratedValue> 19639 </enumeratedValues> 19640 </field> 19641 </fields> 19642 </register> 19643 <register> 19644 <name>WAKE_FL</name> 19645 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 19646 <addressOffset>0x28</addressOffset> 19647 <access>read-write</access> 19648 <fields> 19649 <field> 19650 <name>TX_THRESH</name> 19651 <description>Wake on TX FIFO Threshold Crossed.</description> 19652 <bitOffset>0</bitOffset> 19653 <bitWidth>1</bitWidth> 19654 <enumeratedValues> 19655 <enumeratedValue> 19656 <name>clear</name> 19657 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19658 <value>1</value> 19659 </enumeratedValue> 19660 </enumeratedValues> 19661 </field> 19662 <field> 19663 <name>TX_EMPTY</name> 19664 <description>Wake on TX FIFO Empty.</description> 19665 <bitOffset>1</bitOffset> 19666 <bitWidth>1</bitWidth> 19667 <enumeratedValues> 19668 <enumeratedValue> 19669 <name>clear</name> 19670 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19671 <value>1</value> 19672 </enumeratedValue> 19673 </enumeratedValues> 19674 </field> 19675 <field> 19676 <name>RX_THRESH</name> 19677 <description>Wake on RX FIFO Threshold Crossed.</description> 19678 <bitOffset>2</bitOffset> 19679 <bitWidth>1</bitWidth> 19680 <enumeratedValues> 19681 <enumeratedValue> 19682 <name>clear</name> 19683 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19684 <value>1</value> 19685 </enumeratedValue> 19686 </enumeratedValues> 19687 </field> 19688 <field> 19689 <name>RX_FULL</name> 19690 <description>Wake on RX FIFO Full.</description> 19691 <bitOffset>3</bitOffset> 19692 <bitWidth>1</bitWidth> 19693 <enumeratedValues> 19694 <enumeratedValue> 19695 <name>clear</name> 19696 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 19697 <value>1</value> 19698 </enumeratedValue> 19699 </enumeratedValues> 19700 </field> 19701 </fields> 19702 </register> 19703 <register> 19704 <name>WAKE_EN</name> 19705 <description>Register for wake up enable.</description> 19706 <addressOffset>0x2C</addressOffset> 19707 <access>read-write</access> 19708 <fields> 19709 <field> 19710 <name>TX_THRESH</name> 19711 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 19712 <bitOffset>0</bitOffset> 19713 <bitWidth>1</bitWidth> 19714 <enumeratedValues> 19715 <enumeratedValue> 19716 <name>dis</name> 19717 <description>Wakeup source disabled.</description> 19718 <value>0</value> 19719 </enumeratedValue> 19720 <enumeratedValue> 19721 <name>en</name> 19722 <description>Wakeup source enabled.</description> 19723 <value>1</value> 19724 </enumeratedValue> 19725 </enumeratedValues> 19726 </field> 19727 <field> 19728 <name>TX_EMPTY</name> 19729 <description>Wake on TX FIFO Empty Enable.</description> 19730 <bitOffset>1</bitOffset> 19731 <bitWidth>1</bitWidth> 19732 <enumeratedValues> 19733 <enumeratedValue> 19734 <name>dis</name> 19735 <description>Wakeup source disabled.</description> 19736 <value>0</value> 19737 </enumeratedValue> 19738 <enumeratedValue> 19739 <name>en</name> 19740 <description>Wakeup source enabled.</description> 19741 <value>1</value> 19742 </enumeratedValue> 19743 </enumeratedValues> 19744 </field> 19745 <field> 19746 <name>RX_THRESH</name> 19747 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 19748 <bitOffset>2</bitOffset> 19749 <bitWidth>1</bitWidth> 19750 <enumeratedValues> 19751 <enumeratedValue> 19752 <name>dis</name> 19753 <description>Wakeup source disabled.</description> 19754 <value>0</value> 19755 </enumeratedValue> 19756 <enumeratedValue> 19757 <name>en</name> 19758 <description>Wakeup source enabled.</description> 19759 <value>1</value> 19760 </enumeratedValue> 19761 </enumeratedValues> 19762 </field> 19763 <field> 19764 <name>RX_FULL</name> 19765 <description>Wake on RX FIFO Full Enable.</description> 19766 <bitOffset>3</bitOffset> 19767 <bitWidth>1</bitWidth> 19768 <enumeratedValues> 19769 <enumeratedValue> 19770 <name>dis</name> 19771 <description>Wakeup source disabled.</description> 19772 <value>0</value> 19773 </enumeratedValue> 19774 <enumeratedValue> 19775 <name>en</name> 19776 <description>Wakeup source enabled.</description> 19777 <value>1</value> 19778 </enumeratedValue> 19779 </enumeratedValues> 19780 </field> 19781 </fields> 19782 </register> 19783 <register> 19784 <name>STAT</name> 19785 <description>SPI Status register.</description> 19786 <addressOffset>0x30</addressOffset> 19787 <access>read-only</access> 19788 <fields> 19789 <field> 19790 <name>BUSY</name> 19791 <description>SPI active status. In Master mode, set when transaction starts, 19792 cleared when last bit of last character is acted upon and Slave Select 19793 de-assertion would occur. In Slave mode, set when Slave Select is 19794 asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 19795 </description> 19796 <bitOffset>0</bitOffset> 19797 <bitWidth>1</bitWidth> 19798 <enumeratedValues> 19799 <enumeratedValue> 19800 <name>not</name> 19801 <description>SPI not active.</description> 19802 <value>0</value> 19803 </enumeratedValue> 19804 <enumeratedValue> 19805 <name>active</name> 19806 <description>SPI active.</description> 19807 <value>1</value> 19808 </enumeratedValue> 19809 </enumeratedValues> 19810 </field> 19811 </fields> 19812 </register> 19813 <register> 19814 <name>XMEM_CTRL</name> 19815 <description>Register to control external memory.</description> 19816 <addressOffset>0x34</addressOffset> 19817 <access>read-write</access> 19818 <fields> 19819 <field> 19820 <name>RD_CMD</name> 19821 <description>Read command.</description> 19822 <bitOffset>0</bitOffset> 19823 <bitWidth>8</bitWidth> 19824 </field> 19825 <field> 19826 <name>WR_CMD</name> 19827 <description>Write command.</description> 19828 <bitOffset>8</bitOffset> 19829 <bitWidth>8</bitWidth> 19830 </field> 19831 <field> 19832 <name>DUMMY_CLK</name> 19833 <description>Dummy clocks.</description> 19834 <bitOffset>16</bitOffset> 19835 <bitWidth>8</bitWidth> 19836 </field> 19837 <field> 19838 <name>XMEM_EN</name> 19839 <description>XMEM enable.</description> 19840 <bitOffset>31</bitOffset> 19841 <bitWidth>1</bitWidth> 19842 </field> 19843 </fields> 19844 </register> 19845 </registers> 19846 </peripheral> 19847<!--SPIXR SPIXR peripheral.--> 19848 <peripheral> 19849 <name>SPIXFC</name> 19850 <description>SPI XiP Flash Configuration Controller</description> 19851 <baseAddress>0x40027000</baseAddress> 19852 <addressBlock> 19853 <offset>0</offset> 19854 <size>0x1000</size> 19855 <usage>registers</usage> 19856 </addressBlock> 19857 <interrupt> 19858 <name>SPIXFC</name> 19859 <description>SPIXFC IRQ</description> 19860 <value>38</value> 19861 </interrupt> 19862 <registers> 19863 <register> 19864 <name>CFG</name> 19865 <description>Configuration Register.</description> 19866 <addressOffset>0x00</addressOffset> 19867 <fields> 19868 <field> 19869 <name>SSEL</name> 19870 <description>Slaves Select.</description> 19871 <bitOffset>0</bitOffset> 19872 <bitWidth>3</bitWidth> 19873 <enumeratedValues> 19874 <enumeratedValue> 19875 <name>Slave_0</name> 19876 <description>Slave 0 is selected.</description> 19877 <value>0</value> 19878 </enumeratedValue> 19879 <enumeratedValue> 19880 <name>Slave_1</name> 19881 <description>Slave 1 is selected.</description> 19882 <value>1</value> 19883 </enumeratedValue> 19884 </enumeratedValues> 19885 </field> 19886 <field> 19887 <name>MODE</name> 19888 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 19889 <bitOffset>4</bitOffset> 19890 <bitWidth>2</bitWidth> 19891 <enumeratedValues> 19892 <enumeratedValue> 19893 <name>SPIX_Mode_0</name> 19894 <description>SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0.</description> 19895 <value>0</value> 19896 </enumeratedValue> 19897 <enumeratedValue> 19898 <name>SPIX_Mode_3</name> 19899 <description>SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1.</description> 19900 <value>3</value> 19901 </enumeratedValue> 19902 </enumeratedValues> 19903 </field> 19904 <field> 19905 <name>PAGE_SIZE</name> 19906 <description>Page Size.</description> 19907 <bitOffset>6</bitOffset> 19908 <bitWidth>2</bitWidth> 19909 <enumeratedValues> 19910 <enumeratedValue> 19911 <name>4_bytes</name> 19912 <description>4 bytes.</description> 19913 <value>0</value> 19914 </enumeratedValue> 19915 <enumeratedValue> 19916 <name>8_bytes</name> 19917 <description>8 bytes.</description> 19918 <value>1</value> 19919 </enumeratedValue> 19920 <enumeratedValue> 19921 <name>16_bytes</name> 19922 <description>16 bytes.</description> 19923 <value>2</value> 19924 </enumeratedValue> 19925 <enumeratedValue> 19926 <name>32_bytes</name> 19927 <description>32 bytes.</description> 19928 <value>3</value> 19929 </enumeratedValue> 19930 </enumeratedValues> 19931 </field> 19932 <field> 19933 <name>HI_CLK</name> 19934 <description>SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high.</description> 19935 <bitOffset>8</bitOffset> 19936 <bitWidth>4</bitWidth> 19937 <enumeratedValues> 19938 <enumeratedValue> 19939 <name>16_SCLK</name> 19940 <description>16 system clocks.</description> 19941 <value>0</value> 19942 </enumeratedValue> 19943 </enumeratedValues> 19944 </field> 19945 <field> 19946 <name>LO_CLK</name> 19947 <description>SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low.</description> 19948 <bitOffset>12</bitOffset> 19949 <bitWidth>4</bitWidth> 19950 <enumeratedValues> 19951 <enumeratedValue> 19952 <name>16_SCLK</name> 19953 <description>16 system clocks.</description> 19954 <value>0</value> 19955 </enumeratedValue> 19956 </enumeratedValues> 19957 </field> 19958 <field> 19959 <name>SSACT</name> 19960 <description>Slaves Select Activate Timing.</description> 19961 <bitOffset>16</bitOffset> 19962 <bitWidth>2</bitWidth> 19963 <enumeratedValues> 19964 <enumeratedValue> 19965 <name>0_CLKS</name> 19966 <description>0 sytem clocks.</description> 19967 <value>0</value> 19968 </enumeratedValue> 19969 <enumeratedValue> 19970 <name>2_CLKS</name> 19971 <description>2 sytem clocks.</description> 19972 <value>1</value> 19973 </enumeratedValue> 19974 <enumeratedValue> 19975 <name>4_CLKS</name> 19976 <description>4 sytem clocks.</description> 19977 <value>2</value> 19978 </enumeratedValue> 19979 <enumeratedValue> 19980 <name>8_CLKS</name> 19981 <description>8 sytem clocks.</description> 19982 <value>3</value> 19983 </enumeratedValue> 19984 </enumeratedValues> 19985 </field> 19986 <field> 19987 <name>SSIACT</name> 19988 <description>Slaves Select Inactive Timing.</description> 19989 <bitOffset>18</bitOffset> 19990 <bitWidth>2</bitWidth> 19991 <enumeratedValues> 19992 <enumeratedValue> 19993 <name>4_CLKS</name> 19994 <description>4 sytem clocks.</description> 19995 <value>0</value> 19996 </enumeratedValue> 19997 <enumeratedValue> 19998 <name>6_CLKS</name> 19999 <description>6 sytem clocks.</description> 20000 <value>1</value> 20001 </enumeratedValue> 20002 <enumeratedValue> 20003 <name>8_CLKS</name> 20004 <description>8 sytem clocks.</description> 20005 <value>2</value> 20006 </enumeratedValue> 20007 <enumeratedValue> 20008 <name>12_CLKS</name> 20009 <description>12 sytem clocks.</description> 20010 <value>3</value> 20011 </enumeratedValue> 20012 </enumeratedValues> 20013 </field> 20014 <field> 20015 <name>IOSMPL</name> 20016 <description>Sample Delay</description> 20017 <bitOffset>20</bitOffset> 20018 <bitWidth>4</bitWidth> 20019 </field> 20020 </fields> 20021 </register> 20022 <register> 20023 <name>SS_POL</name> 20024 <description>SPIX Controller Slave Select Polarity Register.</description> 20025 <addressOffset>0x04</addressOffset> 20026 <fields> 20027 <field> 20028 <name>SSPOL_0</name> 20029 <description>Slave Select Polarity.</description> 20030 <bitOffset>0</bitOffset> 20031 <bitWidth>1</bitWidth> 20032 <enumeratedValues> 20033 <enumeratedValue> 20034 <name>lo</name> 20035 <description>Active Low.</description> 20036 <value>0</value> 20037 </enumeratedValue> 20038 <enumeratedValue> 20039 <name>hi</name> 20040 <description>Active High.</description> 20041 <value>1</value> 20042 </enumeratedValue> 20043 </enumeratedValues> 20044 </field> 20045 </fields> 20046 </register> 20047 <register> 20048 <name>GEN_CTRL</name> 20049 <description>SPIX Controller General Controller Register.</description> 20050 <addressOffset>0x08</addressOffset> 20051 <fields> 20052 <field> 20053 <name>ENABLE</name> 20054 <description>SPI Master enable.</description> 20055 <bitOffset>0</bitOffset> 20056 <bitWidth>1</bitWidth> 20057 <enumeratedValues> 20058 <enumeratedValue> 20059 <name>dis</name> 20060 <description>Disable SPI Master, putting a reset state.</description> 20061 <value>0</value> 20062 </enumeratedValue> 20063 <enumeratedValue> 20064 <name>en</name> 20065 <description>Enable SPI Master for processing transactions.</description> 20066 <value>1</value> 20067 </enumeratedValue> 20068 </enumeratedValues> 20069 </field> 20070 <field> 20071 <name>TX_FIFO_EN</name> 20072 <description>Transaction FIFO Enable.</description> 20073 <bitOffset>1</bitOffset> 20074 <bitWidth>1</bitWidth> 20075 <enumeratedValues> 20076 <enumeratedValue> 20077 <name>dis_txfifo</name> 20078 <description>Disable Transaction FIFO.</description> 20079 <value>0</value> 20080 </enumeratedValue> 20081 <enumeratedValue> 20082 <name>en_txfifo</name> 20083 <description>Enable Transaction FIFO.</description> 20084 <value>1</value> 20085 </enumeratedValue> 20086 </enumeratedValues> 20087 </field> 20088 <field> 20089 <name>RX_FIFO_EN</name> 20090 <description>Result FIFO Enable.</description> 20091 <bitOffset>2</bitOffset> 20092 <bitWidth>1</bitWidth> 20093 <enumeratedValues> 20094 <enumeratedValue> 20095 <name>dis_rxfifo</name> 20096 <description>Disable Result FIFO.</description> 20097 <value>0</value> 20098 </enumeratedValue> 20099 <enumeratedValue> 20100 <name>en_rxfifo</name> 20101 <description>Enable Result FIFO.</description> 20102 <value>1</value> 20103 </enumeratedValue> 20104 </enumeratedValues> 20105 </field> 20106 <field> 20107 <name>BBMODE</name> 20108 <description>Bit-Bang Mode.</description> 20109 <bitOffset>3</bitOffset> 20110 <bitWidth>1</bitWidth> 20111 <enumeratedValues> 20112 <enumeratedValue> 20113 <name>dis</name> 20114 <description>Disable Bit-Bang Mode.</description> 20115 <value>0</value> 20116 </enumeratedValue> 20117 <enumeratedValue> 20118 <name>en</name> 20119 <description>Enable Bit-Bang Mode.</description> 20120 <value>1</value> 20121 </enumeratedValue> 20122 </enumeratedValues> 20123 </field> 20124 <field> 20125 <name>SSDR</name> 20126 <description>This bits reflects the state of the currently selected slave select.</description> 20127 <bitOffset>4</bitOffset> 20128 <bitWidth>1</bitWidth> 20129 <enumeratedValues> 20130 <enumeratedValue> 20131 <name>output0</name> 20132 <description>Selected Slave select output = 0.</description> 20133 <value>0</value> 20134 </enumeratedValue> 20135 <enumeratedValue> 20136 <name>output1</name> 20137 <description>Selected Slave select output = 1.</description> 20138 <value>1</value> 20139 </enumeratedValue> 20140 </enumeratedValues> 20141 </field> 20142 <field> 20143 <name>SCLK_DR</name> 20144 <description>SSCLK Drive and State.</description> 20145 <bitOffset>6</bitOffset> 20146 <bitWidth>1</bitWidth> 20147 <enumeratedValues> 20148 <enumeratedValue> 20149 <name>SCLK_0</name> 20150 <description>SCLK is 0.</description> 20151 <value>0</value> 20152 </enumeratedValue> 20153 <enumeratedValue> 20154 <name>SCLK_1</name> 20155 <description>SCLK is 1.</description> 20156 <value>1</value> 20157 </enumeratedValue> 20158 </enumeratedValues> 20159 </field> 20160 <field> 20161 <name>SDIO_DATA_IN</name> 20162 <description>SDIO Input Data Value.</description> 20163 <bitOffset>8</bitOffset> 20164 <bitWidth>4</bitWidth> 20165 <enumeratedValues> 20166 <enumeratedValue> 20167 <name>SDIO0</name> 20168 <description>SDIO[0]</description> 20169 <value>0</value> 20170 </enumeratedValue> 20171 <enumeratedValue> 20172 <name>SDIO1</name> 20173 <description>SDIO[1]</description> 20174 <value>1</value> 20175 </enumeratedValue> 20176 <enumeratedValue> 20177 <name>SDIO2</name> 20178 <description>SDIO[2]</description> 20179 <value>2</value> 20180 </enumeratedValue> 20181 <enumeratedValue> 20182 <name>SDIO3</name> 20183 <description>SDIO[3]</description> 20184 <value>3</value> 20185 </enumeratedValue> 20186 </enumeratedValues> 20187 </field> 20188 <field> 20189 <name>BB_DATA</name> 20190 <description>No description available.</description> 20191 <bitOffset>12</bitOffset> 20192 <bitWidth>4</bitWidth> 20193 <enumeratedValues> 20194 <enumeratedValue> 20195 <name>SDIO0</name> 20196 <description>SDIO[0]</description> 20197 <value>0</value> 20198 </enumeratedValue> 20199 <enumeratedValue> 20200 <name>SDIO1</name> 20201 <description>SDIO[1]</description> 20202 <value>1</value> 20203 </enumeratedValue> 20204 <enumeratedValue> 20205 <name>SDIO2</name> 20206 <description>SDIO[2]</description> 20207 <value>2</value> 20208 </enumeratedValue> 20209 <enumeratedValue> 20210 <name>SDIO3</name> 20211 <description>SDIO[3]</description> 20212 <value>3</value> 20213 </enumeratedValue> 20214 </enumeratedValues> 20215 </field> 20216 <field> 20217 <name>BB_DATA_OUT_EN</name> 20218 <description>Bit Bang SDIO Output Enable.</description> 20219 <bitOffset>16</bitOffset> 20220 <bitWidth>4</bitWidth> 20221 <enumeratedValues> 20222 <enumeratedValue> 20223 <name>SDIO0</name> 20224 <description>SDIO[0]</description> 20225 <value>0</value> 20226 </enumeratedValue> 20227 <enumeratedValue> 20228 <name>SDIO1</name> 20229 <description>SDIO[1]</description> 20230 <value>1</value> 20231 </enumeratedValue> 20232 <enumeratedValue> 20233 <name>SDIO2</name> 20234 <description>SDIO[2]</description> 20235 <value>2</value> 20236 </enumeratedValue> 20237 <enumeratedValue> 20238 <name>SDIO3</name> 20239 <description>SDIO[3]</description> 20240 <value>3</value> 20241 </enumeratedValue> 20242 </enumeratedValues> 20243 </field> 20244 <field> 20245 <name>SIMPLE</name> 20246 <description>Simple Mode Enable.</description> 20247 <bitOffset>20</bitOffset> 20248 <bitWidth>1</bitWidth> 20249 </field> 20250 <field> 20251 <name>SIMPLE_RX</name> 20252 <description>Simple Receive Enable.</description> 20253 <bitOffset>21</bitOffset> 20254 <bitWidth>1</bitWidth> 20255 </field> 20256 <field> 20257 <name>SIMPLE_SS</name> 20258 <description>Simple Mode Slave Select.</description> 20259 <bitOffset>22</bitOffset> 20260 <bitWidth>1</bitWidth> 20261 </field> 20262 <field> 20263 <name>SCLK_FB</name> 20264 <description>Enable SCLK Feedback Mode.</description> 20265 <bitOffset>24</bitOffset> 20266 <bitWidth>1</bitWidth> 20267 <enumeratedValues> 20268 <enumeratedValue> 20269 <name>dis</name> 20270 <value>0</value> 20271 </enumeratedValue> 20272 <enumeratedValue> 20273 <name>en</name> 20274 <value>1</value> 20275 </enumeratedValue> 20276 </enumeratedValues> 20277 </field> 20278 <field> 20279 <name>SCLK_FB_INVERT</name> 20280 <description>SCK Invert.</description> 20281 <bitOffset>25</bitOffset> 20282 <bitWidth>1</bitWidth> 20283 </field> 20284 </fields> 20285 </register> 20286 <register> 20287 <name>FIFO_CTRL</name> 20288 <description>SPIX Controller FIFO Control and Status Register.</description> 20289 <addressOffset>0x0C</addressOffset> 20290 <fields> 20291 <field> 20292 <name>TX_FIFO_AE_LVL</name> 20293 <description>Transaction FIFO Almost Empty Level.</description> 20294 <bitOffset>0</bitOffset> 20295 <bitWidth>4</bitWidth> 20296 </field> 20297 <field> 20298 <name>TX_FIFO_CNT</name> 20299 <description>Transaction FIFO Used.</description> 20300 <bitOffset>8</bitOffset> 20301 <bitWidth>5</bitWidth> 20302 </field> 20303 <field> 20304 <name>RX_FIFO_AF_LVL</name> 20305 <description>Results FIFO Almost Full Level.</description> 20306 <bitOffset>16</bitOffset> 20307 <bitWidth>5</bitWidth> 20308 </field> 20309 <field> 20310 <name>RX_FIFO_CNT</name> 20311 <description>Result FIFO Used.</description> 20312 <bitOffset>24</bitOffset> 20313 <bitWidth>6</bitWidth> 20314 </field> 20315 </fields> 20316 </register> 20317 <register> 20318 <name>SP_CTRL</name> 20319 <description>SPIX Controller Special Control Register.</description> 20320 <addressOffset>0x10</addressOffset> 20321 <fields> 20322 <field> 20323 <name>SAMPL</name> 20324 <description>Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must 20325 only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the 20326 next slave select assertion.</description> 20327 <bitOffset>0</bitOffset> 20328 <bitWidth>1</bitWidth> 20329 </field> 20330 <field> 20331 <name>SDIO_OUT</name> 20332 <description>SDIO Output Value Sample Mode</description> 20333 <bitOffset>4</bitOffset> 20334 <bitWidth>4</bitWidth> 20335 </field> 20336 <field> 20337 <name>SDIO_OUT_EN</name> 20338 <description>SDIO Output Enable Sample Mode</description> 20339 <bitOffset>8</bitOffset> 20340 <bitWidth>4</bitWidth> 20341 </field> 20342 <field> 20343 <name>SCLKINH3</name> 20344 <description>SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.</description> 20345 <bitOffset>16</bitOffset> 20346 <bitWidth>1</bitWidth> 20347 <enumeratedValues> 20348 <enumeratedValue> 20349 <name>EN</name> 20350 <description>Allow trailing SCLK low pulse prior to Slave Select de-assertion.</description> 20351 <value>0</value> 20352 </enumeratedValue> 20353 <enumeratedValue> 20354 <name>DIS</name> 20355 <description>Inhibit trailing SCLK low pulse prior to Slave Select de-assertion.</description> 20356 <value>1</value> 20357 </enumeratedValue> 20358 </enumeratedValues> 20359 </field> 20360 </fields> 20361 </register> 20362 <register> 20363 <name>INT_FL</name> 20364 <description>SPIX Controller Interrupt Status Register.</description> 20365 <addressOffset>0x14</addressOffset> 20366 <fields> 20367 <field> 20368 <name>TX_STALLED</name> 20369 <description>Transaction Stalled Interrupt Flag.</description> 20370 <bitOffset>0</bitOffset> 20371 <bitWidth>1</bitWidth> 20372 <enumeratedValues> 20373 <enumeratedValue> 20374 <name>CLR</name> 20375 <description>Normal FIFO Transaction.</description> 20376 <value>0</value> 20377 </enumeratedValue> 20378 <enumeratedValue> 20379 <name>SET</name> 20380 <description>Stalled FIFO Transaction.</description> 20381 <value>1</value> 20382 </enumeratedValue> 20383 </enumeratedValues> 20384 </field> 20385 <field> 20386 <name>RX_STALLED</name> 20387 <description>Results Stalled Interrupt Flag.</description> 20388 <bitOffset>1</bitOffset> 20389 <bitWidth>1</bitWidth> 20390 <enumeratedValues> 20391 <enumeratedValue> 20392 <name>CLR</name> 20393 <description>Normal FIFO Operation.</description> 20394 <value>0</value> 20395 </enumeratedValue> 20396 <enumeratedValue> 20397 <name>SET</name> 20398 <description>Stalled FIFO.</description> 20399 <value>1</value> 20400 </enumeratedValue> 20401 </enumeratedValues> 20402 </field> 20403 <field> 20404 <name>TX_READY</name> 20405 <description>Transaction Ready Interrupt Status.</description> 20406 <bitOffset>2</bitOffset> 20407 <bitWidth>1</bitWidth> 20408 <enumeratedValues> 20409 <enumeratedValue> 20410 <name>CLR</name> 20411 <description>FIFO Transaction not ready.</description> 20412 <value>0</value> 20413 </enumeratedValue> 20414 <enumeratedValue> 20415 <name>SET</name> 20416 <description>FIFO Transaction ready.</description> 20417 <value>1</value> 20418 </enumeratedValue> 20419 </enumeratedValues> 20420 </field> 20421 <field> 20422 <name>RX_DONE</name> 20423 <description>Results Done Interrupt Status.</description> 20424 <bitOffset>3</bitOffset> 20425 <bitWidth>1</bitWidth> 20426 <enumeratedValues> 20427 <enumeratedValue> 20428 <name>CLR</name> 20429 <description>Results FIFO ready.</description> 20430 <value>0</value> 20431 </enumeratedValue> 20432 <enumeratedValue> 20433 <name>SET</name> 20434 <description>Results FIFO Not ready.</description> 20435 <value>1</value> 20436 </enumeratedValue> 20437 </enumeratedValues> 20438 </field> 20439 <field> 20440 <name>TX_FIFO_AE</name> 20441 <description>Transaction FIFO Almost Empty Flag.</description> 20442 <bitOffset>4</bitOffset> 20443 <bitWidth>1</bitWidth> 20444 <enumeratedValues> 20445 <enumeratedValue> 20446 <name>CLR</name> 20447 <description>Transaction FIFO not Almost Empty.</description> 20448 <value>0</value> 20449 </enumeratedValue> 20450 <enumeratedValue> 20451 <name>SET</name> 20452 <description>Transaction FIFO Almost Empty.</description> 20453 <value>1</value> 20454 </enumeratedValue> 20455 </enumeratedValues> 20456 </field> 20457 <field> 20458 <name>RX_FIFO_AF</name> 20459 <description>Results FIFO Almost Full Flag.</description> 20460 <bitOffset>5</bitOffset> 20461 <bitWidth>1</bitWidth> 20462 <enumeratedValues> 20463 <enumeratedValue> 20464 <name>CLR</name> 20465 <description>Results FIFO level below the Almost Full level.</description> 20466 <value>0</value> 20467 </enumeratedValue> 20468 <enumeratedValue> 20469 <name>SET</name> 20470 <description>Results FIFO level at Almost Full level.</description> 20471 <value>1</value> 20472 </enumeratedValue> 20473 </enumeratedValues> 20474 </field> 20475 </fields> 20476 </register> 20477 <register> 20478 <name>INT_EN</name> 20479 <description>SPIX Controller Interrupt Enable Register.</description> 20480 <addressOffset>0x18</addressOffset> 20481 <fields> 20482 <field> 20483 <name>TX_STALLED</name> 20484 <description>Transaction Stalled Interrupt Enable.</description> 20485 <bitOffset>0</bitOffset> 20486 <bitWidth>1</bitWidth> 20487 <enumeratedValues> 20488 <enumeratedValue> 20489 <name>en</name> 20490 <description>Disable Transaction Stalled Interrupt.</description> 20491 <value>0</value> 20492 </enumeratedValue> 20493 <enumeratedValue> 20494 <name>dis</name> 20495 <description>Enable Transaction Stalled Interrupt.</description> 20496 <value>1</value> 20497 </enumeratedValue> 20498 </enumeratedValues> 20499 </field> 20500 <field> 20501 <name>RX_STALLED</name> 20502 <description>Results Stalled Interrupt Enable.</description> 20503 <bitOffset>1</bitOffset> 20504 <bitWidth>1</bitWidth> 20505 <enumeratedValues> 20506 <enumeratedValue> 20507 <name>en</name> 20508 <description>Disable Results Stalled Interrupt.</description> 20509 <value>0</value> 20510 </enumeratedValue> 20511 <enumeratedValue> 20512 <name>dis</name> 20513 <description>Enable Results Stalled Interrupt.</description> 20514 <value>1</value> 20515 </enumeratedValue> 20516 </enumeratedValues> 20517 </field> 20518 <field> 20519 <name>TX_READY</name> 20520 <description>Transaction Ready Interrupt Enable.</description> 20521 <bitOffset>2</bitOffset> 20522 <bitWidth>1</bitWidth> 20523 <enumeratedValues> 20524 <enumeratedValue> 20525 <name>en</name> 20526 <description>Disable FIFO Transaction Ready Interrupt.</description> 20527 <value>0</value> 20528 </enumeratedValue> 20529 <enumeratedValue> 20530 <name>dis</name> 20531 <description>Enable FIFO Transaction Ready Interrupt.</description> 20532 <value>1</value> 20533 </enumeratedValue> 20534 </enumeratedValues> 20535 </field> 20536 <field> 20537 <name>RX_DONE</name> 20538 <description>Results Done Interrupt Enable.</description> 20539 <bitOffset>3</bitOffset> 20540 <bitWidth>1</bitWidth> 20541 <enumeratedValues> 20542 <enumeratedValue> 20543 <name>en</name> 20544 <description>Disable Results Done Interrupt.</description> 20545 <value>0</value> 20546 </enumeratedValue> 20547 <enumeratedValue> 20548 <name>dis</name> 20549 <description>Enable Results Done Interrupt.</description> 20550 <value>1</value> 20551 </enumeratedValue> 20552 </enumeratedValues> 20553 </field> 20554 <field> 20555 <name>TX_FIFO_AE</name> 20556 <description>Transaction FIFO Almost Empty Interrupt Enable.</description> 20557 <bitOffset>4</bitOffset> 20558 <bitWidth>1</bitWidth> 20559 <enumeratedValues> 20560 <enumeratedValue> 20561 <name>en</name> 20562 <description>Disable Transaction FIFO Almost Empty Interrupt.</description> 20563 <value>0</value> 20564 </enumeratedValue> 20565 <enumeratedValue> 20566 <name>dis</name> 20567 <description>Enable Transaction FIFO Almost Empty Interrupt.</description> 20568 <value>1</value> 20569 </enumeratedValue> 20570 </enumeratedValues> 20571 </field> 20572 <field> 20573 <name>RX_FIFO_AF</name> 20574 <description>Results FIFO Almost Full Interrupt Enable.</description> 20575 <bitOffset>5</bitOffset> 20576 <bitWidth>1</bitWidth> 20577 <enumeratedValues> 20578 <enumeratedValue> 20579 <name>en</name> 20580 <description>Disable Results FIFO Almost Full Interrupt.</description> 20581 <value>0</value> 20582 </enumeratedValue> 20583 <enumeratedValue> 20584 <name>dis</name> 20585 <description>Enable Results FIFO Almost Full Interrupt.</description> 20586 <value>1</value> 20587 </enumeratedValue> 20588 </enumeratedValues> 20589 </field> 20590 </fields> 20591 </register> 20592 </registers> 20593 </peripheral> 20594<!--SPIXFC SPI XiP Flash Configuration Controller--> 20595 <peripheral> 20596 <name>SPIXFC_FIFO</name> 20597 <description>SPI XiP Master Controller FIFO.</description> 20598 <baseAddress>0x400BC000</baseAddress> 20599 <addressBlock> 20600 <offset>0</offset> 20601 <size>0x1000</size> 20602 <usage>registers</usage> 20603 </addressBlock> 20604 <registers> 20605 <register> 20606 <name>TX_8</name> 20607 <description>SPI TX FIFO 8-Bit Write</description> 20608 <addressOffset>0x00</addressOffset> 20609 <size>8</size> 20610 <dataType>uint8_t</dataType> 20611 </register> 20612 <register> 20613 <name>TX_16</name> 20614 <description>SPI TX FIFO 16-Bit Write</description> 20615 <alternateRegister>TX_8</alternateRegister> 20616 <addressOffset>0x00</addressOffset> 20617 <size>16</size> 20618 <dataType>uint16_t</dataType> 20619 </register> 20620 <register> 20621 <name>TX_32</name> 20622 <description>SPI TX FIFO 32-Bit Write</description> 20623 <alternateRegister>TX_8</alternateRegister> 20624 <addressOffset>0x00</addressOffset> 20625 <size>32</size> 20626 <dataType>uint32_t</dataType> 20627 </register> 20628 <register> 20629 <name>RX_8</name> 20630 <description>SPI RX FIFO 8-Bit Access</description> 20631 <addressOffset>0x04</addressOffset> 20632 <size>8</size> 20633 <dataType>uint8_t</dataType> 20634 </register> 20635 <register> 20636 <name>RX_16</name> 20637 <description>SPI RX FIFO 16-Bit Access</description> 20638 <alternateRegister>RX_8</alternateRegister> 20639 <addressOffset>0x04</addressOffset> 20640 <size>16</size> 20641 <dataType>uint16_t</dataType> 20642 </register> 20643 <register> 20644 <name>RX_32</name> 20645 <description>SPI RX FIFO 32-Bit Access</description> 20646 <alternateRegister>RX_8</alternateRegister> 20647 <addressOffset>0x04</addressOffset> 20648 <size>32</size> 20649 <dataType>uint32_t</dataType> 20650 </register> 20651 </registers> 20652 </peripheral> 20653<!--SPIXFC_FIFO SPI XiP Master Controller FIFO.--> 20654 <peripheral> 20655 <name>SPIXFM</name> 20656 <description>SPIXF Master</description> 20657 <baseAddress>0x40026000</baseAddress> 20658 <addressBlock> 20659 <offset>0x00</offset> 20660 <size>0x1000</size> 20661 <usage>registers</usage> 20662 </addressBlock> 20663 <registers> 20664 <register> 20665 <name>CFG</name> 20666 <description>SPIX Configuration Register.</description> 20667 <addressOffset>0x00</addressOffset> 20668 <fields> 20669 <field> 20670 <name>MODE</name> 20671 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 20672 <bitOffset>0</bitOffset> 20673 <bitWidth>2</bitWidth> 20674 <enumeratedValues> 20675 <enumeratedValue> 20676 <name>SCLK_HI_SAMPLE_RISING</name> 20677 <description>Description not available.</description> 20678 <value>0</value> 20679 </enumeratedValue> 20680 <enumeratedValue> 20681 <name>SCLK_LO_SAMPLE_FAILLING</name> 20682 <description>Description not available.</description> 20683 <value>3</value> 20684 </enumeratedValue> 20685 </enumeratedValues> 20686 </field> 20687 <field> 20688 <name>SSPOL</name> 20689 <description>Slave Select Polarity.</description> 20690 <bitOffset>2</bitOffset> 20691 <bitWidth>1</bitWidth> 20692 <enumeratedValues> 20693 <enumeratedValue> 20694 <name>ACTIVE_HIGH</name> 20695 <description>Slave Select is Active High.</description> 20696 <value>0</value> 20697 </enumeratedValue> 20698 <enumeratedValue> 20699 <name>ACTIVE_LOW</name> 20700 <description>Slave Select is Active Low.</description> 20701 <value>1</value> 20702 </enumeratedValue> 20703 </enumeratedValues> 20704 </field> 20705 <field> 20706 <name>SSEL</name> 20707 <description>Slave Select. Only valid value is zero.</description> 20708 <bitOffset>4</bitOffset> 20709 <bitWidth>3</bitWidth> 20710 </field> 20711 <field> 20712 <name>LO_CLK</name> 20713 <description>Number of system clocks that SCLK will be low when SCLK pulses are generated.</description> 20714 <bitOffset>8</bitOffset> 20715 <bitWidth>4</bitWidth> 20716 </field> 20717 <field> 20718 <name>HI_CLK</name> 20719 <description>Number of system clocks that SCLK will be high when SCLK pulses are generated.</description> 20720 <bitOffset>12</bitOffset> 20721 <bitWidth>4</bitWidth> 20722 </field> 20723 <field> 20724 <name>SSACT</name> 20725 <description>Slave Select Active Timing.</description> 20726 <bitOffset>16</bitOffset> 20727 <bitWidth>2</bitWidth> 20728 <enumeratedValues> 20729 <enumeratedValue> 20730 <name>off</name> 20731 <description>0 system clocks.</description> 20732 <value>0</value> 20733 </enumeratedValue> 20734 <enumeratedValue> 20735 <name>for_2_mod_clk</name> 20736 <description>2 System clocks.</description> 20737 <value>1</value> 20738 </enumeratedValue> 20739 <enumeratedValue> 20740 <name>for_4_mod_clk</name> 20741 <description>4 System clocks.</description> 20742 <value>2</value> 20743 </enumeratedValue> 20744 <enumeratedValue> 20745 <name>for_8_mod_clk</name> 20746 <description>8 System clocks.</description> 20747 <value>3</value> 20748 </enumeratedValue> 20749 </enumeratedValues> 20750 </field> 20751 <field> 20752 <name>SSIACT</name> 20753 <description>Slave Select Inactive Timing.</description> 20754 <bitOffset>18</bitOffset> 20755 <bitWidth>2</bitWidth> 20756 <enumeratedValues> 20757 <enumeratedValue> 20758 <name>for_1_mod_clk</name> 20759 <description>1 system clocks.</description> 20760 <value>0</value> 20761 </enumeratedValue> 20762 <enumeratedValue> 20763 <name>for_3_mod_clk</name> 20764 <description>3 System clocks.</description> 20765 <value>1</value> 20766 </enumeratedValue> 20767 <enumeratedValue> 20768 <name>for_5_mod_clk</name> 20769 <description>5 System clocks.</description> 20770 <value>2</value> 20771 </enumeratedValue> 20772 <enumeratedValue> 20773 <name>for_9_mod_clk</name> 20774 <description>9 System clocks.</description> 20775 <value>3</value> 20776 </enumeratedValue> 20777 </enumeratedValues> 20778 </field> 20779 </fields> 20780 </register> 20781 <register> 20782 <name>FETCH_CTRL</name> 20783 <description>SPIX Fetch Control Register.</description> 20784 <addressOffset>0x04</addressOffset> 20785 <fields> 20786 <field> 20787 <name>CMDVAL</name> 20788 <description>Command Value sent to target to initiate fetching from SPI flash.</description> 20789 <bitOffset>0</bitOffset> 20790 <bitWidth>8</bitWidth> 20791 </field> 20792 <field> 20793 <name>CMD_WIDTH</name> 20794 <description>Command Width. Number of data I/O used to send commands.</description> 20795 <bitOffset>8</bitOffset> 20796 <bitWidth>2</bitWidth> 20797 <enumeratedValues> 20798 <enumeratedValue> 20799 <name>Single</name> 20800 <description>Single SDIO.</description> 20801 <value>0</value> 20802 </enumeratedValue> 20803 <enumeratedValue> 20804 <name>Dual_IO</name> 20805 <description>Dual SDIO.</description> 20806 <value>1</value> 20807 </enumeratedValue> 20808 <enumeratedValue> 20809 <name>Quad_IO</name> 20810 <description>Quad SDIO.</description> 20811 <value>2</value> 20812 </enumeratedValue> 20813 <enumeratedValue> 20814 <name>Invalid</name> 20815 <description>Invalid.</description> 20816 <value>3</value> 20817 </enumeratedValue> 20818 </enumeratedValues> 20819 </field> 20820 <field> 20821 <name>ADDR_WIDTH</name> 20822 <description>Address Width. Number of data I/O used to send address, and mode/dummy clocks.</description> 20823 <bitOffset>10</bitOffset> 20824 <bitWidth>2</bitWidth> 20825 <enumeratedValues> 20826 <enumeratedValue> 20827 <name>Single</name> 20828 <description>Single SDIO.</description> 20829 <value>0</value> 20830 </enumeratedValue> 20831 <enumeratedValue> 20832 <name>Dual_IO</name> 20833 <description>Dual SDIO.</description> 20834 <value>1</value> 20835 </enumeratedValue> 20836 <enumeratedValue> 20837 <name>Quad_IO</name> 20838 <description>Quad SDIO.</description> 20839 <value>2</value> 20840 </enumeratedValue> 20841 <enumeratedValue> 20842 <name>Invalid</name> 20843 <description>Invalid.</description> 20844 <value>3</value> 20845 </enumeratedValue> 20846 </enumeratedValues> 20847 </field> 20848 <field> 20849 <name>DATA_WIDTH</name> 20850 <description>Data Width. Number of data I/O used to receive data.</description> 20851 <bitOffset>12</bitOffset> 20852 <bitWidth>2</bitWidth> 20853 <enumeratedValues> 20854 <enumeratedValue> 20855 <name>Single</name> 20856 <description>Single SDIO.</description> 20857 <value>0</value> 20858 </enumeratedValue> 20859 <enumeratedValue> 20860 <name>Dual_IO</name> 20861 <description>Dual SDIO.</description> 20862 <value>1</value> 20863 </enumeratedValue> 20864 <enumeratedValue> 20865 <name>Quad_IO</name> 20866 <description>Quad SDIO.</description> 20867 <value>2</value> 20868 </enumeratedValue> 20869 <enumeratedValue> 20870 <name>Invalid</name> 20871 <description>Invalid.</description> 20872 <value>3</value> 20873 </enumeratedValue> 20874 </enumeratedValues> 20875 </field> 20876 <field> 20877 <name>FOUR_BYTE_ADDR</name> 20878 <description>Four Byte Address Mode. Enables 4-byte Flash Address Mode.</description> 20879 <bitOffset>16</bitOffset> 20880 <bitWidth>1</bitWidth> 20881 <enumeratedValues> 20882 <enumeratedValue> 20883 <name>3</name> 20884 <description>3 Byte Address Mode.</description> 20885 <value>0</value> 20886 </enumeratedValue> 20887 <enumeratedValue> 20888 <name>4</name> 20889 <description>4 Byte Address Mode.</description> 20890 <value>1</value> 20891 </enumeratedValue> 20892 </enumeratedValues> 20893 </field> 20894 </fields> 20895 </register> 20896 <register> 20897 <name>MODE_CTRL</name> 20898 <description>SPIX Mode Control Register.</description> 20899 <addressOffset>0x08</addressOffset> 20900 <fields> 20901 <field> 20902 <name>MDCLK</name> 20903 <description>Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.</description> 20904 <bitOffset>0</bitOffset> 20905 <bitWidth>4</bitWidth> 20906 </field> 20907 <field> 20908 <name>NO_CMD</name> 20909 <description>No Command Mode.</description> 20910 <bitOffset>8</bitOffset> 20911 <bitWidth>1</bitWidth> 20912 <enumeratedValues> 20913 <enumeratedValue> 20914 <name>always</name> 20915 <description>Send read command every time SPI transaction is initiated.</description> 20916 <value>0</value> 20917 </enumeratedValue> 20918 <enumeratedValue> 20919 <name>once</name> 20920 <description>Send read command only once. NO read command in subsequent SPI transactions.</description> 20921 <value>1</value> 20922 </enumeratedValue> 20923 </enumeratedValues> 20924 </field> 20925 <field> 20926 <name>MODE_SEND</name> 20927 <description>Mode Send.</description> 20928 <bitOffset>9</bitOffset> 20929 <bitWidth>1</bitWidth> 20930 </field> 20931 </fields> 20932 </register> 20933 <register> 20934 <name>MODE_DATA</name> 20935 <description>SPIX Mode Data Register.</description> 20936 <addressOffset>0x0C</addressOffset> 20937 <fields> 20938 <field> 20939 <name>DATA</name> 20940 <description>Mode Data. Specifies the data to send with the Dummy/Mode clocks.</description> 20941 <bitOffset>0</bitOffset> 20942 <bitWidth>16</bitWidth> 20943 </field> 20944 <field> 20945 <name>OUT_EN</name> 20946 <description>Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.</description> 20947 <bitOffset>16</bitOffset> 20948 <bitWidth>16</bitWidth> 20949 </field> 20950 </fields> 20951 </register> 20952 <register> 20953 <name>FB_CTRL</name> 20954 <description>SPIX Feedback Control Register.</description> 20955 <addressOffset>0x10</addressOffset> 20956 <fields> 20957 <field> 20958 <name>FB_EN</name> 20959 <description>Enable SCLK feedback mode.</description> 20960 <bitOffset>0</bitOffset> 20961 <bitWidth>1</bitWidth> 20962 <enumeratedValues> 20963 <enumeratedValue> 20964 <name>dis</name> 20965 <description>Disable SCLK feedback mode.</description> 20966 <value>0</value> 20967 </enumeratedValue> 20968 <enumeratedValue> 20969 <name>en</name> 20970 <description>Enable SCLK feedback mode.</description> 20971 <value>1</value> 20972 </enumeratedValue> 20973 </enumeratedValues> 20974 </field> 20975 <field> 20976 <name>INVERT_EN</name> 20977 <description>Invert SCLK in feedback mode.</description> 20978 <bitOffset>1</bitOffset> 20979 <bitWidth>1</bitWidth> 20980 <enumeratedValues> 20981 <enumeratedValue> 20982 <name>dis</name> 20983 <description>Disable Invert SCLK feedback mode.</description> 20984 <value>0</value> 20985 </enumeratedValue> 20986 <enumeratedValue> 20987 <name>en</name> 20988 <description>Enable Invert SCLK feedback mode.</description> 20989 <value>1</value> 20990 </enumeratedValue> 20991 </enumeratedValues> 20992 </field> 20993 </fields> 20994 </register> 20995 <register> 20996 <name>IO_CTRL</name> 20997 <description>SPIX IO Control Register.</description> 20998 <addressOffset>0x1C</addressOffset> 20999 <fields> 21000 <field> 21001 <name>SCLK_DS</name> 21002 <description>SCLK drive Strength. This bit controls the drive strength on the SCLK pin.</description> 21003 <bitOffset>0</bitOffset> 21004 <bitWidth>1</bitWidth> 21005 <enumeratedValues> 21006 <enumeratedValue> 21007 <name>Low</name> 21008 <description>Low drive strength.</description> 21009 <value>0</value> 21010 </enumeratedValue> 21011 <enumeratedValue> 21012 <name>High</name> 21013 <description>High drive strength.</description> 21014 <value>1</value> 21015 </enumeratedValue> 21016 </enumeratedValues> 21017 </field> 21018 <field> 21019 <name>SS_DS</name> 21020 <description>Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.</description> 21021 <bitOffset>1</bitOffset> 21022 <bitWidth>1</bitWidth> 21023 <enumeratedValues> 21024 <enumeratedValue> 21025 <name>Low</name> 21026 <description>Low drive strength.</description> 21027 <value>0</value> 21028 </enumeratedValue> 21029 <enumeratedValue> 21030 <name>High</name> 21031 <description>High drive strength.</description> 21032 <value>1</value> 21033 </enumeratedValue> 21034 </enumeratedValues> 21035 </field> 21036 <field> 21037 <name>SDIO_DS</name> 21038 <description>SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.</description> 21039 <bitOffset>2</bitOffset> 21040 <bitWidth>1</bitWidth> 21041 <enumeratedValues> 21042 <enumeratedValue> 21043 <name>Low</name> 21044 <description>Low drive strength.</description> 21045 <value>0</value> 21046 </enumeratedValue> 21047 <enumeratedValue> 21048 <name>High</name> 21049 <description>High drive strength.</description> 21050 <value>1</value> 21051 </enumeratedValue> 21052 </enumeratedValues> 21053 </field> 21054 <field> 21055 <name>PU_PD_CTRL</name> 21056 <description>IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.</description> 21057 <bitOffset>3</bitOffset> 21058 <bitWidth>2</bitWidth> 21059 <enumeratedValues> 21060 <enumeratedValue> 21061 <name>tri_state</name> 21062 <description>Tristate.</description> 21063 <value>0</value> 21064 </enumeratedValue> 21065 <enumeratedValue> 21066 <name>Pull_Up</name> 21067 <description>Pull-Up.</description> 21068 <value>1</value> 21069 </enumeratedValue> 21070 <enumeratedValue> 21071 <name>Pull_down</name> 21072 <description>Pull-Down.</description> 21073 <value>2</value> 21074 </enumeratedValue> 21075 </enumeratedValues> 21076 </field> 21077 </fields> 21078 </register> 21079 <register> 21080 <name>SEC_CTRL</name> 21081 <description>SPIX Memory Security Control Register.</description> 21082 <addressOffset>0x20</addressOffset> 21083 <fields> 21084 <field> 21085 <name>DEC_EN</name> 21086 <description>Decryption Enable.</description> 21087 <bitOffset>0</bitOffset> 21088 <bitWidth>1</bitWidth> 21089 <enumeratedValues> 21090 <enumeratedValue> 21091 <name>dis</name> 21092 <description>Disable decryption of SPIX data.</description> 21093 <value>0</value> 21094 </enumeratedValue> 21095 <enumeratedValue> 21096 <name>en</name> 21097 <description>Enable decryption of SPIX data.</description> 21098 <value>1</value> 21099 </enumeratedValue> 21100 </enumeratedValues> 21101 </field> 21102 <field> 21103 <name>AUTH_DISABLE</name> 21104 <description>Integrity Enable.</description> 21105 <bitOffset>1</bitOffset> 21106 <bitWidth>1</bitWidth> 21107 <enumeratedValues> 21108 <enumeratedValue> 21109 <name>en</name> 21110 <description>Integrity checking enabled.</description> 21111 <value>0</value> 21112 </enumeratedValue> 21113 <enumeratedValue> 21114 <name>dis</name> 21115 <description>Integrity checking disabled.</description> 21116 <value>1</value> 21117 </enumeratedValue> 21118 </enumeratedValues> 21119 </field> 21120 </fields> 21121 </register> 21122 <register> 21123 <name>BUS_IDLE</name> 21124 <description>Bus Idle</description> 21125 <addressOffset>0x24</addressOffset> 21126 <fields> 21127 <field> 21128 <name>BUSIDLE</name> 21129 <description>A 16-bit timer will be triggered for each external access. The timer will be 21130 restarted if another access is performed before the timer expires. When the 21131 timer expires, slave select will be deactivated.</description> 21132 <bitOffset>0</bitOffset> 21133 <bitWidth>16</bitWidth> 21134 </field> 21135 </fields> 21136 </register> 21137 <register> 21138 <name>AUTHOFFSET</name> 21139 <description>Auth Offset</description> 21140 <addressOffset>0x28</addressOffset> 21141 </register> 21142 </registers> 21143 </peripheral> 21144<!--SPIXFM SPIXF Master--> 21145 <peripheral> 21146 <name>SRCC</name> 21147 <description>SPIX Cache Controller Registers.</description> 21148 <baseAddress>0x40033000</baseAddress> 21149 <addressBlock> 21150 <offset>0x00</offset> 21151 <size>0x1000</size> 21152 <usage>registers</usage> 21153 </addressBlock> 21154 <registers> 21155 <register> 21156 <name>CACHE_ID</name> 21157 <description>Cache ID Register.</description> 21158 <addressOffset>0x0000</addressOffset> 21159 <access>read-only</access> 21160 <fields> 21161 <field> 21162 <name>RELNUM</name> 21163 <description>Release Number. Identifies the RTL release version.</description> 21164 <bitOffset>0</bitOffset> 21165 <bitWidth>6</bitWidth> 21166 </field> 21167 <field> 21168 <name>PARTNUM</name> 21169 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 21170 <bitOffset>6</bitOffset> 21171 <bitWidth>4</bitWidth> 21172 </field> 21173 <field> 21174 <name>CCHID</name> 21175 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 21176 <bitOffset>10</bitOffset> 21177 <bitWidth>6</bitWidth> 21178 </field> 21179 </fields> 21180 </register> 21181 <register> 21182 <name>MEMCFG</name> 21183 <description>Memory Configuration Register.</description> 21184 <addressOffset>0x0004</addressOffset> 21185 <access>read-only</access> 21186 <resetValue>0x00080008</resetValue> 21187 <fields> 21188 <field> 21189 <name>CCHSZ</name> 21190 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 21191 <bitOffset>0</bitOffset> 21192 <bitWidth>16</bitWidth> 21193 </field> 21194 <field> 21195 <name>MEMSZ</name> 21196 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 21197 <bitOffset>16</bitOffset> 21198 <bitWidth>16</bitWidth> 21199 </field> 21200 </fields> 21201 </register> 21202 <register> 21203 <name>CACHE_CTRL</name> 21204 <description>Cache Control and Status Register.</description> 21205 <addressOffset>0x0100</addressOffset> 21206 <fields> 21207 <field> 21208 <name>CACHE_EN</name> 21209 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 21210 <bitOffset>0</bitOffset> 21211 <bitWidth>1</bitWidth> 21212 <enumeratedValues> 21213 <enumeratedValue> 21214 <name>dis</name> 21215 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 21216 <value>0</value> 21217 </enumeratedValue> 21218 <enumeratedValue> 21219 <name>en</name> 21220 <description>Cache Enabled.</description> 21221 <value>1</value> 21222 </enumeratedValue> 21223 </enumeratedValues> 21224 </field> 21225 <field> 21226 <name>WRITE_ALLOC_EN</name> 21227 <description>Write Allocate Enable. This bit only writable while the cache is disabled.</description> 21228 <bitOffset>1</bitOffset> 21229 <bitWidth>1</bitWidth> 21230 <enumeratedValues> 21231 <enumeratedValue> 21232 <name>dis</name> 21233 <description>Write-no-allocate.</description> 21234 <value>0</value> 21235 </enumeratedValue> 21236 <enumeratedValue> 21237 <name>en</name> 21238 <description>Write-allocate enabled.</description> 21239 <value>1</value> 21240 </enumeratedValue> 21241 </enumeratedValues> 21242 </field> 21243 <field> 21244 <name>CWFST_DIS</name> 21245 <description>Critical word first and streaming disable. This bit only writeable while the cache is disabled.</description> 21246 <bitOffset>2</bitOffset> 21247 <bitWidth>1</bitWidth> 21248 <enumeratedValues> 21249 <enumeratedValue> 21250 <name>dis</name> 21251 <description>Critical word first and streaming disabled.</description> 21252 <value>1</value> 21253 </enumeratedValue> 21254 <enumeratedValue> 21255 <name>en</name> 21256 <description>Critical word first and streaming enabled.</description> 21257 <value>0</value> 21258 </enumeratedValue> 21259 </enumeratedValues> 21260 </field> 21261 <field> 21262 <name>CACHE_RDY</name> 21263 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 21264 <bitOffset>16</bitOffset> 21265 <bitWidth>1</bitWidth> 21266 <enumeratedValues> 21267 <enumeratedValue> 21268 <name>notReady</name> 21269 <description>Not Ready.</description> 21270 <value>0</value> 21271 </enumeratedValue> 21272 <enumeratedValue> 21273 <name>ready</name> 21274 <description>Ready.</description> 21275 <value>1</value> 21276 </enumeratedValue> 21277 </enumeratedValues> 21278 </field> 21279 </fields> 21280 </register> 21281 <register> 21282 <name>INVALIDATE</name> 21283 <description>Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.</description> 21284 <addressOffset>0x0700</addressOffset> 21285 <fields> 21286 <field> 21287 <name>IA</name> 21288 <description>Invalidate all cache contents.</description> 21289 <bitOffset>0</bitOffset> 21290 <bitWidth>32</bitWidth> 21291 </field> 21292 </fields> 21293 </register> 21294 </registers> 21295 </peripheral> 21296<!--SRCC SPIX Cache Controller Registers.--> 21297 <peripheral> 21298 <name>TMR0</name> 21299 <description>32-bit reloadable timer that can be used for timing and event counting.</description> 21300 <groupName>Timers</groupName> 21301 <baseAddress>0x40010000</baseAddress> 21302 <addressBlock> 21303 <offset>0x00</offset> 21304 <size>0x1000</size> 21305 <usage>registers</usage> 21306 </addressBlock> 21307 <interrupt> 21308 <name>TMR0</name> 21309 <description>TMR0 IRQ</description> 21310 <value>5</value> 21311 </interrupt> 21312 <registers> 21313 <register> 21314 <name>CNT</name> 21315 <description>Count. This register stores the current timer count.</description> 21316 <addressOffset>0x00</addressOffset> 21317 <resetValue>0x00000001</resetValue> 21318 </register> 21319 <register> 21320 <name>CMP</name> 21321 <description>Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.</description> 21322 <addressOffset>0x04</addressOffset> 21323 <resetValue>0x0000FFFF</resetValue> 21324 </register> 21325 <register> 21326 <name>PWM</name> 21327 <description>PWM. This register stores the value that is compared to the current timer count.</description> 21328 <addressOffset>0x08</addressOffset> 21329 </register> 21330 <register> 21331 <name>INTR</name> 21332 <description>Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.</description> 21333 <addressOffset>0x0C</addressOffset> 21334 <modifiedWriteValues>oneToClear</modifiedWriteValues> 21335 <fields> 21336 <field> 21337 <name>IRQ</name> 21338 <description>Clear Interrupt.</description> 21339 <bitOffset>0</bitOffset> 21340 <bitWidth>1</bitWidth> 21341 </field> 21342 </fields> 21343 </register> 21344 <register> 21345 <name>CN</name> 21346 <description>Timer Control Register.</description> 21347 <addressOffset>0x10</addressOffset> 21348 <fields> 21349 <field> 21350 <name>TMODE</name> 21351 <description>Timer Mode.</description> 21352 <bitOffset>0</bitOffset> 21353 <bitWidth>3</bitWidth> 21354 <enumeratedValues> 21355 <enumeratedValue> 21356 <name>oneShot</name> 21357 <description>One Shot Mode.</description> 21358 <value>0</value> 21359 </enumeratedValue> 21360 <enumeratedValue> 21361 <name>continuous</name> 21362 <description>Continuous Mode.</description> 21363 <value>1</value> 21364 </enumeratedValue> 21365 <enumeratedValue> 21366 <name>counter</name> 21367 <description>Counter Mode.</description> 21368 <value>2</value> 21369 </enumeratedValue> 21370 <enumeratedValue> 21371 <name>pwm</name> 21372 <description>PWM Mode.</description> 21373 <value>3</value> 21374 </enumeratedValue> 21375 <enumeratedValue> 21376 <name>capture</name> 21377 <description>Capture Mode.</description> 21378 <value>4</value> 21379 </enumeratedValue> 21380 <enumeratedValue> 21381 <name>compare</name> 21382 <description>Compare Mode.</description> 21383 <value>5</value> 21384 </enumeratedValue> 21385 <enumeratedValue> 21386 <name>gated</name> 21387 <description>Gated Mode.</description> 21388 <value>6</value> 21389 </enumeratedValue> 21390 <enumeratedValue> 21391 <name>captureCompare</name> 21392 <description>Capture/Compare Mode.</description> 21393 <value>7</value> 21394 </enumeratedValue> 21395 </enumeratedValues> 21396 </field> 21397 <field> 21398 <name>PRES</name> 21399 <description>Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].</description> 21400 <bitOffset>3</bitOffset> 21401 <bitWidth>3</bitWidth> 21402 <enumeratedValues> 21403 <enumeratedValue> 21404 <name>div1</name> 21405 <description>Divide by 1.</description> 21406 <value>0</value> 21407 </enumeratedValue> 21408 <enumeratedValue> 21409 <name>div2</name> 21410 <description>Divide by 2.</description> 21411 <value>1</value> 21412 </enumeratedValue> 21413 <enumeratedValue> 21414 <name>div4</name> 21415 <description>Divide by 4.</description> 21416 <value>2</value> 21417 </enumeratedValue> 21418 <enumeratedValue> 21419 <name>div8</name> 21420 <description>Divide by 8.</description> 21421 <value>3</value> 21422 </enumeratedValue> 21423 <enumeratedValue> 21424 <name>div16</name> 21425 <description>Divide by 16.</description> 21426 <value>4</value> 21427 </enumeratedValue> 21428 <enumeratedValue> 21429 <name>div32</name> 21430 <description>Divide by 32.</description> 21431 <value>5</value> 21432 </enumeratedValue> 21433 <enumeratedValue> 21434 <name>div64</name> 21435 <description>Divide by 64.</description> 21436 <value>6</value> 21437 </enumeratedValue> 21438 <enumeratedValue> 21439 <name>div128</name> 21440 <description>Divide by 128.</description> 21441 <value>7</value> 21442 </enumeratedValue> 21443 </enumeratedValues> 21444 </field> 21445 <field> 21446 <name>TPOL</name> 21447 <description>Timer input/output polarity bit.</description> 21448 <bitOffset>6</bitOffset> 21449 <bitWidth>1</bitWidth> 21450 <enumeratedValues> 21451 <enumeratedValue> 21452 <name>activeHi</name> 21453 <description>Active High.</description> 21454 <value>0</value> 21455 </enumeratedValue> 21456 <enumeratedValue> 21457 <name>activeLo</name> 21458 <description>Active Low.</description> 21459 <value>1</value> 21460 </enumeratedValue> 21461 </enumeratedValues> 21462 </field> 21463 <field> 21464 <name>TEN</name> 21465 <description>Timer Enable.</description> 21466 <bitOffset>7</bitOffset> 21467 <bitWidth>1</bitWidth> 21468 <enumeratedValues> 21469 <enumeratedValue> 21470 <name>dis</name> 21471 <description>Disable.</description> 21472 <value>0</value> 21473 </enumeratedValue> 21474 <enumeratedValue> 21475 <name>en</name> 21476 <description>Enable.</description> 21477 <value>1</value> 21478 </enumeratedValue> 21479 </enumeratedValues> 21480 </field> 21481 <field> 21482 <name>PRES3</name> 21483 <description>MSB of prescaler value.</description> 21484 <bitOffset>8</bitOffset> 21485 <bitWidth>1</bitWidth> 21486 </field> 21487 <field> 21488 <name>PWMSYNC</name> 21489 <description>Timer PWM Synchronization Mode Enable.</description> 21490 <bitOffset>9</bitOffset> 21491 <bitWidth>1</bitWidth> 21492 <enumeratedValues> 21493 <enumeratedValue> 21494 <name>dis</name> 21495 <description>Disable.</description> 21496 <value>0</value> 21497 </enumeratedValue> 21498 <enumeratedValue> 21499 <name>en</name> 21500 <description>Enable.</description> 21501 <value>1</value> 21502 </enumeratedValue> 21503 </enumeratedValues> 21504 </field> 21505 <field> 21506 <name>NOLHPOL</name> 21507 <description>Timer PWM output 0A polarity bit.</description> 21508 <bitOffset>10</bitOffset> 21509 <bitWidth>1</bitWidth> 21510 <enumeratedValues> 21511 <enumeratedValue> 21512 <name>dis</name> 21513 <description>Disable.</description> 21514 <value>0</value> 21515 </enumeratedValue> 21516 <enumeratedValue> 21517 <name>en</name> 21518 <description>Enable.</description> 21519 <value>1</value> 21520 </enumeratedValue> 21521 </enumeratedValues> 21522 </field> 21523 <field> 21524 <name>NOLLPOL</name> 21525 <description>Timer PWM output 0A' polarity bit.</description> 21526 <bitOffset>11</bitOffset> 21527 <bitWidth>1</bitWidth> 21528 <enumeratedValues> 21529 <enumeratedValue> 21530 <name>dis</name> 21531 <description>Disable.</description> 21532 <value>0</value> 21533 </enumeratedValue> 21534 <enumeratedValue> 21535 <name>en</name> 21536 <description>Enable.</description> 21537 <value>1</value> 21538 </enumeratedValue> 21539 </enumeratedValues> 21540 </field> 21541 <field> 21542 <name>PWMCKBD</name> 21543 <description>Timer PWM output 0A Mode Disable.</description> 21544 <bitOffset>12</bitOffset> 21545 <bitWidth>1</bitWidth> 21546 <enumeratedValues> 21547 <enumeratedValue> 21548 <name>dis</name> 21549 <description>Disable.</description> 21550 <value>1</value> 21551 </enumeratedValue> 21552 <enumeratedValue> 21553 <name>en</name> 21554 <description>Enable.</description> 21555 <value>0</value> 21556 </enumeratedValue> 21557 </enumeratedValues> 21558 </field> 21559 </fields> 21560 </register> 21561 <register> 21562 <name>NOLCMP</name> 21563 <description>Timer Non-Overlapping Compare Register.</description> 21564 <addressOffset>0x14</addressOffset> 21565 <fields> 21566 <field> 21567 <name>NOLLCMP</name> 21568 <description>Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.</description> 21569 <bitOffset>0</bitOffset> 21570 <bitWidth>8</bitWidth> 21571 </field> 21572 <field> 21573 <name>NOLHCMP</name> 21574 <description>Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.</description> 21575 <bitOffset>8</bitOffset> 21576 <bitWidth>8</bitWidth> 21577 </field> 21578 </fields> 21579 </register> 21580 </registers> 21581 </peripheral> 21582<!--TMR0 32-bit reloadable timer that can be used for timing and event counting.--> 21583 <peripheral derivedFrom="TMR0"> 21584 <name>TMR1</name> 21585 <description>32-bit reloadable timer that can be used for timing and event counting. 1</description> 21586 <baseAddress>0x40011000</baseAddress> 21587 <interrupt> 21588 <name>TMR1</name> 21589 <description>TMR1 IRQ</description> 21590 <value>6</value> 21591 </interrupt> 21592 </peripheral> 21593<!--TMR1 32-bit reloadable timer that can be used for timing and event counting. 1--> 21594 <peripheral derivedFrom="TMR0"> 21595 <name>TMR2</name> 21596 <description>32-bit reloadable timer that can be used for timing and event counting. 2</description> 21597 <baseAddress>0x40012000</baseAddress> 21598 <interrupt> 21599 <name>TMR2</name> 21600 <description>TMR2 IRQ</description> 21601 <value>7</value> 21602 </interrupt> 21603 </peripheral> 21604<!--TMR2 32-bit reloadable timer that can be used for timing and event counting. 2--> 21605 <peripheral derivedFrom="TMR0"> 21606 <name>TMR3</name> 21607 <description>32-bit reloadable timer that can be used for timing and event counting. 3</description> 21608 <baseAddress>0x40013000</baseAddress> 21609 <interrupt> 21610 <name>TMR3</name> 21611 <description>TMR3 IRQ</description> 21612 <value>8</value> 21613 </interrupt> 21614 </peripheral> 21615<!--TMR3 32-bit reloadable timer that can be used for timing and event counting. 3--> 21616 <peripheral derivedFrom="TMR0"> 21617 <name>TMR4</name> 21618 <description>32-bit reloadable timer that can be used for timing and event counting. 4</description> 21619 <baseAddress>0x40014000</baseAddress> 21620 <interrupt> 21621 <name>TMR4</name> 21622 <description>TMR4 IRQ</description> 21623 <value>9</value> 21624 </interrupt> 21625 </peripheral> 21626<!--TMR4 32-bit reloadable timer that can be used for timing and event counting. 4--> 21627 <peripheral derivedFrom="TMR0"> 21628 <name>TMR5</name> 21629 <description>32-bit reloadable timer that can be used for timing and event counting. 5</description> 21630 <baseAddress>0x40015000</baseAddress> 21631 <interrupt> 21632 <name>TMR5</name> 21633 <description>TMR5 IRQ</description> 21634 <value>10</value> 21635 </interrupt> 21636 </peripheral> 21637<!--TMR5 32-bit reloadable timer that can be used for timing and event counting. 5--> 21638 <peripheral> 21639 <name>TRIMSIR</name> 21640 <description>Trim System Initilazation Registers</description> 21641 <baseAddress>0x40005400</baseAddress> 21642 <addressBlock> 21643 <offset>0x00</offset> 21644 <size>0x400</size> 21645 <usage>registers</usage> 21646 </addressBlock> 21647 <registers> 21648 <register> 21649 <name>rsv0</name> 21650 <description>RFU</description> 21651 <addressOffset>0x00</addressOffset> 21652 </register> 21653 <register> 21654 <name>BB_SIR2</name> 21655 <description>System Init. Configuration Register 2.</description> 21656 <addressOffset>0x08</addressOffset> 21657 <access>read-only</access> 21658 </register> 21659 <register> 21660 <name>BB_SIR3</name> 21661 <description>System Init. Configuration Register 3.</description> 21662 <addressOffset>0x0C</addressOffset> 21663 <access>read-only</access> 21664 </register> 21665 </registers> 21666 </peripheral> 21667<!--TRIMSIR Trim System Initilazation Registers--> 21668 <peripheral> 21669 <name>TRNG</name> 21670 <description>Random Number Generator.</description> 21671 <baseAddress>0x4004D000</baseAddress> 21672 <addressBlock> 21673 <offset>0x00</offset> 21674 <size>0x1000</size> 21675 <usage>registers</usage> 21676 </addressBlock> 21677 <interrupt> 21678 <name>TRNG</name> 21679 <description>TRNG interrupt.</description> 21680 <value>4</value> 21681 </interrupt> 21682 <registers> 21683 <register> 21684 <name>CN</name> 21685 <description>TRNG Control Register.</description> 21686 <addressOffset>0x00</addressOffset> 21687 <resetValue>0x00000003</resetValue> 21688 <fields> 21689 <field> 21690 <name>RND_IRQ_EN</name> 21691 <description>To enable IRQ generation when a new 32-bit Random number is ready.</description> 21692 <bitOffset>1</bitOffset> 21693 <bitWidth>1</bitWidth> 21694 <enumeratedValues> 21695 <enumeratedValue> 21696 <name>disable</name> 21697 <description>Disable</description> 21698 <value>0</value> 21699 </enumeratedValue> 21700 <enumeratedValue> 21701 <name>enable</name> 21702 <description>Enable</description> 21703 <value>1</value> 21704 </enumeratedValue> 21705 </enumeratedValues> 21706 </field> 21707 <field> 21708 <name>AESKG</name> 21709 <description>AES Key Generate.</description> 21710 <bitOffset>3</bitOffset> 21711 <bitWidth>1</bitWidth> 21712 </field> 21713 <field> 21714 <name>AESKG_MEMPROTE</name> 21715 <description>AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.</description> 21716 <bitOffset>4</bitOffset> 21717 <bitWidth>1</bitWidth> 21718 </field> 21719 </fields> 21720 </register> 21721 <register> 21722 <name>ST</name> 21723 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 21724 <addressOffset>0x04</addressOffset> 21725 <access>read-only</access> 21726 <fields> 21727 <field> 21728 <name>RND_RDY</name> 21729 <description>32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.</description> 21730 <bitOffset>0</bitOffset> 21731 <bitWidth>1</bitWidth> 21732 <enumeratedValues> 21733 <enumeratedValue> 21734 <name>Busy</name> 21735 <description>TRNG Busy</description> 21736 <value>0</value> 21737 </enumeratedValue> 21738 <enumeratedValue> 21739 <name>Ready</name> 21740 <description>32 bit random data is ready</description> 21741 <value>1</value> 21742 </enumeratedValue> 21743 </enumeratedValues> 21744 </field> 21745 <field> 21746 <name>AESKGD_MEU_S</name> 21747 <description>Automatically AES transfer on going</description> 21748 <bitOffset>4</bitOffset> 21749 <bitWidth>1</bitWidth> 21750 </field> 21751 </fields> 21752 </register> 21753 <register> 21754 <name>DATA</name> 21755 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 21756 <addressOffset>0x08</addressOffset> 21757 <access>read-only</access> 21758 <fields> 21759 <field> 21760 <name>DATA</name> 21761 <description>Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.</description> 21762 <bitOffset>0</bitOffset> 21763 <bitWidth>32</bitWidth> 21764 </field> 21765 </fields> 21766 </register> 21767 </registers> 21768 </peripheral> 21769<!--TRNG Random Number Generator.--> 21770 <peripheral> 21771 <name>UART0</name> 21772 <description>UART</description> 21773 <baseAddress>0x40042000</baseAddress> 21774 <addressBlock> 21775 <offset>0</offset> 21776 <size>0x1000</size> 21777 <usage>registers</usage> 21778 </addressBlock> 21779 <interrupt> 21780 <name>UART0</name> 21781 <description>UART0 IRQ</description> 21782 <value>14</value> 21783 </interrupt> 21784 <registers> 21785 <register> 21786 <name>CTRL</name> 21787 <description>Control Register.</description> 21788 <addressOffset>0x00</addressOffset> 21789 <size>32</size> 21790 <fields> 21791 <field> 21792 <name>ENABLE</name> 21793 <description>UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.</description> 21794 <bitOffset>0</bitOffset> 21795 <bitWidth>1</bitWidth> 21796 <enumeratedValues> 21797 <enumeratedValue> 21798 <name>dis</name> 21799 <description>UART disabled. FIFOs are flushed. Clock is gated off for power savings. </description> 21800 <value>0</value> 21801 </enumeratedValue> 21802 <enumeratedValue> 21803 <name>en</name> 21804 <description>UART enabled. </description> 21805 <value>1</value> 21806 </enumeratedValue> 21807 </enumeratedValues> 21808 </field> 21809 <field> 21810 <name>PARITY_EN</name> 21811 <description>Enable/disable Parity bit (9th character).</description> 21812 <bitOffset>1</bitOffset> 21813 <bitWidth>1</bitWidth> 21814 <enumeratedValues> 21815 <enumeratedValue> 21816 <name>dis</name> 21817 <description>No Parity </description> 21818 <value>0</value> 21819 </enumeratedValue> 21820 <enumeratedValue> 21821 <name>en</name> 21822 <description>Parity enabled as 9th bit</description> 21823 <value>1</value> 21824 </enumeratedValue> 21825 </enumeratedValues> 21826 </field> 21827 <field> 21828 <name>PARITY</name> 21829 <description>When PARITY_EN=1, selects odd, even, Mark or Space parity. 21830 Mark parity = always 1; 21831 21832 Space parity = always 0.</description> 21833 <bitOffset>2</bitOffset> 21834 <bitWidth>2</bitWidth> 21835 <enumeratedValues> 21836 <enumeratedValue> 21837 <name>Even</name> 21838 <description>Even parity selected.</description> 21839 <value>0</value> 21840 </enumeratedValue> 21841 <enumeratedValue> 21842 <name>ODD</name> 21843 <description>Odd parity selected.</description> 21844 <value>1</value> 21845 </enumeratedValue> 21846 <enumeratedValue> 21847 <name>MARK</name> 21848 <description>Mark parity selected.</description> 21849 <value>2</value> 21850 </enumeratedValue> 21851 <enumeratedValue> 21852 <name>SPACE</name> 21853 <description>Space parity selected.</description> 21854 <value>3</value> 21855 </enumeratedValue> 21856 </enumeratedValues> 21857 </field> 21858 <field> 21859 <name>PARMD</name> 21860 <description>Selects parity based on 1s or 0s count (when PARITY_EN=1).</description> 21861 <bitOffset>4</bitOffset> 21862 <bitWidth>1</bitWidth> 21863 <enumeratedValues> 21864 <enumeratedValue> 21865 <name>1</name> 21866 <description>Parity calculation is based on number of 1s in frame.</description> 21867 <value>0</value> 21868 </enumeratedValue> 21869 <enumeratedValue> 21870 <name>0</name> 21871 <description>Parity calculation is based on number of 0s in frame.</description> 21872 <value>1</value> 21873 </enumeratedValue> 21874 </enumeratedValues> 21875 </field> 21876 <field> 21877 <name>TX_FLUSH</name> 21878 <description>Flushes the TX FIFO buffer.</description> 21879 <bitOffset>5</bitOffset> 21880 <bitWidth>1</bitWidth> 21881 </field> 21882 <field> 21883 <name>RX_FLUSH</name> 21884 <description>Flushes the RX FIFO buffer.</description> 21885 <bitOffset>6</bitOffset> 21886 <bitWidth>1</bitWidth> 21887 </field> 21888 <field> 21889 <name>BITACC</name> 21890 <description>If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.</description> 21891 <bitOffset>7</bitOffset> 21892 <bitWidth>1</bitWidth> 21893 <enumeratedValues> 21894 <enumeratedValue> 21895 <name>FRAME</name> 21896 <description>Frame accuracy.</description> 21897 <value>0</value> 21898 </enumeratedValue> 21899 <enumeratedValue> 21900 <name>BIT</name> 21901 <description>Bit accuracy.</description> 21902 <value>1</value> 21903 </enumeratedValue> 21904 </enumeratedValues> 21905 </field> 21906 <field> 21907 <name>CHAR_SIZE</name> 21908 <description>Selects UART character size.</description> 21909 <bitOffset>8</bitOffset> 21910 <bitWidth>2</bitWidth> 21911 <enumeratedValues> 21912 <enumeratedValue> 21913 <name>5</name> 21914 <description>5 bits.</description> 21915 <value>0</value> 21916 </enumeratedValue> 21917 <enumeratedValue> 21918 <name>6</name> 21919 <description>6 bits.</description> 21920 <value>1</value> 21921 </enumeratedValue> 21922 <enumeratedValue> 21923 <name>7</name> 21924 <description>7 bits.</description> 21925 <value>2</value> 21926 </enumeratedValue> 21927 <enumeratedValue> 21928 <name>8</name> 21929 <description>8 bits.</description> 21930 <value>3</value> 21931 </enumeratedValue> 21932 </enumeratedValues> 21933 </field> 21934 <field> 21935 <name>STOPBITS</name> 21936 <description>Selects the number of stop bits that will be generated.</description> 21937 <bitOffset>10</bitOffset> 21938 <bitWidth>1</bitWidth> 21939 <enumeratedValues> 21940 <enumeratedValue> 21941 <name>1</name> 21942 <description>1 stop bit.</description> 21943 <value>0</value> 21944 </enumeratedValue> 21945 <enumeratedValue> 21946 <name>1_5</name> 21947 <description>1.5 stop bits.</description> 21948 <value>1</value> 21949 </enumeratedValue> 21950 </enumeratedValues> 21951 </field> 21952 <field> 21953 <name>FLOW_CTRL</name> 21954 <description>Enables/disables hardware flow control.</description> 21955 <bitOffset>11</bitOffset> 21956 <bitWidth>1</bitWidth> 21957 <enumeratedValues> 21958 <enumeratedValue> 21959 <name>en</name> 21960 <description>HW Flow Control with RTS/CTS enabled</description> 21961 <value>1</value> 21962 </enumeratedValue> 21963 <enumeratedValue> 21964 <name>dis</name> 21965 <description>HW Flow Control disabled</description> 21966 <value>0</value> 21967 </enumeratedValue> 21968 </enumeratedValues> 21969 </field> 21970 <field> 21971 <name>FLOW_POL</name> 21972 <description>RTS/CTS polarity.</description> 21973 <bitOffset>12</bitOffset> 21974 <bitWidth>1</bitWidth> 21975 <enumeratedValues> 21976 <enumeratedValue> 21977 <name>0</name> 21978 <description>RTS/CTS asserted is logic 0.</description> 21979 <value>0</value> 21980 </enumeratedValue> 21981 <enumeratedValue> 21982 <name>1</name> 21983 <description>RTS/CTS asserted is logic 1.</description> 21984 <value>1</value> 21985 </enumeratedValue> 21986 </enumeratedValues> 21987 </field> 21988 <field> 21989 <name>NULL_MODEM</name> 21990 <description>NULL Modem Support (RTS/CTS and TXD/RXD swap).</description> 21991 <bitOffset>13</bitOffset> 21992 <bitWidth>1</bitWidth> 21993 <enumeratedValues> 21994 <enumeratedValue> 21995 <name>DIS</name> 21996 <description>Direct convention.</description> 21997 <value>0</value> 21998 </enumeratedValue> 21999 <enumeratedValue> 22000 <name>EN</name> 22001 <description>Null Modem Mode.</description> 22002 <value>1</value> 22003 </enumeratedValue> 22004 </enumeratedValues> 22005 </field> 22006 <field> 22007 <name>BREAK</name> 22008 <description>Break control bit. It causes a break condition to be transmitted to receiving UART.</description> 22009 <bitOffset>14</bitOffset> 22010 <bitWidth>1</bitWidth> 22011 <enumeratedValues> 22012 <enumeratedValue> 22013 <name>DIS</name> 22014 <description>Break characters are not generated.</description> 22015 <value>0</value> 22016 </enumeratedValue> 22017 <enumeratedValue> 22018 <name>EN</name> 22019 <description>Break characters are sent (all the bits are at '0' including start/parity/stop).</description> 22020 <value>1</value> 22021 </enumeratedValue> 22022 </enumeratedValues> 22023 </field> 22024 <field> 22025 <name>CLKSEL</name> 22026 <description>Baud Rate Clock Source Select. Selects the baud rate clock.</description> 22027 <bitOffset>15</bitOffset> 22028 <bitWidth>1</bitWidth> 22029 <enumeratedValues> 22030 <enumeratedValue> 22031 <name>SYSTEM</name> 22032 <description>System clock.</description> 22033 <value>0</value> 22034 </enumeratedValue> 22035 <enumeratedValue> 22036 <name>ALTERNATE</name> 22037 <description>Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.</description> 22038 <value>1</value> 22039 </enumeratedValue> 22040 </enumeratedValues> 22041 </field> 22042 <field> 22043 <name>RX_TO</name> 22044 <description>RX Time Out. RX time out interrupt will occur after RXTO Uart 22045 characters if RX-FIFO is not empty and RX FIFO has not been read.</description> 22046 <bitOffset>16</bitOffset> 22047 <bitWidth>8</bitWidth> 22048 </field> 22049 </fields> 22050 </register> 22051 <register> 22052 <name>THRESH_CTRL</name> 22053 <description>Threshold Control register.</description> 22054 <addressOffset>0x04</addressOffset> 22055 <size>32</size> 22056 <fields> 22057 <field> 22058 <name>RX_FIFO_THRESH</name> 22059 <description>RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.</description> 22060 <bitOffset>0</bitOffset> 22061 <bitWidth>6</bitWidth> 22062 </field> 22063 <field> 22064 <name>TX_FIFO_THRESH</name> 22065 <description>TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.</description> 22066 <bitOffset>8</bitOffset> 22067 <bitWidth>6</bitWidth> 22068 </field> 22069 <field> 22070 <name>RTS_FIFO_THRESH</name> 22071 <description>RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.</description> 22072 <bitOffset>16</bitOffset> 22073 <bitWidth>6</bitWidth> 22074 </field> 22075 </fields> 22076 </register> 22077 <register> 22078 <name>STATUS</name> 22079 <description>Status Register.</description> 22080 <addressOffset>0x08</addressOffset> 22081 <size>32</size> 22082 <access>read-only</access> 22083 <fields> 22084 <field> 22085 <name>TX_BUSY</name> 22086 <description>Read-only flag indicating the UART transmit status.</description> 22087 <bitOffset>0</bitOffset> 22088 <bitWidth>1</bitWidth> 22089 <access>read-only</access> 22090 </field> 22091 <field> 22092 <name>RX_BUSY</name> 22093 <description>Read-only flag indicating the UARTreceiver status.</description> 22094 <bitOffset>1</bitOffset> 22095 <bitWidth>1</bitWidth> 22096 <access>read-only</access> 22097 </field> 22098 <field> 22099 <name>PARITY</name> 22100 <description>9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.</description> 22101 <bitOffset>2</bitOffset> 22102 <bitWidth>1</bitWidth> 22103 <access>read-only</access> 22104 </field> 22105 <field> 22106 <name>BREAK</name> 22107 <description>Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).</description> 22108 <bitOffset>3</bitOffset> 22109 <bitWidth>1</bitWidth> 22110 <access>read-only</access> 22111 </field> 22112 <field> 22113 <name>RX_EMPTY</name> 22114 <description>Read-only flag indicating the RX FIFO state.</description> 22115 <bitOffset>4</bitOffset> 22116 <bitWidth>1</bitWidth> 22117 <access>read-only</access> 22118 </field> 22119 <field> 22120 <name>RX_FULL</name> 22121 <description>Read-only flag indicating the RX FIFO state.</description> 22122 <bitOffset>5</bitOffset> 22123 <bitWidth>1</bitWidth> 22124 <access>read-only</access> 22125 </field> 22126 <field> 22127 <name>TX_EMPTY</name> 22128 <description>Read-only flag indicating the TX FIFO state.</description> 22129 <bitOffset>6</bitOffset> 22130 <bitWidth>1</bitWidth> 22131 <access>read-only</access> 22132 </field> 22133 <field> 22134 <name>TX_FULL</name> 22135 <description>Read-only flag indicating the TX FIFO state.</description> 22136 <bitOffset>7</bitOffset> 22137 <bitWidth>1</bitWidth> 22138 <access>read-only</access> 22139 </field> 22140 <field> 22141 <name>RX_FIFO_CNT</name> 22142 <description>Indicates the number of bytes currently in the RX FIFO.</description> 22143 <bitOffset>8</bitOffset> 22144 <bitWidth>6</bitWidth> 22145 <access>read-only</access> 22146 </field> 22147 <field> 22148 <name>TX_FIFO_CNT</name> 22149 <description>Indicates the number of bytes currently in the TX FIFO.</description> 22150 <bitOffset>16</bitOffset> 22151 <bitWidth>6</bitWidth> 22152 <access>read-only</access> 22153 </field> 22154 </fields> 22155 </register> 22156 <register> 22157 <name>INT_EN</name> 22158 <description>Interrupt Enable Register.</description> 22159 <addressOffset>0x0C</addressOffset> 22160 <size>32</size> 22161 <fields> 22162 <field> 22163 <name>RX_FRAME_ERROR</name> 22164 <description>Enable for RX Frame Error Interrupt.</description> 22165 <bitOffset>0</bitOffset> 22166 <bitWidth>1</bitWidth> 22167 </field> 22168 <field> 22169 <name>RX_PARITY_ERROR</name> 22170 <description>Enable for RX Parity Error interrupt.</description> 22171 <bitOffset>1</bitOffset> 22172 <bitWidth>1</bitWidth> 22173 </field> 22174 <field> 22175 <name>CTS_CHANGE</name> 22176 <description>Enable for CTS signal change interrupt.</description> 22177 <bitOffset>2</bitOffset> 22178 <bitWidth>1</bitWidth> 22179 </field> 22180 <field> 22181 <name>RX_OVERRUN</name> 22182 <description>Enable for RX FIFO OVerrun interrupt.</description> 22183 <bitOffset>3</bitOffset> 22184 <bitWidth>1</bitWidth> 22185 </field> 22186 <field> 22187 <name>RX_FIFO_THRESH</name> 22188 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 22189 <bitOffset>4</bitOffset> 22190 <bitWidth>1</bitWidth> 22191 </field> 22192 <field> 22193 <name>TX_FIFO_ALMOST_EMPTY</name> 22194 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 22195 <bitOffset>5</bitOffset> 22196 <bitWidth>1</bitWidth> 22197 </field> 22198 <field> 22199 <name>TX_FIFO_THRESH</name> 22200 <description>Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 22201 <bitOffset>6</bitOffset> 22202 <bitWidth>1</bitWidth> 22203 </field> 22204 <field> 22205 <name>BREAK</name> 22206 <description>Enable for received BREAK character interrupt.</description> 22207 <bitOffset>7</bitOffset> 22208 <bitWidth>1</bitWidth> 22209 </field> 22210 <field> 22211 <name>RX_TIMEOUT</name> 22212 <description>Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 22213 <bitOffset>8</bitOffset> 22214 <bitWidth>1</bitWidth> 22215 </field> 22216 <field> 22217 <name>LAST_BREAK</name> 22218 <description>Enable for Last break character interrupt.</description> 22219 <bitOffset>9</bitOffset> 22220 <bitWidth>1</bitWidth> 22221 </field> 22222 </fields> 22223 </register> 22224 <register> 22225 <name>INT_FL</name> 22226 <description>Interrupt Status Flags.</description> 22227 <addressOffset>0x10</addressOffset> 22228 <size>32</size> 22229 <modifiedWriteValues>oneToClear</modifiedWriteValues> 22230 <fields> 22231 <field> 22232 <name>FRAME</name> 22233 <description>FLAG for RX Frame Error Interrupt.</description> 22234 <bitOffset>0</bitOffset> 22235 <bitWidth>1</bitWidth> 22236 </field> 22237 <field> 22238 <name>PARITY</name> 22239 <description>FLAG for RX Parity Error interrupt.</description> 22240 <bitOffset>1</bitOffset> 22241 <bitWidth>1</bitWidth> 22242 </field> 22243 <field> 22244 <name>CTS_CHANGE</name> 22245 <description>FLAG for CTS signal change interrupt.</description> 22246 <bitOffset>2</bitOffset> 22247 <bitWidth>1</bitWidth> 22248 </field> 22249 <field> 22250 <name>RX_OVERRUN</name> 22251 <description>FLAG for RX FIFO Overrun interrupt.</description> 22252 <bitOffset>3</bitOffset> 22253 <bitWidth>1</bitWidth> 22254 </field> 22255 <field> 22256 <name>RX_FIFO_THRESH</name> 22257 <description>FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 22258 <bitOffset>4</bitOffset> 22259 <bitWidth>1</bitWidth> 22260 </field> 22261 <field> 22262 <name>TX_FIFO_ALMOST_EMPTY</name> 22263 <description>FLAG for interrupt when TX FIFO has only one byte remaining.</description> 22264 <bitOffset>5</bitOffset> 22265 <bitWidth>1</bitWidth> 22266 </field> 22267 <field> 22268 <name>TX_FIFO_THRESH</name> 22269 <description>FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.</description> 22270 <bitOffset>6</bitOffset> 22271 <bitWidth>1</bitWidth> 22272 </field> 22273 <field> 22274 <name>BREAK</name> 22275 <description>FLAG for received BREAK character interrupt.</description> 22276 <bitOffset>7</bitOffset> 22277 <bitWidth>1</bitWidth> 22278 </field> 22279 <field> 22280 <name>RX_TIMEOUT</name> 22281 <description>FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).</description> 22282 <bitOffset>8</bitOffset> 22283 <bitWidth>1</bitWidth> 22284 </field> 22285 <field> 22286 <name>LAST_BREAK</name> 22287 <description>FLAG for Last break character interrupt.</description> 22288 <bitOffset>9</bitOffset> 22289 <bitWidth>1</bitWidth> 22290 </field> 22291 </fields> 22292 </register> 22293 <register> 22294 <name>BAUD0</name> 22295 <description>Baud rate register. Integer portion.</description> 22296 <addressOffset>0x14</addressOffset> 22297 <size>32</size> 22298 <fields> 22299 <field> 22300 <name>IBAUD</name> 22301 <description>Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).</description> 22302 <bitOffset>0</bitOffset> 22303 <bitWidth>12</bitWidth> 22304 </field> 22305 <field> 22306 <name>FACTOR</name> 22307 <description>FACTOR must be chosen to have IDIV> 22308 0. factor used in calculation = 128 > 22309 > 22310 FACTOR. 22311 </description> 22312 <bitOffset>16</bitOffset> 22313 <bitWidth>3</bitWidth> 22314 <enumeratedValues> 22315 <enumeratedValue> 22316 <name>128</name> 22317 <description>Baud Factor 128</description> 22318 <value>0</value> 22319 </enumeratedValue> 22320 <enumeratedValue> 22321 <name>64</name> 22322 <description>Baud Factor 64</description> 22323 <value>1</value> 22324 </enumeratedValue> 22325 <enumeratedValue> 22326 <name>32</name> 22327 <description>Baud Factor 32</description> 22328 <value>2</value> 22329 </enumeratedValue> 22330 <enumeratedValue> 22331 <name>16</name> 22332 <description>Baud Factor 16</description> 22333 <value>3</value> 22334 </enumeratedValue> 22335 </enumeratedValues> 22336 </field> 22337 </fields> 22338 </register> 22339 <register> 22340 <name>BAUD1</name> 22341 <description>Baud rate register. Decimal Setting.</description> 22342 <addressOffset>0x18</addressOffset> 22343 <size>32</size> 22344 <fields> 22345 <field> 22346 <name>DBAUD</name> 22347 <description>Decimal portion of baud rate divisor value. DIV = InputClock/ (factor*Baud Rate Frequency). DDIV= (DIV-IDIV) *128.</description> 22348 <bitOffset>0</bitOffset> 22349 <bitWidth>12</bitWidth> 22350 </field> 22351 </fields> 22352 </register> 22353 <register> 22354 <name>FIFO</name> 22355 <description>FIFO Data buffer.</description> 22356 <addressOffset>0x1C</addressOffset> 22357 <size>32</size> 22358 <fields> 22359 <field> 22360 <name>FIFO</name> 22361 <description>Load/unload location for TX and RX FIFO buffers.</description> 22362 <bitOffset>0</bitOffset> 22363 <bitWidth>8</bitWidth> 22364 </field> 22365 </fields> 22366 </register> 22367 <register> 22368 <name>DMA</name> 22369 <description>DMA Configuration.</description> 22370 <addressOffset>0x20</addressOffset> 22371 <size>32</size> 22372 <fields> 22373 <field> 22374 <name>TXDMA_EN</name> 22375 <description>TX DMA channel enable.</description> 22376 <bitOffset>0</bitOffset> 22377 <bitWidth>1</bitWidth> 22378 <enumeratedValues> 22379 <enumeratedValue> 22380 <name>dis</name> 22381 <description>DMA is disabled </description> 22382 <value>0</value> 22383 </enumeratedValue> 22384 <enumeratedValue> 22385 <name>en</name> 22386 <description>DMA is enabled </description> 22387 <value>1</value> 22388 </enumeratedValue> 22389 </enumeratedValues> 22390 </field> 22391 <field> 22392 <name>RXDMA_EN</name> 22393 <description>RX DMA channel enable.</description> 22394 <bitOffset>1</bitOffset> 22395 <bitWidth>1</bitWidth> 22396 <enumeratedValues> 22397 <enumeratedValue> 22398 <name>dis</name> 22399 <description>DMA is disabled </description> 22400 <value>0</value> 22401 </enumeratedValue> 22402 <enumeratedValue> 22403 <name>en</name> 22404 <description>DMA is enabled </description> 22405 <value>1</value> 22406 </enumeratedValue> 22407 </enumeratedValues> 22408 </field> 22409 <field> 22410 <name>RXDMA_START</name> 22411 <description>Receive DMA Start.</description> 22412 <bitOffset>3</bitOffset> 22413 <bitWidth>1</bitWidth> 22414 </field> 22415 <field> 22416 <name>RXDMA_AUTO_TO</name> 22417 <description>Receive DMA Timeout Start.</description> 22418 <bitOffset>5</bitOffset> 22419 <bitWidth>1</bitWidth> 22420 </field> 22421 <field> 22422 <name>TXDMA_LEVEL</name> 22423 <description>TX threshold for DMA transmission.</description> 22424 <bitOffset>8</bitOffset> 22425 <bitWidth>6</bitWidth> 22426 </field> 22427 <field> 22428 <name>RXDMA_LEVEL</name> 22429 <description>RX threshold for DMA transmission.</description> 22430 <bitOffset>16</bitOffset> 22431 <bitWidth>6</bitWidth> 22432 </field> 22433 </fields> 22434 </register> 22435 <register> 22436 <name>TX_FIFO</name> 22437 <description>Transmit FIFO Status register.</description> 22438 <addressOffset>0x24</addressOffset> 22439 <size>32</size> 22440 <fields> 22441 <field> 22442 <name>DATA</name> 22443 <description>Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).</description> 22444 <bitOffset>0</bitOffset> 22445 <bitWidth>8</bitWidth> 22446 </field> 22447 </fields> 22448 </register> 22449 </registers> 22450 </peripheral> 22451<!--UART0 UART--> 22452 <peripheral derivedFrom="UART0"> 22453 <name>UART1</name> 22454 <description>UART 1</description> 22455 <baseAddress>0x40043000</baseAddress> 22456 <interrupt> 22457 <name>UART1</name> 22458 <description>UART1 IRQ</description> 22459 <value>15</value> 22460 </interrupt> 22461 </peripheral> 22462<!--UART1 UART 1--> 22463 <peripheral derivedFrom="UART0"> 22464 <name>UART2</name> 22465 <description>UART 2</description> 22466 <baseAddress>0x40044000</baseAddress> 22467 <interrupt> 22468 <name>UART2</name> 22469 <description>UART2 IRQ</description> 22470 <value>34</value> 22471 </interrupt> 22472 </peripheral> 22473<!--UART2 UART 2--> 22474 <peripheral derivedFrom="UART0"> 22475 <name>UART3</name> 22476 <description>UART 3</description> 22477 <baseAddress>0x40045000</baseAddress> 22478 <interrupt> 22479 <name>UART3</name> 22480 <description>UART3 IRQ</description> 22481 <value>88</value> 22482 </interrupt> 22483 </peripheral> 22484<!--UART3 UART 3--> 22485 <peripheral derivedFrom="UART0"> 22486 <name>UART4</name> 22487 <description>UART 4</description> 22488 <baseAddress>0x40023000</baseAddress> 22489 <interrupt> 22490 <name>UART4</name> 22491 <description>UART4 IRQ</description> 22492 <value>89</value> 22493 </interrupt> 22494 </peripheral> 22495<!--UART4 UART 4--> 22496 <peripheral derivedFrom="UART0"> 22497 <name>UART5</name> 22498 <description>UART 5</description> 22499 <baseAddress>0x40024000</baseAddress> 22500 <interrupt> 22501 <name>UART5</name> 22502 <description>UART5 IRQ</description> 22503 <value>90</value> 22504 </interrupt> 22505 </peripheral> 22506<!--UART5 UART 5--> 22507 <peripheral> 22508 <name>USBHS</name> 22509 <description>USB 2.0 High-speed Controller.</description> 22510 <baseAddress>0x400B1000</baseAddress> 22511 <addressBlock> 22512 <offset>0</offset> 22513 <size>0x1000</size> 22514 <usage>registers</usage> 22515 </addressBlock> 22516 <interrupt> 22517 <name>USB</name> 22518 <value>2</value> 22519 </interrupt> 22520 <registers> 22521 <register> 22522 <name>FADDR</name> 22523 <description>Function address register.</description> 22524 <addressOffset>0x00</addressOffset> 22525 <size>8</size> 22526 <resetMask>0x00</resetMask> 22527 <fields> 22528 <field> 22529 <name>ADDR</name> 22530 <description>Function address for this controller.</description> 22531 <bitOffset>0</bitOffset> 22532 <bitWidth>7</bitWidth> 22533 <access>read-write</access> 22534 </field> 22535 <field> 22536 <name>UPDATE</name> 22537 <description>Set when ADDR is written, cleared when new address takes effect.</description> 22538 <bitOffset>7</bitOffset> 22539 <bitWidth>1</bitWidth> 22540 <access>read-only</access> 22541 </field> 22542 </fields> 22543 </register> 22544 <register> 22545 <name>POWER</name> 22546 <description>Power management register.</description> 22547 <addressOffset>0x01</addressOffset> 22548 <size>8</size> 22549 <fields> 22550 <field> 22551 <name>EN_SUSPENDM</name> 22552 <description>Enable SUSPENDM signal.</description> 22553 <bitOffset>0</bitOffset> 22554 <bitWidth>1</bitWidth> 22555 <access>read-write</access> 22556 </field> 22557 <field> 22558 <name>SUSPEND</name> 22559 <description>Suspend mode detected.</description> 22560 <bitOffset>1</bitOffset> 22561 <bitWidth>1</bitWidth> 22562 <access>read-only</access> 22563 </field> 22564 <field> 22565 <name>RESUME</name> 22566 <description>Generate resume signaling.</description> 22567 <bitOffset>2</bitOffset> 22568 <bitWidth>1</bitWidth> 22569 <access>read-write</access> 22570 </field> 22571 <field> 22572 <name>RESET</name> 22573 <description>Bus reset detected.</description> 22574 <bitOffset>3</bitOffset> 22575 <bitWidth>1</bitWidth> 22576 <access>read-only</access> 22577 </field> 22578 <field> 22579 <name>HS_MODE</name> 22580 <description>High-speed mode detected.</description> 22581 <bitOffset>4</bitOffset> 22582 <bitWidth>1</bitWidth> 22583 <access>read-only</access> 22584 </field> 22585 <field> 22586 <name>HS_ENABLE</name> 22587 <description>High-speed mode enable.</description> 22588 <bitOffset>5</bitOffset> 22589 <bitWidth>1</bitWidth> 22590 <access>read-write</access> 22591 </field> 22592 <field> 22593 <name>SOFTCONN</name> 22594 <description>Softconn.</description> 22595 <bitOffset>6</bitOffset> 22596 <bitWidth>1</bitWidth> 22597 <access>read-write</access> 22598 </field> 22599 <field> 22600 <name>ISO_UPDATE</name> 22601 <description>Wait for SOF during Isochronous xfers.</description> 22602 <bitOffset>7</bitOffset> 22603 <bitWidth>1</bitWidth> 22604 <access>read-write</access> 22605 </field> 22606 </fields> 22607 </register> 22608 <register> 22609 <name>INTRIN</name> 22610 <description>Interrupt register for EP0 and IN EP1-15.</description> 22611 <addressOffset>0x02</addressOffset> 22612 <size>16</size> 22613 <fields> 22614 <field> 22615 <name>EP15_IN_INT</name> 22616 <description>Endpoint 15 interrupt.</description> 22617 <bitOffset>15</bitOffset> 22618 <bitWidth>1</bitWidth> 22619 <access>read-only</access> 22620 </field> 22621 <field> 22622 <name>EP14_IN_INT</name> 22623 <description>Endpoint 14 interrupt.</description> 22624 <bitOffset>14</bitOffset> 22625 <bitWidth>1</bitWidth> 22626 <access>read-only</access> 22627 </field> 22628 <field> 22629 <name>EP13_IN_INT</name> 22630 <description>Endpoint 13 interrupt.</description> 22631 <bitOffset>13</bitOffset> 22632 <bitWidth>1</bitWidth> 22633 <access>read-only</access> 22634 </field> 22635 <field> 22636 <name>EP12_IN_INT</name> 22637 <description>Endpoint 12 interrupt.</description> 22638 <bitOffset>12</bitOffset> 22639 <bitWidth>1</bitWidth> 22640 <access>read-only</access> 22641 </field> 22642 <field> 22643 <name>EP11_IN_INT</name> 22644 <description>Endpoint 11 interrupt.</description> 22645 <bitOffset>11</bitOffset> 22646 <bitWidth>1</bitWidth> 22647 <access>read-only</access> 22648 </field> 22649 <field> 22650 <name>EP10_IN_INT</name> 22651 <description>Endpoint 10 interrupt.</description> 22652 <bitOffset>10</bitOffset> 22653 <bitWidth>1</bitWidth> 22654 <access>read-only</access> 22655 </field> 22656 <field> 22657 <name>EP9_IN_INT</name> 22658 <description>Endpoint 9 interrupt.</description> 22659 <bitOffset>9</bitOffset> 22660 <bitWidth>1</bitWidth> 22661 <access>read-only</access> 22662 </field> 22663 <field> 22664 <name>EP8_IN_INT</name> 22665 <description>Endpoint 8 interrupt.</description> 22666 <bitOffset>8</bitOffset> 22667 <bitWidth>1</bitWidth> 22668 <access>read-only</access> 22669 </field> 22670 <field> 22671 <name>EP7_IN_INT</name> 22672 <description>Endpoint 7 interrupt.</description> 22673 <bitOffset>7</bitOffset> 22674 <bitWidth>1</bitWidth> 22675 <access>read-only</access> 22676 </field> 22677 <field> 22678 <name>EP6_IN_INT</name> 22679 <description>Endpoint 6 interrupt.</description> 22680 <bitOffset>6</bitOffset> 22681 <bitWidth>1</bitWidth> 22682 <access>read-only</access> 22683 </field> 22684 <field> 22685 <name>EP5_IN_INT</name> 22686 <description>Endpoint 5 interrupt.</description> 22687 <bitOffset>5</bitOffset> 22688 <bitWidth>1</bitWidth> 22689 <access>read-only</access> 22690 </field> 22691 <field> 22692 <name>EP4_IN_INT</name> 22693 <description>Endpoint 4 interrupt.</description> 22694 <bitOffset>4</bitOffset> 22695 <bitWidth>1</bitWidth> 22696 <access>read-only</access> 22697 </field> 22698 <field> 22699 <name>EP3_IN_INT</name> 22700 <description>Endpoint 3 interrupt.</description> 22701 <bitOffset>3</bitOffset> 22702 <bitWidth>1</bitWidth> 22703 <access>read-only</access> 22704 </field> 22705 <field> 22706 <name>EP2_IN_INT</name> 22707 <description>Endpoint 2 interrupt.</description> 22708 <bitOffset>2</bitOffset> 22709 <bitWidth>1</bitWidth> 22710 <access>read-only</access> 22711 </field> 22712 <field> 22713 <name>EP1_IN_INT</name> 22714 <description>Endpoint 1 interrupt.</description> 22715 <bitOffset>1</bitOffset> 22716 <bitWidth>1</bitWidth> 22717 <access>read-only</access> 22718 </field> 22719 <field> 22720 <name>EP0_IN_INT</name> 22721 <description>Endpoint 0 interrupt.</description> 22722 <bitOffset>0</bitOffset> 22723 <bitWidth>1</bitWidth> 22724 <access>read-only</access> 22725 </field> 22726 </fields> 22727 </register> 22728 <register> 22729 <name>INTROUT</name> 22730 <description>Interrupt register for OUT EP 1-15.</description> 22731 <addressOffset>0x04</addressOffset> 22732 <size>16</size> 22733 <fields> 22734 <field> 22735 <name>EP15_OUT_INT</name> 22736 <description>Endpoint 15 interrupt.</description> 22737 <bitOffset>15</bitOffset> 22738 <bitWidth>1</bitWidth> 22739 <access>read-only</access> 22740 </field> 22741 <field> 22742 <name>EP14_OUT_INT</name> 22743 <description>Endpoint 14 interrupt.</description> 22744 <bitOffset>14</bitOffset> 22745 <bitWidth>1</bitWidth> 22746 <access>read-only</access> 22747 </field> 22748 <field> 22749 <name>EP13_OUT_INT</name> 22750 <description>Endpoint 13 interrupt.</description> 22751 <bitOffset>13</bitOffset> 22752 <bitWidth>1</bitWidth> 22753 <access>read-only</access> 22754 </field> 22755 <field> 22756 <name>EP12_OUT_INT</name> 22757 <description>Endpoint 12 interrupt.</description> 22758 <bitOffset>12</bitOffset> 22759 <bitWidth>1</bitWidth> 22760 <access>read-only</access> 22761 </field> 22762 <field> 22763 <name>EP11_OUT_INT</name> 22764 <description>Endpoint 11 interrupt.</description> 22765 <bitOffset>11</bitOffset> 22766 <bitWidth>1</bitWidth> 22767 <access>read-only</access> 22768 </field> 22769 <field> 22770 <name>EP10_OUT_INT</name> 22771 <description>Endpoint 10 interrupt.</description> 22772 <bitOffset>10</bitOffset> 22773 <bitWidth>1</bitWidth> 22774 <access>read-only</access> 22775 </field> 22776 <field> 22777 <name>EP9_OUT_INT</name> 22778 <description>Endpoint 9 interrupt.</description> 22779 <bitOffset>9</bitOffset> 22780 <bitWidth>1</bitWidth> 22781 <access>read-only</access> 22782 </field> 22783 <field> 22784 <name>EP8_OUT_INT</name> 22785 <description>Endpoint 8 interrupt.</description> 22786 <bitOffset>8</bitOffset> 22787 <bitWidth>1</bitWidth> 22788 <access>read-only</access> 22789 </field> 22790 <field> 22791 <name>EP7_OUT_INT</name> 22792 <description>Endpoint 7 interrupt.</description> 22793 <bitOffset>7</bitOffset> 22794 <bitWidth>1</bitWidth> 22795 <access>read-only</access> 22796 </field> 22797 <field> 22798 <name>EP6_OUT_INT</name> 22799 <description>Endpoint 6 interrupt.</description> 22800 <bitOffset>6</bitOffset> 22801 <bitWidth>1</bitWidth> 22802 <access>read-only</access> 22803 </field> 22804 <field> 22805 <name>EP5_OUT_INT</name> 22806 <description>Endpoint 5 interrupt.</description> 22807 <bitOffset>5</bitOffset> 22808 <bitWidth>1</bitWidth> 22809 <access>read-only</access> 22810 </field> 22811 <field> 22812 <name>EP4_OUT_INT</name> 22813 <description>Endpoint 4 interrupt.</description> 22814 <bitOffset>4</bitOffset> 22815 <bitWidth>1</bitWidth> 22816 <access>read-only</access> 22817 </field> 22818 <field> 22819 <name>EP3_OUT_INT</name> 22820 <description>Endpoint 3 interrupt.</description> 22821 <bitOffset>3</bitOffset> 22822 <bitWidth>1</bitWidth> 22823 <access>read-only</access> 22824 </field> 22825 <field> 22826 <name>EP2_OUT_INT</name> 22827 <description>Endpoint 2 interrupt.</description> 22828 <bitOffset>2</bitOffset> 22829 <bitWidth>1</bitWidth> 22830 <access>read-only</access> 22831 </field> 22832 <field> 22833 <name>EP1_OUT_INT</name> 22834 <description>Endpoint 1 interrupt.</description> 22835 <bitOffset>1</bitOffset> 22836 <bitWidth>1</bitWidth> 22837 <access>read-only</access> 22838 </field> 22839 </fields> 22840 </register> 22841 <register> 22842 <name>INTRINEN</name> 22843 <description>Interrupt enable for EP 0 and IN EP 1-15.</description> 22844 <addressOffset>0x06</addressOffset> 22845 <size>16</size> 22846 <fields> 22847 <field> 22848 <name>EP15_IN_INT_EN</name> 22849 <description>Endpoint 15 interrupt enable.</description> 22850 <bitOffset>15</bitOffset> 22851 <bitWidth>1</bitWidth> 22852 <access>read-write</access> 22853 </field> 22854 <field> 22855 <name>EP14_IN_INT_EN</name> 22856 <description>Endpoint 14 interrupt enable.</description> 22857 <bitOffset>14</bitOffset> 22858 <bitWidth>1</bitWidth> 22859 <access>read-write</access> 22860 </field> 22861 <field> 22862 <name>EP13_IN_INT_EN</name> 22863 <description>Endpoint 13 interrupt enable.</description> 22864 <bitOffset>13</bitOffset> 22865 <bitWidth>1</bitWidth> 22866 <access>read-write</access> 22867 </field> 22868 <field> 22869 <name>EP12_IN_INT_EN</name> 22870 <description>Endpoint 12 interrupt enable.</description> 22871 <bitOffset>12</bitOffset> 22872 <bitWidth>1</bitWidth> 22873 <access>read-write</access> 22874 </field> 22875 <field> 22876 <name>EP11_IN_INT_EN</name> 22877 <description>Endpoint 11 interrupt enable.</description> 22878 <bitOffset>11</bitOffset> 22879 <bitWidth>1</bitWidth> 22880 <access>read-write</access> 22881 </field> 22882 <field> 22883 <name>EP10_IN_INT_EN</name> 22884 <description>Endpoint 10 interrupt enable.</description> 22885 <bitOffset>10</bitOffset> 22886 <bitWidth>1</bitWidth> 22887 <access>read-write</access> 22888 </field> 22889 <field> 22890 <name>EP9_IN_INT_EN</name> 22891 <description>Endpoint 9 interrupt enable.</description> 22892 <bitOffset>9</bitOffset> 22893 <bitWidth>1</bitWidth> 22894 <access>read-write</access> 22895 </field> 22896 <field> 22897 <name>EP8_IN_INT_EN</name> 22898 <description>Endpoint 8 interrupt enable.</description> 22899 <bitOffset>8</bitOffset> 22900 <bitWidth>1</bitWidth> 22901 <access>read-write</access> 22902 </field> 22903 <field> 22904 <name>EP7_IN_INT_EN</name> 22905 <description>Endpoint 7 interrupt enable.</description> 22906 <bitOffset>7</bitOffset> 22907 <bitWidth>1</bitWidth> 22908 <access>read-write</access> 22909 </field> 22910 <field> 22911 <name>EP6_IN_INT_EN</name> 22912 <description>Endpoint 6 interrupt enable.</description> 22913 <bitOffset>6</bitOffset> 22914 <bitWidth>1</bitWidth> 22915 <access>read-write</access> 22916 </field> 22917 <field> 22918 <name>EP5_IN_INT_EN</name> 22919 <description>Endpoint 5 interrupt enable.</description> 22920 <bitOffset>5</bitOffset> 22921 <bitWidth>1</bitWidth> 22922 <access>read-write</access> 22923 </field> 22924 <field> 22925 <name>EP4_IN_INT_EN</name> 22926 <description>Endpoint 4 interrupt enable.</description> 22927 <bitOffset>4</bitOffset> 22928 <bitWidth>1</bitWidth> 22929 <access>read-write</access> 22930 </field> 22931 <field> 22932 <name>EP3_IN_INT_EN</name> 22933 <description>Endpoint 3 interrupt enable.</description> 22934 <bitOffset>3</bitOffset> 22935 <bitWidth>1</bitWidth> 22936 <access>read-write</access> 22937 </field> 22938 <field> 22939 <name>EP2_IN_INT_EN</name> 22940 <description>Endpoint 2 interrupt enable.</description> 22941 <bitOffset>2</bitOffset> 22942 <bitWidth>1</bitWidth> 22943 <access>read-write</access> 22944 </field> 22945 <field> 22946 <name>EP1_IN_INT_EN</name> 22947 <description>Endpoint 1 interrupt enable.</description> 22948 <bitOffset>1</bitOffset> 22949 <bitWidth>1</bitWidth> 22950 <access>read-write</access> 22951 </field> 22952 <field> 22953 <name>EP0_INT_EN</name> 22954 <description>Endpoint 0 interrupt enable.</description> 22955 <bitOffset>0</bitOffset> 22956 <bitWidth>1</bitWidth> 22957 <access>read-write</access> 22958 </field> 22959 </fields> 22960 </register> 22961 <register> 22962 <name>INTROUTEN</name> 22963 <description>Interrupt enable for OUT EP 1-15.</description> 22964 <addressOffset>0x08</addressOffset> 22965 <size>16</size> 22966 <fields> 22967 <field> 22968 <name>EP15_OUT_INT_EN</name> 22969 <description>Endpoint 15 interrupt.</description> 22970 <bitOffset>15</bitOffset> 22971 <bitWidth>1</bitWidth> 22972 <access>read-write</access> 22973 </field> 22974 <field> 22975 <name>EP14_OUT_INT_EN</name> 22976 <description>Endpoint 14 interrupt.</description> 22977 <bitOffset>14</bitOffset> 22978 <bitWidth>1</bitWidth> 22979 <access>read-write</access> 22980 </field> 22981 <field> 22982 <name>EP13_OUT_INT_EN</name> 22983 <description>Endpoint 13 interrupt.</description> 22984 <bitOffset>13</bitOffset> 22985 <bitWidth>1</bitWidth> 22986 <access>read-write</access> 22987 </field> 22988 <field> 22989 <name>EP12_OUT_INT_EN</name> 22990 <description>Endpoint 12 interrupt.</description> 22991 <bitOffset>12</bitOffset> 22992 <bitWidth>1</bitWidth> 22993 <access>read-write</access> 22994 </field> 22995 <field> 22996 <name>EP11_OUT_INT_EN</name> 22997 <description>Endpoint 11 interrupt.</description> 22998 <bitOffset>11</bitOffset> 22999 <bitWidth>1</bitWidth> 23000 <access>read-write</access> 23001 </field> 23002 <field> 23003 <name>EP10_OUT_INT_EN</name> 23004 <description>Endpoint 10 interrupt.</description> 23005 <bitOffset>10</bitOffset> 23006 <bitWidth>1</bitWidth> 23007 <access>read-write</access> 23008 </field> 23009 <field> 23010 <name>EP9_OUT_INT_EN</name> 23011 <description>Endpoint 9 interrupt.</description> 23012 <bitOffset>9</bitOffset> 23013 <bitWidth>1</bitWidth> 23014 <access>read-write</access> 23015 </field> 23016 <field> 23017 <name>EP8_OUT_INT_EN</name> 23018 <description>Endpoint 8 interrupt.</description> 23019 <bitOffset>8</bitOffset> 23020 <bitWidth>1</bitWidth> 23021 <access>read-write</access> 23022 </field> 23023 <field> 23024 <name>EP7_OUT_INT_EN</name> 23025 <description>Endpoint 7 interrupt.</description> 23026 <bitOffset>7</bitOffset> 23027 <bitWidth>1</bitWidth> 23028 <access>read-write</access> 23029 </field> 23030 <field> 23031 <name>EP6_OUT_INT_EN</name> 23032 <description>Endpoint 6 interrupt.</description> 23033 <bitOffset>6</bitOffset> 23034 <bitWidth>1</bitWidth> 23035 <access>read-write</access> 23036 </field> 23037 <field> 23038 <name>EP5_OUT_INT_EN</name> 23039 <description>Endpoint 5 interrupt.</description> 23040 <bitOffset>5</bitOffset> 23041 <bitWidth>1</bitWidth> 23042 <access>read-write</access> 23043 </field> 23044 <field> 23045 <name>EP4_OUT_INT_EN</name> 23046 <description>Endpoint 4 interrupt.</description> 23047 <bitOffset>4</bitOffset> 23048 <bitWidth>1</bitWidth> 23049 <access>read-write</access> 23050 </field> 23051 <field> 23052 <name>EP3_OUT_INT_EN</name> 23053 <description>Endpoint 3 interrupt.</description> 23054 <bitOffset>3</bitOffset> 23055 <bitWidth>1</bitWidth> 23056 <access>read-write</access> 23057 </field> 23058 <field> 23059 <name>EP2_OUT_INT_EN</name> 23060 <description>Endpoint 2 interrupt.</description> 23061 <bitOffset>2</bitOffset> 23062 <bitWidth>1</bitWidth> 23063 <access>read-write</access> 23064 </field> 23065 <field> 23066 <name>EP1_OUT_INT_EN</name> 23067 <description>Endpoint 1 interrupt.</description> 23068 <bitOffset>1</bitOffset> 23069 <bitWidth>1</bitWidth> 23070 <access>read-write</access> 23071 </field> 23072 </fields> 23073 </register> 23074 <register> 23075 <name>INTRUSB</name> 23076 <description>Interrupt register for common USB interrupts.</description> 23077 <addressOffset>0x0A</addressOffset> 23078 <size>8</size> 23079 <fields> 23080 <field> 23081 <name>SOF_INT</name> 23082 <description>Start of Frame.</description> 23083 <bitOffset>3</bitOffset> 23084 <bitWidth>1</bitWidth> 23085 <access>read-only</access> 23086 </field> 23087 <field> 23088 <name>RESET_INT</name> 23089 <description>Bus reset detected.</description> 23090 <bitOffset>2</bitOffset> 23091 <bitWidth>1</bitWidth> 23092 <access>read-only</access> 23093 </field> 23094 <field> 23095 <name>RESUME_INT</name> 23096 <description>Resume detected.</description> 23097 <bitOffset>1</bitOffset> 23098 <bitWidth>1</bitWidth> 23099 <access>read-only</access> 23100 </field> 23101 <field> 23102 <name>SUSPEND_INT</name> 23103 <description>Suspend detected.</description> 23104 <bitOffset>0</bitOffset> 23105 <bitWidth>1</bitWidth> 23106 <access>read-only</access> 23107 </field> 23108 </fields> 23109 </register> 23110 <register> 23111 <name>INTRUSBEN</name> 23112 <description>Interrupt enable for common USB interrupts.</description> 23113 <addressOffset>0x0B</addressOffset> 23114 <size>8</size> 23115 <fields> 23116 <field> 23117 <name>SOF_INT_EN</name> 23118 <description>Start of Frame.</description> 23119 <bitOffset>3</bitOffset> 23120 <bitWidth>1</bitWidth> 23121 <access>read-write</access> 23122 </field> 23123 <field> 23124 <name>RESET_INT_EN</name> 23125 <description>Bus reset detected.</description> 23126 <bitOffset>2</bitOffset> 23127 <bitWidth>1</bitWidth> 23128 <access>read-write</access> 23129 </field> 23130 <field> 23131 <name>RESUME_INT_EN</name> 23132 <description>Resume detected.</description> 23133 <bitOffset>1</bitOffset> 23134 <bitWidth>1</bitWidth> 23135 <access>read-write</access> 23136 </field> 23137 <field> 23138 <name>SUSPEND_INT_EN</name> 23139 <description>Suspend detected.</description> 23140 <bitOffset>0</bitOffset> 23141 <bitWidth>1</bitWidth> 23142 <access>read-write</access> 23143 </field> 23144 </fields> 23145 </register> 23146 <register> 23147 <name>FRAME</name> 23148 <description>Frame number.</description> 23149 <addressOffset>0x0C</addressOffset> 23150 <size>16</size> 23151 <fields> 23152 <field> 23153 <name>FRAMENUM</name> 23154 <description>Read the last received frame number, that is the 11-bit frame number received in the SOF packet.</description> 23155 <bitOffset>0</bitOffset> 23156 <bitWidth>11</bitWidth> 23157 <access>read-only</access> 23158 </field> 23159 </fields> 23160 </register> 23161 <register> 23162 <name>INDEX</name> 23163 <description>Index for banked registers.</description> 23164 <addressOffset>0x0E</addressOffset> 23165 <size>8</size> 23166 <fields> 23167 <field> 23168 <name>INDEX</name> 23169 <description>Index Register Access Selector. </description> 23170 <bitOffset>0</bitOffset> 23171 <bitWidth>4</bitWidth> 23172 <access>read-write</access> 23173 </field> 23174 </fields> 23175 </register> 23176 <register> 23177 <name>TESTMODE</name> 23178 <description>USB 2.0 test mode enable register.</description> 23179 <addressOffset>0x0F</addressOffset> 23180 <size>8</size> 23181 <fields> 23182 <field> 23183 <name>FORCE_FS</name> 23184 <description>Force USB to Full-speed after reset.</description> 23185 <bitOffset>5</bitOffset> 23186 <bitWidth>1</bitWidth> 23187 <access>read-write</access> 23188 </field> 23189 <field> 23190 <name>FORCE_HS</name> 23191 <description>Force USB to High-speed after reset.</description> 23192 <bitOffset>4</bitOffset> 23193 <bitWidth>1</bitWidth> 23194 <access>read-write</access> 23195 </field> 23196 <field> 23197 <name>TEST_PKT</name> 23198 <description>Transmit fixed test packet.</description> 23199 <bitOffset>3</bitOffset> 23200 <bitWidth>1</bitWidth> 23201 <access>read-write</access> 23202 </field> 23203 <field> 23204 <name>TEST_K</name> 23205 <description>Force USB to continuous K state.</description> 23206 <bitOffset>2</bitOffset> 23207 <bitWidth>1</bitWidth> 23208 <access>read-write</access> 23209 </field> 23210 <field> 23211 <name>TEST_J</name> 23212 <description>Force USB to continuous J state.</description> 23213 <bitOffset>1</bitOffset> 23214 <bitWidth>1</bitWidth> 23215 <access>read-write</access> 23216 </field> 23217 <field> 23218 <name>TEST_SE0_NAK</name> 23219 <description>Respond to any valid IN token with NAK.</description> 23220 <bitOffset>0</bitOffset> 23221 <bitWidth>1</bitWidth> 23222 <access>read-write</access> 23223 </field> 23224 </fields> 23225 </register> 23226 <register> 23227 <name>INMAXP</name> 23228 <description>Maximum packet size for INx endpoint (x == INDEX).</description> 23229 <addressOffset>0x10</addressOffset> 23230 <size>16</size> 23231 <fields> 23232 <field> 23233 <name>MAXPACKETSIZE</name> 23234 <description>Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9</description> 23235 <bitOffset>0</bitOffset> 23236 <bitWidth>11</bitWidth> 23237 </field> 23238 <field> 23239 <name>NUMPACKMINUS1</name> 23240 <description>Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. </description> 23241 <bitOffset>11</bitOffset> 23242 <bitWidth>5</bitWidth> 23243 </field> 23244 </fields> 23245 </register> 23246 <register> 23247 <name>CSR0</name> 23248 <description>Control status register for EP 0 (when INDEX == 0).</description> 23249 <addressOffset>0x12</addressOffset> 23250 <size>8</size> 23251 <fields> 23252 <field> 23253 <name>SERV_SETUP_END</name> 23254 <description>Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set </description> 23255 <bitOffset>7</bitOffset> 23256 <bitWidth>1</bitWidth> 23257 <access>read-write</access> 23258 </field> 23259 <field> 23260 <name>SERV_OUTPKTRDY</name> 23261 <description>Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set.</description> 23262 <bitOffset>6</bitOffset> 23263 <bitWidth>1</bitWidth> 23264 <access>read-write</access> 23265 </field> 23266 <field> 23267 <name>SEND_STALL</name> 23268 <description>Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. </description> 23269 <bitOffset>5</bitOffset> 23270 <bitWidth>1</bitWidth> 23271 <access>read-write</access> 23272 </field> 23273 <field> 23274 <name>SETUP_END</name> 23275 <description>Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear.</description> 23276 <bitOffset>4</bitOffset> 23277 <bitWidth>1</bitWidth> 23278 <access>read-only</access> 23279 </field> 23280 <field> 23281 <name>DATA_END</name> 23282 <description>Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. </description> 23283 <bitOffset>3</bitOffset> 23284 <bitWidth>1</bitWidth> 23285 <access>read-write</access> 23286 </field> 23287 <field> 23288 <name>SENT_STALL</name> 23289 <description> Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. </description> 23290 <bitOffset>2</bitOffset> 23291 <bitWidth>1</bitWidth> 23292 <access>read-write</access> 23293 </field> 23294 <field> 23295 <name>INPKTRDY</name> 23296 <description>EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. </description> 23297 <bitOffset>1</bitOffset> 23298 <bitWidth>1</bitWidth> 23299 <access>read-write</access> 23300 </field> 23301 <field> 23302 <name>OUTPKTRDY</name> 23303 <description>EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. </description> 23304 <bitOffset>0</bitOffset> 23305 <bitWidth>1</bitWidth> 23306 <access>read-only</access> 23307 </field> 23308 </fields> 23309 </register> 23310 <register> 23311 <name>INCSRL</name> 23312 <description>Control status lower register for INx endpoint (x == INDEX).</description> 23313 <alternateRegister>CSR0</alternateRegister> 23314 <addressOffset>0x12</addressOffset> 23315 <size>8</size> 23316 <fields> 23317 <field> 23318 <name>INCOMPTX</name> 23319 <description>Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear.</description> 23320 <bitOffset>7</bitOffset> 23321 <bitWidth>1</bitWidth> 23322 <access>read-write</access> 23323 </field> 23324 <field> 23325 <name>CLRDATATOG</name> 23326 <description>Write 1 to clear IN endpoint data-toggle to 0.</description> 23327 <bitOffset>6</bitOffset> 23328 <bitWidth>1</bitWidth> 23329 <access>read-write</access> 23330 </field> 23331 <field> 23332 <name>SENTSTALL</name> 23333 <description>Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear.</description> 23334 <bitOffset>5</bitOffset> 23335 <bitWidth>1</bitWidth> 23336 <access>read-write</access> 23337 </field> 23338 <field> 23339 <name>SENDSTALL</name> 23340 <description>Send STALL Handshake.</description> 23341 <bitOffset>4</bitOffset> 23342 <bitWidth>1</bitWidth> 23343 <access>read-only</access> 23344 <enumeratedValues> 23345 <enumeratedValue> 23346 <name>terminate</name> 23347 <description>Terminate STALL handhsake</description> 23348 <value>0</value> 23349 </enumeratedValue> 23350 <enumeratedValue> 23351 <name>respond</name> 23352 <description>Respond to an IN token with a STALL handshake</description> 23353 <value>1</value> 23354 </enumeratedValue> 23355 </enumeratedValues> 23356 </field> 23357 <field> 23358 <name>FLUSHFIFO</name> 23359 <description>Flush Next Packet from IN FIFO. Write 1 to clear</description> 23360 <bitOffset>3</bitOffset> 23361 <bitWidth>1</bitWidth> 23362 <access>read-write</access> 23363 </field> 23364 <field> 23365 <name>UNDERRUN</name> 23366 <description>Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear</description> 23367 <bitOffset>2</bitOffset> 23368 <bitWidth>1</bitWidth> 23369 <access>read-write</access> 23370 </field> 23371 <field> 23372 <name>FIFONOTEMPTY</name> 23373 <description>Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. </description> 23374 <bitOffset>1</bitOffset> 23375 <bitWidth>1</bitWidth> 23376 <access>read-write</access> 23377 </field> 23378 <field> 23379 <name>INPKTRDY</name> 23380 <description>IN Packet Ready. Write a 1 to clear </description> 23381 <bitOffset>0</bitOffset> 23382 <bitWidth>1</bitWidth> 23383 <access>read-only</access> 23384 </field> 23385 </fields> 23386 </register> 23387 <register> 23388 <name>INCSRU</name> 23389 <description>Control status upper register for INx endpoint (x == INDEX).</description> 23390 <addressOffset>0x13</addressOffset> 23391 <size>8</size> 23392 <fields> 23393 <field> 23394 <name>AUTOSET</name> 23395 <description>Auto Set inpktrdy. </description> 23396 <bitOffset>7</bitOffset> 23397 <bitWidth>1</bitWidth> 23398 <access>read-write</access> 23399 <enumeratedValues> 23400 <enumeratedValue> 23401 <name>set</name> 23402 <description>USBHS_INCSRL_inpktrdy must be set by firmware.</description> 23403 <value>0</value> 23404 </enumeratedValue> 23405 <enumeratedValue> 23406 <name>auto</name> 23407 <description>USBHS_INCSRL_inpktrdy is automatically set. </description> 23408 <value>1</value> 23409 </enumeratedValue> 23410 </enumeratedValues> 23411 </field> 23412 <field> 23413 <name>ISO</name> 23414 <description>Isochronous Transfer Enable</description> 23415 <bitOffset>6</bitOffset> 23416 <bitWidth>1</bitWidth> 23417 <access>read-write</access> 23418 <enumeratedValues> 23419 <enumeratedValue> 23420 <name>interrupt</name> 23421 <description>Enable IN Bulk and IN interrupt transfers.</description> 23422 <value>0</value> 23423 </enumeratedValue> 23424 <enumeratedValue> 23425 <name>isochronous</name> 23426 <description>Enable IN Isochronous transfers. </description> 23427 <value>1</value> 23428 </enumeratedValue> 23429 </enumeratedValues> 23430 </field> 23431 <field> 23432 <name>MODE</name> 23433 <description> Endpoint Direction Mode.</description> 23434 <bitOffset>5</bitOffset> 23435 <bitWidth>1</bitWidth> 23436 <access>read-write</access> 23437 <enumeratedValues> 23438 <enumeratedValue> 23439 <name>out</name> 23440 <description>Endpoint direction is OUT.</description> 23441 <value>0</value> 23442 </enumeratedValue> 23443 <enumeratedValue> 23444 <name>in</name> 23445 <description>Endpoint direction is IN. </description> 23446 <value>1</value> 23447 </enumeratedValue> 23448 </enumeratedValues> 23449 </field> 23450 <field> 23451 <name>DMAREQEN</name> 23452 <description> DMA Request Enable </description> 23453 <bitOffset>4</bitOffset> 23454 <bitWidth>1</bitWidth> 23455 <access>read-write</access> 23456 <enumeratedValues> 23457 <enumeratedValue> 23458 <name>dis</name> 23459 <description>Disable DMA for this IN endpoint.</description> 23460 <value>0</value> 23461 </enumeratedValue> 23462 <enumeratedValue> 23463 <name>en</name> 23464 <description>Enable DMA for this IN endpoint.</description> 23465 <value>1</value> 23466 </enumeratedValue> 23467 </enumeratedValues> 23468 </field> 23469 <field> 23470 <name>FRCDATATOG</name> 23471 <description> Force In Data - Toggle</description> 23472 <bitOffset>3</bitOffset> 23473 <bitWidth>1</bitWidth> 23474 <access>read-write</access> 23475 <enumeratedValues> 23476 <enumeratedValue> 23477 <name>received</name> 23478 <description>Toggle data-toglge only when an ACK is received.</description> 23479 <value>0</value> 23480 </enumeratedValue> 23481 <enumeratedValue> 23482 <name>dontcare</name> 23483 <description>Toggle data-toggle regardless of ACK. </description> 23484 <value>1</value> 23485 </enumeratedValue> 23486 </enumeratedValues> 23487 </field> 23488 <field> 23489 <name>DMAREQMODE</name> 23490 <description> DMA Request Mode Enable </description> 23491 <bitOffset>2</bitOffset> 23492 <bitWidth>1</bitWidth> 23493 <access>read-write</access> 23494 <enumeratedValues> 23495 <enumeratedValue> 23496 <name>0</name> 23497 <description>Enable DMA Request Mode 0.</description> 23498 <value>0</value> 23499 </enumeratedValue> 23500 <enumeratedValue> 23501 <name>1</name> 23502 <description>Enable DMA Request Mode 1.</description> 23503 <value>1</value> 23504 </enumeratedValue> 23505 </enumeratedValues> 23506 </field> 23507 <field> 23508 <name>DPKTBUFDIS</name> 23509 <description> Double Packet Buffering Disable </description> 23510 <bitOffset>1</bitOffset> 23511 <bitWidth>1</bitWidth> 23512 <access>read-write</access> 23513 <enumeratedValues> 23514 <enumeratedValue> 23515 <name>en</name> 23516 <description>Enable Double packet buffering.</description> 23517 <value>0</value> 23518 </enumeratedValue> 23519 <enumeratedValue> 23520 <name>dis</name> 23521 <description>Disable Double Packet Buffering.</description> 23522 <value>1</value> 23523 </enumeratedValue> 23524 </enumeratedValues> 23525 </field> 23526 </fields> 23527 </register> 23528 <register> 23529 <name>OUTMAXP</name> 23530 <description>Maximum packet size for OUTx endpoint (x == INDEX).</description> 23531 <addressOffset>0x14</addressOffset> 23532 <size>16</size> 23533 <fields> 23534 <field> 23535 <name>NUMPACKMINUS1</name> 23536 <description>Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. </description> 23537 <bitOffset>11</bitOffset> 23538 <bitWidth>5</bitWidth> 23539 </field> 23540 <field> 23541 <name>MAXPACKETSIZE</name> 23542 <description>Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9.</description> 23543 <bitOffset>0</bitOffset> 23544 <bitWidth>11</bitWidth> 23545 </field> 23546 </fields> 23547 </register> 23548 <register> 23549 <name>OUTCSRL</name> 23550 <description>Control status lower register for OUTx endpoint (x == INDEX).</description> 23551 <addressOffset>0x16</addressOffset> 23552 <size>8</size> 23553 <fields> 23554 <field> 23555 <name>CLRDATATOG</name> 23556 <bitOffset>7</bitOffset> 23557 <bitWidth>1</bitWidth> 23558 <access>read-write</access> 23559 </field> 23560 <field> 23561 <name>SENTSTALL</name> 23562 <bitOffset>6</bitOffset> 23563 <bitWidth>1</bitWidth> 23564 <access>read-write</access> 23565 </field> 23566 <field> 23567 <name>SENDSTALL</name> 23568 <bitOffset>5</bitOffset> 23569 <bitWidth>1</bitWidth> 23570 <access>read-write</access> 23571 </field> 23572 <field> 23573 <name>FLUSHFIFO</name> 23574 <bitOffset>4</bitOffset> 23575 <bitWidth>1</bitWidth> 23576 <access>read-write</access> 23577 </field> 23578 <field> 23579 <name>DATAERROR</name> 23580 <bitOffset>3</bitOffset> 23581 <bitWidth>1</bitWidth> 23582 <access>read-only</access> 23583 </field> 23584 <field> 23585 <name>OVERRUN</name> 23586 <bitOffset>2</bitOffset> 23587 <bitWidth>1</bitWidth> 23588 <access>read-write</access> 23589 </field> 23590 <field> 23591 <name>FIFOFULL</name> 23592 <bitOffset>1</bitOffset> 23593 <bitWidth>1</bitWidth> 23594 <access>read-only</access> 23595 </field> 23596 <field> 23597 <name>OUTPKTRDY</name> 23598 <bitOffset>0</bitOffset> 23599 <bitWidth>1</bitWidth> 23600 <access>read-write</access> 23601 </field> 23602 </fields> 23603 </register> 23604 <register> 23605 <name>OUTCSRU</name> 23606 <description>Control status upper register for OUTx endpoint (x == INDEX).</description> 23607 <addressOffset>0x17</addressOffset> 23608 <size>8</size> 23609 <fields> 23610 <field> 23611 <name>AUTOCLEAR</name> 23612 <bitOffset>7</bitOffset> 23613 <bitWidth>1</bitWidth> 23614 <access>read-write</access> 23615 </field> 23616 <field> 23617 <name>ISO</name> 23618 <bitOffset>6</bitOffset> 23619 <bitWidth>1</bitWidth> 23620 <access>read-write</access> 23621 </field> 23622 <field> 23623 <name>DMAREQEN</name> 23624 <bitOffset>5</bitOffset> 23625 <bitWidth>1</bitWidth> 23626 <access>read-write</access> 23627 </field> 23628 <field> 23629 <name>DISNYET</name> 23630 <bitOffset>4</bitOffset> 23631 <bitWidth>1</bitWidth> 23632 <access>read-write</access> 23633 </field> 23634 <field> 23635 <name>DMAREQMODE</name> 23636 <bitOffset>3</bitOffset> 23637 <bitWidth>1</bitWidth> 23638 <access>read-write</access> 23639 </field> 23640 <field> 23641 <name>DPKTBUFDIS</name> 23642 <bitOffset>1</bitOffset> 23643 <bitWidth>1</bitWidth> 23644 <access>read-write</access> 23645 </field> 23646 <field> 23647 <name>INCOMPRX</name> 23648 <bitOffset>0</bitOffset> 23649 <bitWidth>1</bitWidth> 23650 <access>read-only</access> 23651 </field> 23652 </fields> 23653 </register> 23654 <register> 23655 <name>COUNT0</name> 23656 <description>Number of received bytes in EP 0 FIFO (INDEX == 0).</description> 23657 <addressOffset>0x18</addressOffset> 23658 <size>16</size> 23659 <fields> 23660 <field> 23661 <name>COUNT0</name> 23662 <description>Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 </description> 23663 <bitOffset>0</bitOffset> 23664 <bitWidth>7</bitWidth> 23665 <access>read-only</access> 23666 </field> 23667 </fields> 23668 </register> 23669 <register> 23670 <name>OUTCOUNT</name> 23671 <description>Number of received bytes in OUT EPx FIFO (x == INDEX).</description> 23672 <alternateRegister>COUNT0</alternateRegister> 23673 <addressOffset>0x18</addressOffset> 23674 <size>16</size> 23675 <fields> 23676 <field> 23677 <name>OUTCOUNT</name> 23678 <description>Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. </description> 23679 <bitOffset>0</bitOffset> 23680 <bitWidth>13</bitWidth> 23681 <access>read-only</access> 23682 </field> 23683 </fields> 23684 </register> 23685 <register> 23686 <name>FIFO0</name> 23687 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23688 <addressOffset>0x20</addressOffset> 23689 <fields> 23690 <field> 23691 <name>USBHS_FIFO0</name> 23692 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23693 <bitOffset>0</bitOffset> 23694 <bitWidth>32</bitWidth> 23695 </field> 23696 </fields> 23697 </register> 23698 <register> 23699 <name>FIFO1</name> 23700 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23701 <addressOffset>0x24</addressOffset> 23702 <fields> 23703 <field> 23704 <name>USBHS_FIFO1</name> 23705 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23706 <bitOffset>0</bitOffset> 23707 <bitWidth>32</bitWidth> 23708 </field> 23709 </fields> 23710 </register> 23711 <register> 23712 <name>FIFO2</name> 23713 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23714 <addressOffset>0x28</addressOffset> 23715 <fields> 23716 <field> 23717 <name>USBHS_FIFO2</name> 23718 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23719 <bitOffset>0</bitOffset> 23720 <bitWidth>32</bitWidth> 23721 </field> 23722 </fields> 23723 </register> 23724 <register> 23725 <name>FIFO3</name> 23726 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23727 <addressOffset>0x2c</addressOffset> 23728 <fields> 23729 <field> 23730 <name>USBHS_FIFO3</name> 23731 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23732 <bitOffset>0</bitOffset> 23733 <bitWidth>32</bitWidth> 23734 </field> 23735 </fields> 23736 </register> 23737 <register> 23738 <name>FIFO4</name> 23739 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23740 <addressOffset>0x30</addressOffset> 23741 <fields> 23742 <field> 23743 <name>USBHS_FIFO4</name> 23744 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23745 <bitOffset>0</bitOffset> 23746 <bitWidth>32</bitWidth> 23747 </field> 23748 </fields> 23749 </register> 23750 <register> 23751 <name>FIFO5</name> 23752 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23753 <addressOffset>0x34</addressOffset> 23754 <fields> 23755 <field> 23756 <name>USBHS_FIFO5</name> 23757 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23758 <bitOffset>0</bitOffset> 23759 <bitWidth>32</bitWidth> 23760 </field> 23761 </fields> 23762 </register> 23763 <register> 23764 <name>FIFO6</name> 23765 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23766 <addressOffset>0x38</addressOffset> 23767 <fields> 23768 <field> 23769 <name>USBHS_FIFO6</name> 23770 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23771 <bitOffset>0</bitOffset> 23772 <bitWidth>32</bitWidth> 23773 </field> 23774 </fields> 23775 </register> 23776 <register> 23777 <name>FIFO7</name> 23778 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23779 <addressOffset>0x3c</addressOffset> 23780 <fields> 23781 <field> 23782 <name>USBHS_FIFO7</name> 23783 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23784 <bitOffset>0</bitOffset> 23785 <bitWidth>32</bitWidth> 23786 </field> 23787 </fields> 23788 </register> 23789 <register> 23790 <name>FIFO8</name> 23791 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23792 <addressOffset>0x40</addressOffset> 23793 <fields> 23794 <field> 23795 <name>USBHS_FIFO8</name> 23796 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23797 <bitOffset>0</bitOffset> 23798 <bitWidth>32</bitWidth> 23799 </field> 23800 </fields> 23801 </register> 23802 <register> 23803 <name>FIFO9</name> 23804 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23805 <addressOffset>0x44</addressOffset> 23806 <fields> 23807 <field> 23808 <name>USBHS_FIFO9</name> 23809 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23810 <bitOffset>0</bitOffset> 23811 <bitWidth>32</bitWidth> 23812 </field> 23813 </fields> 23814 </register> 23815 <register> 23816 <name>FIFO10</name> 23817 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23818 <addressOffset>0x48</addressOffset> 23819 <fields> 23820 <field> 23821 <name>USBHS_FIFO10</name> 23822 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23823 <bitOffset>0</bitOffset> 23824 <bitWidth>32</bitWidth> 23825 </field> 23826 </fields> 23827 </register> 23828 <register> 23829 <name>FIFO11</name> 23830 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23831 <addressOffset>0x4c</addressOffset> 23832 <fields> 23833 <field> 23834 <name>USBHS_FIFO11</name> 23835 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23836 <bitOffset>0</bitOffset> 23837 <bitWidth>32</bitWidth> 23838 </field> 23839 </fields> 23840 </register> 23841 <register> 23842 <name>FIFO12</name> 23843 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23844 <addressOffset>0x50</addressOffset> 23845 <fields> 23846 <field> 23847 <name>USBHS_FIFO12</name> 23848 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23849 <bitOffset>0</bitOffset> 23850 <bitWidth>32</bitWidth> 23851 </field> 23852 </fields> 23853 </register> 23854 <register> 23855 <name>FIFO13</name> 23856 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23857 <addressOffset>0x54</addressOffset> 23858 <fields> 23859 <field> 23860 <name>USBHS_FIFO13</name> 23861 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23862 <bitOffset>0</bitOffset> 23863 <bitWidth>32</bitWidth> 23864 </field> 23865 </fields> 23866 </register> 23867 <register> 23868 <name>FIFO14</name> 23869 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23870 <addressOffset>0x58</addressOffset> 23871 <fields> 23872 <field> 23873 <name>USBHS_FIFO14</name> 23874 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23875 <bitOffset>0</bitOffset> 23876 <bitWidth>32</bitWidth> 23877 </field> 23878 </fields> 23879 </register> 23880 <register> 23881 <name>FIFO15</name> 23882 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 23883 <addressOffset>0x5c</addressOffset> 23884 <fields> 23885 <field> 23886 <name>USBHS_FIFO15</name> 23887 <description>USBHS Endpoint FIFO Read/Write Register.</description> 23888 <bitOffset>0</bitOffset> 23889 <bitWidth>32</bitWidth> 23890 </field> 23891 </fields> 23892 </register> 23893 <register> 23894 <name>HWVERS</name> 23895 <description>HWVERS</description> 23896 <addressOffset>0x6c</addressOffset> 23897 <size>16</size> 23898 <fields> 23899 <field> 23900 <name>USBHS_HWVERS</name> 23901 <description>USBHS Register.</description> 23902 <bitOffset>0</bitOffset> 23903 <bitWidth>16</bitWidth> 23904 </field> 23905 </fields> 23906 </register> 23907 <register> 23908 <name>EPINFO</name> 23909 <description>Endpoint hardware information.</description> 23910 <addressOffset>0x78</addressOffset> 23911 <size>8</size> 23912 <fields> 23913 <field> 23914 <name>OUTENDPOINTS</name> 23915 <bitOffset>4</bitOffset> 23916 <bitWidth>4</bitWidth> 23917 <access>read-only</access> 23918 </field> 23919 <field> 23920 <name>INTENDPOINTS</name> 23921 <bitOffset>0</bitOffset> 23922 <bitWidth>4</bitWidth> 23923 <access>read-only</access> 23924 </field> 23925 </fields> 23926 </register> 23927 <register> 23928 <name>RAMINFO</name> 23929 <description>RAM width and DMA hardware information.</description> 23930 <addressOffset>0x79</addressOffset> 23931 <size>8</size> 23932 <fields> 23933 <field> 23934 <name>DMACHANS</name> 23935 <bitOffset>4</bitOffset> 23936 <bitWidth>4</bitWidth> 23937 <access>read-only</access> 23938 </field> 23939 <field> 23940 <name>RAMBITS</name> 23941 <bitOffset>0</bitOffset> 23942 <bitWidth>4</bitWidth> 23943 <access>read-only</access> 23944 </field> 23945 </fields> 23946 </register> 23947 <register> 23948 <name>SOFTRESET</name> 23949 <description>Software reset register.</description> 23950 <addressOffset>0x7A</addressOffset> 23951 <size>8</size> 23952 <fields> 23953 <field> 23954 <name>RSTXS</name> 23955 <bitOffset>1</bitOffset> 23956 <bitWidth>1</bitWidth> 23957 <access>read-write</access> 23958 </field> 23959 <field> 23960 <name>RSTS</name> 23961 <bitOffset>0</bitOffset> 23962 <bitWidth>1</bitWidth> 23963 <access>read-write</access> 23964 </field> 23965 </fields> 23966 </register> 23967 <register> 23968 <name>EARLYDMA</name> 23969 <description>DMA timing control register.</description> 23970 <addressOffset>0x7B</addressOffset> 23971 <size>8</size> 23972 <fields> 23973 <field> 23974 <name>EDMAIN</name> 23975 <bitOffset>1</bitOffset> 23976 <bitWidth>1</bitWidth> 23977 <access>read-write</access> 23978 </field> 23979 <field> 23980 <name>EDMAOUT</name> 23981 <bitOffset>0</bitOffset> 23982 <bitWidth>1</bitWidth> 23983 <access>read-write</access> 23984 </field> 23985 </fields> 23986 </register> 23987 <register> 23988 <name>CTUCH</name> 23989 <description>Chirp timeout timer setting.</description> 23990 <addressOffset>0x80</addressOffset> 23991 <size>16</size> 23992 <fields> 23993 <field> 23994 <name>C_T_UCH</name> 23995 <description>HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. </description> 23996 <bitOffset>0</bitOffset> 23997 <bitWidth>16</bitWidth> 23998 </field> 23999 </fields> 24000 </register> 24001 <register> 24002 <name>CTHSRTN</name> 24003 <description>Sets delay between HS resume to UTM normal operating mode.</description> 24004 <addressOffset>0x82</addressOffset> 24005 <size>16</size> 24006 <fields> 24007 <field> 24008 <name>C_T_HSTRN</name> 24009 <description>High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.</description> 24010 <bitOffset>0</bitOffset> 24011 <bitWidth>16</bitWidth> 24012 </field> 24013 </fields> 24014 </register> 24015 <register> 24016 <name>MXM_USB_REG_00</name> 24017 <description>MXM_USB_REG_00</description> 24018 <addressOffset>0x400</addressOffset> 24019 </register> 24020 <register> 24021 <name>M31_PHY_UTMI_RESET</name> 24022 <description>M31_PHY_UTMI_RESET</description> 24023 <addressOffset>0x404</addressOffset> 24024 </register> 24025 <register> 24026 <name>M31_PHY_UTMI_VCONTROL</name> 24027 <description>M31_PHY_UTMI_VCONTROL</description> 24028 <addressOffset>0x408</addressOffset> 24029 </register> 24030 <register> 24031 <name>M31_PHY_CLK_EN</name> 24032 <description>M31_PHY_CLK_EN</description> 24033 <addressOffset>0x40C</addressOffset> 24034 </register> 24035 <register> 24036 <name>M31_PHY_PONRST</name> 24037 <description>M31_PHY_PONRST</description> 24038 <addressOffset>0x410</addressOffset> 24039 </register> 24040 <register> 24041 <name>M31_PHY_NONCRY_RSTB</name> 24042 <description>M31_PHY_NONCRY_RSTB</description> 24043 <addressOffset>0x414</addressOffset> 24044 </register> 24045 <register> 24046 <name>M31_PHY_NONCRY_EN</name> 24047 <description>M31_PHY_NONCRY_EN</description> 24048 <addressOffset>0x418</addressOffset> 24049 </register> 24050 <register> 24051 <name>M31_PHY_U2_COMPLIANCE_EN</name> 24052 <description>M31_PHY_U2_COMPLIANCE_EN</description> 24053 <addressOffset>0x420</addressOffset> 24054 </register> 24055 <register> 24056 <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ</name> 24057 <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ</description> 24058 <addressOffset>0x424</addressOffset> 24059 </register> 24060 <register> 24061 <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</name> 24062 <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</description> 24063 <addressOffset>0x428</addressOffset> 24064 </register> 24065 <register> 24066 <name>M31_PHY_CLK_RDY</name> 24067 <description>M31_PHY_CLK_RDY</description> 24068 <addressOffset>0x42C</addressOffset> 24069 </register> 24070 <register> 24071 <name>M31_PHY_PLL_EN</name> 24072 <description>M31_PHY_PLL_EN</description> 24073 <addressOffset>0x430</addressOffset> 24074 </register> 24075 <register> 24076 <name>M31_PHY_BIST_OK</name> 24077 <description>M31_PHY_BIST_OK</description> 24078 <addressOffset>0x434</addressOffset> 24079 </register> 24080 <register> 24081 <name>M31_PHY_DATA_OE</name> 24082 <description>M31_PHY_DATA_OE</description> 24083 <addressOffset>0x438</addressOffset> 24084 </register> 24085 <register> 24086 <name>M31_PHY_OSCOUTEN</name> 24087 <description>M31_PHY_OSCOUTEN</description> 24088 <addressOffset>0x43C</addressOffset> 24089 </register> 24090 <register> 24091 <name>M31_PHY_LPM_ALIVE</name> 24092 <description>M31_PHY_LPM_ALIVE</description> 24093 <addressOffset>0x440</addressOffset> 24094 </register> 24095 <register> 24096 <name>M31_PHY_HS_BIST_MODE</name> 24097 <description>M31_PHY_HS_BIST_MODE</description> 24098 <addressOffset>0x444</addressOffset> 24099 </register> 24100 <register> 24101 <name>M31_PHY_CORECLKIN</name> 24102 <description>M31_PHY_CORECLKIN</description> 24103 <addressOffset>0x448</addressOffset> 24104 </register> 24105 <register> 24106 <name>M31_PHY_XTLSEL</name> 24107 <description>M31_PHY_XTLSEL</description> 24108 <addressOffset>0x44C</addressOffset> 24109 </register> 24110 <register> 24111 <name>M31_PHY_LS_EN</name> 24112 <description>M31_PHY_LS_EN</description> 24113 <addressOffset>0x450</addressOffset> 24114 </register> 24115 <register> 24116 <name>M31_PHY_DEBUG_SEL</name> 24117 <description>M31_PHY_DEBUG_SEL</description> 24118 <addressOffset>0x454</addressOffset> 24119 </register> 24120 <register> 24121 <name>M31_PHY_DEBUG_OUT</name> 24122 <description>M31_PHY_DEBUG_OUT</description> 24123 <addressOffset>0x458</addressOffset> 24124 </register> 24125 <register> 24126 <name>M31_PHY_OUTCLKSEL</name> 24127 <description>M31_PHY_OUTCLKSEL</description> 24128 <addressOffset>0x45C</addressOffset> 24129 </register> 24130 <register> 24131 <name>M31_PHY_XCFGI_31_0</name> 24132 <description>M31_PHY_XCFGI_31_0</description> 24133 <addressOffset>0x460</addressOffset> 24134 </register> 24135 <register> 24136 <name>M31_PHY_XCFGI_63_32</name> 24137 <description>M31_PHY_XCFGI_63_32</description> 24138 <addressOffset>0x464</addressOffset> 24139 </register> 24140 <register> 24141 <name>M31_PHY_XCFGI_95_64</name> 24142 <description>M31_PHY_XCFGI_95_64</description> 24143 <addressOffset>0x468</addressOffset> 24144 </register> 24145 <register> 24146 <name>M31_PHY_XCFGI_127_96</name> 24147 <description>M31_PHY_XCFGI_127_96</description> 24148 <addressOffset>0x46C</addressOffset> 24149 </register> 24150 <register> 24151 <name>M31_PHY_XCFGI_137_128</name> 24152 <description>M31_PHY_XCFGI_137_128</description> 24153 <addressOffset>0x470</addressOffset> 24154 </register> 24155 <register> 24156 <name>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</name> 24157 <description>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</description> 24158 <addressOffset>0x474</addressOffset> 24159 </register> 24160 <register> 24161 <name>M31_PHY_XCFG_HS_FINE_TUNE_NUM</name> 24162 <description>M31_PHY_XCFG_HS_FINE_TUNE_NUM</description> 24163 <addressOffset>0x478</addressOffset> 24164 </register> 24165 <register> 24166 <name>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</name> 24167 <description>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</description> 24168 <addressOffset>0x47C</addressOffset> 24169 </register> 24170 <register> 24171 <name>M31_PHY_XCFG_FS_FINE_TUNE_NUM</name> 24172 <description>M31_PHY_XCFG_FS_FINE_TUNE_NUM</description> 24173 <addressOffset>0x480</addressOffset> 24174 </register> 24175 <register> 24176 <name>M31_PHY_XCFG_LOCK_RANGE_MAX</name> 24177 <description>M31_PHY_XCFG_LOCK_RANGE_MAX</description> 24178 <addressOffset>0x484</addressOffset> 24179 </register> 24180 <register> 24181 <name>M31_PHY_XCFGI_LOCK_RANGE_MIN</name> 24182 <description>M31_PHY_XCFGI_LOCK_RANGE_MIN</description> 24183 <addressOffset>0x488</addressOffset> 24184 </register> 24185 <register> 24186 <name>M31_PHY_XCFG_OB_RSEL</name> 24187 <description>M31_PHY_XCFG_OB_RSEL</description> 24188 <addressOffset>0x48C</addressOffset> 24189 </register> 24190 <register> 24191 <name>M31_PHY_XCFG_OC_RSEL</name> 24192 <description>M31_PHY_XCFG_OC_RSEL</description> 24193 <addressOffset>0x490</addressOffset> 24194 </register> 24195 <register> 24196 <name>M31_PHY_XCFGO</name> 24197 <description>M31_PHY_XCFGO</description> 24198 <addressOffset>0x494</addressOffset> 24199 </register> 24200 <register> 24201 <name>MXM_INT</name> 24202 <description>USB Added Maxim Interrupt Flag Register.</description> 24203 <addressOffset>0x498</addressOffset> 24204 <fields> 24205 <field> 24206 <name>VBUS</name> 24207 <description>VBUS</description> 24208 <bitOffset>0</bitOffset> 24209 <bitWidth>1</bitWidth> 24210 </field> 24211 <field> 24212 <name>NOVBUS</name> 24213 <description>NOVBUS</description> 24214 <bitOffset>1</bitOffset> 24215 <bitWidth>1</bitWidth> 24216 </field> 24217 </fields> 24218 </register> 24219 <register> 24220 <name>MXM_INT_EN</name> 24221 <description>USB Added Maxim Interrupt Enable Register.</description> 24222 <addressOffset>0x49C</addressOffset> 24223 <fields> 24224 <field> 24225 <name>VBUS</name> 24226 <description>VBUS</description> 24227 <bitOffset>0</bitOffset> 24228 <bitWidth>1</bitWidth> 24229 </field> 24230 <field> 24231 <name>NOVBUS</name> 24232 <description>NOVBUS</description> 24233 <bitOffset>1</bitOffset> 24234 <bitWidth>1</bitWidth> 24235 </field> 24236 </fields> 24237 </register> 24238 <register> 24239 <name>MXM_SUSPEND</name> 24240 <description>USB Added Maxim Suspend Register.</description> 24241 <addressOffset>0x4A0</addressOffset> 24242 <fields> 24243 <field> 24244 <name>SEL</name> 24245 <description>Suspend register</description> 24246 <bitOffset>0</bitOffset> 24247 <bitWidth>1</bitWidth> 24248 </field> 24249 </fields> 24250 </register> 24251 <register> 24252 <name>MXM_REG_A4</name> 24253 <description>USB Added Maxim Power Status Register</description> 24254 <addressOffset>0x4A4</addressOffset> 24255 <fields> 24256 <field> 24257 <name>VRST_VDDB_N_A</name> 24258 <description>VRST_VDDB_N_A</description> 24259 <bitOffset>0</bitOffset> 24260 <bitWidth>1</bitWidth> 24261 </field> 24262 <field> 24263 <name>DMA_INT</name> 24264 <description>DMA_INT</description> 24265 <bitOffset>1</bitOffset> 24266 <bitWidth>1</bitWidth> 24267 </field> 24268 </fields> 24269 </register> 24270 </registers> 24271 </peripheral> 24272<!--USBHS USB 2.0 High-speed Controller.--> 24273 <peripheral> 24274 <name>WDT0</name> 24275 <description>Watchdog Timer 0</description> 24276 <baseAddress>0x40003000</baseAddress> 24277 <addressBlock> 24278 <offset>0x00</offset> 24279 <size>0x0400</size> 24280 <usage>registers</usage> 24281 </addressBlock> 24282 <interrupt> 24283 <name>WDT0</name> 24284 <value>1</value> 24285 </interrupt> 24286 <registers> 24287 <register> 24288 <name>CTRL</name> 24289 <description>Watchdog Timer Control Register.</description> 24290 <addressOffset>0x00</addressOffset> 24291 <resetMask>0x7FFFF000</resetMask> 24292 <fields> 24293 <field> 24294 <name>INT_PERIOD</name> 24295 <description>Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 24296 <bitOffset>0</bitOffset> 24297 <bitWidth>4</bitWidth> 24298 <enumeratedValues> 24299 <enumeratedValue> 24300 <name>wdt2pow31</name> 24301 <description>2**31 clock cycles.</description> 24302 <value>0</value> 24303 </enumeratedValue> 24304 <enumeratedValue> 24305 <name>wdt2pow30</name> 24306 <description>2**30 clock cycles.</description> 24307 <value>1</value> 24308 </enumeratedValue> 24309 <enumeratedValue> 24310 <name>wdt2pow29</name> 24311 <description>2**29 clock cycles.</description> 24312 <value>2</value> 24313 </enumeratedValue> 24314 <enumeratedValue> 24315 <name>wdt2pow28</name> 24316 <description>2**28 clock cycles.</description> 24317 <value>3</value> 24318 </enumeratedValue> 24319 <enumeratedValue> 24320 <name>wdt2pow27</name> 24321 <description>2^27 clock cycles.</description> 24322 <value>4</value> 24323 </enumeratedValue> 24324 <enumeratedValue> 24325 <name>wdt2pow26</name> 24326 <description>2**26 clock cycles.</description> 24327 <value>5</value> 24328 </enumeratedValue> 24329 <enumeratedValue> 24330 <name>wdt2pow25</name> 24331 <description>2**25 clock cycles.</description> 24332 <value>6</value> 24333 </enumeratedValue> 24334 <enumeratedValue> 24335 <name>wdt2pow24</name> 24336 <description>2**24 clock cycles.</description> 24337 <value>7</value> 24338 </enumeratedValue> 24339 <enumeratedValue> 24340 <name>wdt2pow23</name> 24341 <description>2**23 clock cycles.</description> 24342 <value>8</value> 24343 </enumeratedValue> 24344 <enumeratedValue> 24345 <name>wdt2pow22</name> 24346 <description>2**22 clock cycles.</description> 24347 <value>9</value> 24348 </enumeratedValue> 24349 <enumeratedValue> 24350 <name>wdt2pow21</name> 24351 <description>2**21 clock cycles.</description> 24352 <value>10</value> 24353 </enumeratedValue> 24354 <enumeratedValue> 24355 <name>wdt2pow20</name> 24356 <description>2**20 clock cycles.</description> 24357 <value>11</value> 24358 </enumeratedValue> 24359 <enumeratedValue> 24360 <name>wdt2pow19</name> 24361 <description>2**19 clock cycles.</description> 24362 <value>12</value> 24363 </enumeratedValue> 24364 <enumeratedValue> 24365 <name>wdt2pow18</name> 24366 <description>2**18 clock cycles.</description> 24367 <value>13</value> 24368 </enumeratedValue> 24369 <enumeratedValue> 24370 <name>wdt2pow17</name> 24371 <description>2**17 clock cycles.</description> 24372 <value>14</value> 24373 </enumeratedValue> 24374 <enumeratedValue> 24375 <name>wdt2pow16</name> 24376 <description>2**16 clock cycles.</description> 24377 <value>15</value> 24378 </enumeratedValue> 24379 </enumeratedValues> 24380 </field> 24381 <field> 24382 <name>RST_PERIOD</name> 24383 <description>Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 24384 <bitOffset>4</bitOffset> 24385 <bitWidth>4</bitWidth> 24386 <enumeratedValues> 24387 <enumeratedValue> 24388 <name>wdt2pow31</name> 24389 <description>2**31 clock cycles.</description> 24390 <value>0</value> 24391 </enumeratedValue> 24392 <enumeratedValue> 24393 <name>wdt2pow30</name> 24394 <description>2**30 clock cycles.</description> 24395 <value>1</value> 24396 </enumeratedValue> 24397 <enumeratedValue> 24398 <name>wdt2pow29</name> 24399 <description>2**29 clock cycles.</description> 24400 <value>2</value> 24401 </enumeratedValue> 24402 <enumeratedValue> 24403 <name>wdt2pow28</name> 24404 <description>2**28 clock cycles.</description> 24405 <value>3</value> 24406 </enumeratedValue> 24407 <enumeratedValue> 24408 <name>wdt2pow27</name> 24409 <description>2^27 clock cycles.</description> 24410 <value>4</value> 24411 </enumeratedValue> 24412 <enumeratedValue> 24413 <name>wdt2pow26</name> 24414 <description>2**26 clock cycles.</description> 24415 <value>5</value> 24416 </enumeratedValue> 24417 <enumeratedValue> 24418 <name>wdt2pow25</name> 24419 <description>2**25 clock cycles.</description> 24420 <value>6</value> 24421 </enumeratedValue> 24422 <enumeratedValue> 24423 <name>wdt2pow24</name> 24424 <description>2**24 clock cycles.</description> 24425 <value>7</value> 24426 </enumeratedValue> 24427 <enumeratedValue> 24428 <name>wdt2pow23</name> 24429 <description>2**23 clock cycles.</description> 24430 <value>8</value> 24431 </enumeratedValue> 24432 <enumeratedValue> 24433 <name>wdt2pow22</name> 24434 <description>2**22 clock cycles.</description> 24435 <value>9</value> 24436 </enumeratedValue> 24437 <enumeratedValue> 24438 <name>wdt2pow21</name> 24439 <description>2**21 clock cycles.</description> 24440 <value>10</value> 24441 </enumeratedValue> 24442 <enumeratedValue> 24443 <name>wdt2pow20</name> 24444 <description>2**20 clock cycles.</description> 24445 <value>11</value> 24446 </enumeratedValue> 24447 <enumeratedValue> 24448 <name>wdt2pow19</name> 24449 <description>2**19 clock cycles.</description> 24450 <value>12</value> 24451 </enumeratedValue> 24452 <enumeratedValue> 24453 <name>wdt2pow18</name> 24454 <description>2**18 clock cycles.</description> 24455 <value>13</value> 24456 </enumeratedValue> 24457 <enumeratedValue> 24458 <name>wdt2pow17</name> 24459 <description>2**17 clock cycles.</description> 24460 <value>14</value> 24461 </enumeratedValue> 24462 <enumeratedValue> 24463 <name>wdt2pow16</name> 24464 <description>2**16 clock cycles.</description> 24465 <value>15</value> 24466 </enumeratedValue> 24467 </enumeratedValues> 24468 </field> 24469 <field> 24470 <name>WDT_EN</name> 24471 <description>Watchdog Timer Enable.</description> 24472 <bitOffset>8</bitOffset> 24473 <bitWidth>1</bitWidth> 24474 <enumeratedValues> 24475 <enumeratedValue> 24476 <name>dis</name> 24477 <description>Disable.</description> 24478 <value>0</value> 24479 </enumeratedValue> 24480 <enumeratedValue> 24481 <name>en</name> 24482 <description>Enable.</description> 24483 <value>1</value> 24484 </enumeratedValue> 24485 </enumeratedValues> 24486 </field> 24487 <field> 24488 <name>INT_FLAG</name> 24489 <description>Watchdog Timer Interrupt Flag.</description> 24490 <bitOffset>9</bitOffset> 24491 <bitWidth>1</bitWidth> 24492 <modifiedWriteValues>oneToClear</modifiedWriteValues> 24493 <enumeratedValues> 24494 <enumeratedValue> 24495 <name>inactive</name> 24496 <description>No interrupt is pending.</description> 24497 <value>0</value> 24498 </enumeratedValue> 24499 <enumeratedValue> 24500 <name>pending</name> 24501 <description>An interrupt is pending.</description> 24502 <value>1</value> 24503 </enumeratedValue> 24504 </enumeratedValues> 24505 </field> 24506 <field> 24507 <name>INT_EN</name> 24508 <description>Watchdog Timer Interrupt Enable.</description> 24509 <bitOffset>10</bitOffset> 24510 <bitWidth>1</bitWidth> 24511 <enumeratedValues> 24512 <enumeratedValue> 24513 <name>dis</name> 24514 <description>Disable.</description> 24515 <value>0</value> 24516 </enumeratedValue> 24517 <enumeratedValue> 24518 <name>en</name> 24519 <description>Enable.</description> 24520 <value>1</value> 24521 </enumeratedValue> 24522 </enumeratedValues> 24523 </field> 24524 <field> 24525 <name>RST_EN</name> 24526 <description>Watchdog Timer Reset Enable.</description> 24527 <bitOffset>11</bitOffset> 24528 <bitWidth>1</bitWidth> 24529 <enumeratedValues> 24530 <enumeratedValue> 24531 <name>dis</name> 24532 <description>Disable.</description> 24533 <value>0</value> 24534 </enumeratedValue> 24535 <enumeratedValue> 24536 <name>en</name> 24537 <description>Enable.</description> 24538 <value>1</value> 24539 </enumeratedValue> 24540 </enumeratedValues> 24541 </field> 24542 <field> 24543 <name>RST_FLAG</name> 24544 <description>Watchdog Timer Reset Flag.</description> 24545 <bitOffset>31</bitOffset> 24546 <bitWidth>1</bitWidth> 24547 <enumeratedValues> 24548 <usage>read-write</usage> 24549 <enumeratedValue> 24550 <name>noEvent</name> 24551 <description>The event has not occurred.</description> 24552 <value>0</value> 24553 </enumeratedValue> 24554 <enumeratedValue> 24555 <name>occurred</name> 24556 <description>The event has occurred.</description> 24557 <value>1</value> 24558 </enumeratedValue> 24559 </enumeratedValues> 24560 </field> 24561 </fields> 24562 </register> 24563 <register> 24564 <name>RST</name> 24565 <description>Watchdog Timer Reset Register.</description> 24566 <addressOffset>0x04</addressOffset> 24567 <access>write-only</access> 24568 <fields> 24569 <field> 24570 <name>WDT_RST</name> 24571 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.</description> 24572 <bitOffset>0</bitOffset> 24573 <bitWidth>8</bitWidth> 24574 <enumeratedValues> 24575 <enumeratedValue> 24576 <name>seq0</name> 24577 <description>The first value to be written to reset the WDT.</description> 24578 <value>0x000000A5</value> 24579 </enumeratedValue> 24580 <enumeratedValue> 24581 <name>seq1</name> 24582 <description>The second value to be written to reset the WDT.</description> 24583 <value>0x0000005A</value> 24584 </enumeratedValue> 24585 </enumeratedValues> 24586 </field> 24587 </fields> 24588 </register> 24589 </registers> 24590 </peripheral> 24591<!--WDT0 Watchdog Timer 0--> 24592 <peripheral derivedFrom="WDT0"> 24593 <name>WDT1</name> 24594 <description>Watchdog Timer 0 1</description> 24595 <baseAddress>0x40003400</baseAddress> 24596 <interrupt> 24597 <name>WDT1</name> 24598 <description>WDT1 IRQ</description> 24599 <value>57</value> 24600 </interrupt> 24601 </peripheral> 24602<!--WDT1 Watchdog Timer 0 1--> 24603 </peripherals> 24604</device> 24605
