1 /** 2 * @file smon_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup smon_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SMON_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SMON_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup smon 67 * @defgroup smon_registers SMON_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 69 * @details The Security Monitor block used to monitor system threat conditions. 70 */ 71 72 /** 73 * @ingroup smon_registers 74 * Structure type to access the SMON Registers. 75 */ 76 typedef struct { 77 __IO uint32_t extscn; /**< <tt>\b 0x00:</tt> SMON EXTSCN Register */ 78 __IO uint32_t intscn; /**< <tt>\b 0x04:</tt> SMON INTSCN Register */ 79 __IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON SECALM Register */ 80 __I uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */ 81 __R uint32_t rsv_0x10_0x33[9]; 82 __I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON SECST Register */ 83 __IO uint32_t sdbe; /**< <tt>\b 0x38:</tt> SMON SDBE Register */ 84 } mxc_smon_regs_t; 85 86 /* Register offsets for module SMON */ 87 /** 88 * @ingroup smon_registers 89 * @defgroup SMON_Register_Offsets Register Offsets 90 * @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */ 98 #define MXC_R_SMON_SDBE ((uint32_t)0x00000038UL) /**< Offset from SMON Base Address: <tt> 0x0038</tt> */ 99 /**@} end of group smon_registers */ 100 101 /** 102 * @ingroup smon_registers 103 * @defgroup SMON_EXTSCN SMON_EXTSCN 104 * @brief External Sensor Control Register. 105 * @{ 106 */ 107 #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */ 108 #define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */ 109 110 #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */ 111 #define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */ 112 113 #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */ 114 #define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */ 115 116 #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */ 117 #define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */ 118 119 #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */ 120 #define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */ 121 122 #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */ 123 #define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */ 124 125 #define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */ 126 #define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */ 127 128 #define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */ 129 #define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */ 130 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */ 131 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */ 132 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */ 133 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */ 134 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */ 135 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */ 136 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */ 137 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */ 138 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */ 139 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */ 140 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */ 141 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */ 142 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */ 143 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */ 144 #define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */ 145 #define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */ 146 147 #define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */ 148 #define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */ 149 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */ 150 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */ 151 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */ 152 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */ 153 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */ 154 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */ 155 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */ 156 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */ 157 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */ 158 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */ 159 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */ 160 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */ 161 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */ 162 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */ 163 164 #define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */ 165 #define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */ 166 167 #define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */ 168 #define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */ 169 170 /**@} end of group SMON_EXTSCN_Register */ 171 172 /** 173 * @ingroup smon_registers 174 * @defgroup SMON_INTSCN SMON_INTSCN 175 * @brief Internal Sensor Control Register. 176 * @{ 177 */ 178 #define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */ 179 #define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */ 180 181 #define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */ 182 #define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */ 183 184 #define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */ 185 #define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */ 186 187 #define MXC_F_SMON_INTSCN_DFD_EN_POS 3 /**< INTSCN_DFD_EN Position */ 188 #define MXC_F_SMON_INTSCN_DFD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_EN_POS)) /**< INTSCN_DFD_EN Mask */ 189 190 #define MXC_F_SMON_INTSCN_DFD_NMI_POS 4 /**< INTSCN_DFD_NMI Position */ 191 #define MXC_F_SMON_INTSCN_DFD_NMI ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_NMI_POS)) /**< INTSCN_DFD_NMI Mask */ 192 193 #define MXC_F_SMON_INTSCN_DFD_STDBY_POS 8 /**< INTSCN_DFD_STDBY Position */ 194 #define MXC_F_SMON_INTSCN_DFD_STDBY ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_STDBY_POS)) /**< INTSCN_DFD_STDBY Mask */ 195 196 #define MXC_F_SMON_INTSCN_PUF_TRIM_ERASE_POS 10 /**< INTSCN_PUF_TRIM_ERASE Position */ 197 #define MXC_F_SMON_INTSCN_PUF_TRIM_ERASE ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_PUF_TRIM_ERASE_POS)) /**< INTSCN_PUF_TRIM_ERASE Mask */ 198 199 #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */ 200 #define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */ 201 202 #define MXC_F_SMON_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */ 203 #define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */ 204 205 #define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */ 206 #define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */ 207 208 #define MXC_F_SMON_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */ 209 #define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */ 210 211 #define MXC_F_SMON_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */ 212 #define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */ 213 214 #define MXC_F_SMON_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */ 215 #define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */ 216 217 #define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */ 218 #define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */ 219 220 /**@} end of group SMON_INTSCN_Register */ 221 222 /** 223 * @ingroup smon_registers 224 * @defgroup SMON_SECALM SMON_SECALM 225 * @brief Security Alarm Register. 226 * @{ 227 */ 228 #define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ 229 #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ 230 231 #define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ 232 #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ 233 234 #define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */ 235 #define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */ 236 237 #define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */ 238 #define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */ 239 240 #define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */ 241 #define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */ 242 243 #define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */ 244 #define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */ 245 246 #define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */ 247 #define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */ 248 249 #define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */ 250 #define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */ 251 252 #define MXC_F_SMON_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */ 253 #define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */ 254 255 #define MXC_F_SMON_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */ 256 #define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */ 257 258 #define MXC_F_SMON_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */ 259 #define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */ 260 261 #define MXC_F_SMON_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */ 262 #define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */ 263 264 #define MXC_F_SMON_SECALM_VGL_POS 12 /**< SECALM_VGL Position */ 265 #define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */ 266 267 #define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */ 268 #define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */ 269 270 #define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */ 271 #define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */ 272 273 #define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */ 274 #define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */ 275 276 #define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */ 277 #define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */ 278 279 #define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */ 280 #define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */ 281 282 #define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */ 283 #define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */ 284 285 #define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */ 286 #define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */ 287 288 #define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */ 289 #define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */ 290 291 #define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */ 292 #define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */ 293 294 #define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */ 295 #define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */ 296 297 #define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */ 298 #define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */ 299 300 #define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */ 301 #define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */ 302 303 /**@} end of group SMON_SECALM_Register */ 304 305 /** 306 * @ingroup smon_registers 307 * @defgroup SMON_SECDIAG SMON_SECDIAG 308 * @brief Security Diagnostic Register. 309 * @{ 310 */ 311 #define MXC_F_SMON_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */ 312 #define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */ 313 314 #define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */ 315 #define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */ 316 317 #define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */ 318 #define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */ 319 320 #define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */ 321 #define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */ 322 323 #define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */ 324 #define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */ 325 326 #define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */ 327 #define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */ 328 329 #define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */ 330 #define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */ 331 332 #define MXC_F_SMON_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */ 333 #define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */ 334 335 #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */ 336 #define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */ 337 338 #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */ 339 #define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */ 340 341 #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */ 342 #define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */ 343 344 #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */ 345 #define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */ 346 347 #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */ 348 #define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */ 349 350 #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */ 351 #define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */ 352 353 /**@} end of group SMON_SECDIAG_Register */ 354 355 /** 356 * @ingroup smon_registers 357 * @defgroup SMON_SECST SMON_SECST 358 * @brief Security Monitor Status Register. 359 * @{ 360 */ 361 #define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */ 362 #define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */ 363 364 #define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */ 365 #define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */ 366 367 #define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */ 368 #define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */ 369 370 /**@} end of group SMON_SECST_Register */ 371 372 /** 373 * @ingroup smon_registers 374 * @defgroup SMON_SDBE SMON_SDBE 375 * @brief Security Monitor Self Destruct Byte. 376 * @{ 377 */ 378 #define MXC_F_SMON_SDBE_DBYTE_POS 0 /**< SDBE_DBYTE Position */ 379 #define MXC_F_SMON_SDBE_DBYTE ((uint32_t)(0xFFUL << MXC_F_SMON_SDBE_DBYTE_POS)) /**< SDBE_DBYTE Mask */ 380 381 #define MXC_F_SMON_SDBE_SBDEN_POS 31 /**< SDBE_SBDEN Position */ 382 #define MXC_F_SMON_SDBE_SBDEN ((uint32_t)(0x1UL << MXC_F_SMON_SDBE_SBDEN_POS)) /**< SDBE_SBDEN Mask */ 383 384 /**@} end of group SMON_SDBE_Register */ 385 386 #ifdef __cplusplus 387 } 388 #endif 389 390 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_SMON_REGS_H_ 391
