1 /* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Domain clocks */ 12 13 /* RM0481/0492, Table 47 Kernel clock distribution summary */ 14 15 /** System clock */ 16 /* defined in stm32_common_clocks.h */ 17 /** Fixed clocks */ 18 /* Low speed clocks defined in stm32_common_clocks.h */ 19 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) 20 #define STM32_SRC_CSI (STM32_SRC_HSE + 1) 21 #define STM32_SRC_HSI (STM32_SRC_CSI + 1) 22 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) 23 /** Bus clock */ 24 #define STM32_SRC_HCLK (STM32_SRC_HSI48 + 1) 25 #define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1) 26 #define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1) 27 #define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1) 28 /** PLL outputs */ 29 #define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1) 30 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) 31 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) 32 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) 33 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) 34 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) 35 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) 36 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) 37 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) 38 /** Clock muxes */ 39 #define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1) 40 41 42 /** Bus clocks */ 43 #define STM32_CLOCK_BUS_AHB1 0x088 44 #define STM32_CLOCK_BUS_AHB2 0x08C 45 #define STM32_CLOCK_BUS_AHB4 0x094 46 #define STM32_CLOCK_BUS_APB1 0x09c 47 #define STM32_CLOCK_BUS_APB1_2 0x0A0 48 #define STM32_CLOCK_BUS_APB2 0x0A4 49 #define STM32_CLOCK_BUS_APB3 0x0A8 50 51 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 52 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 53 54 #define STM32_CLOCK_REG_MASK 0xFFU 55 #define STM32_CLOCK_REG_SHIFT 0U 56 #define STM32_CLOCK_SHIFT_MASK 0x1FU 57 #define STM32_CLOCK_SHIFT_SHIFT 8U 58 #define STM32_CLOCK_MASK_MASK 0x7U 59 #define STM32_CLOCK_MASK_SHIFT 13U 60 #define STM32_CLOCK_VAL_MASK 0x7U 61 #define STM32_CLOCK_VAL_SHIFT 16U 62 63 /** 64 * @brief STM32H5 clock configuration bit field. 65 * 66 * - reg (1/2/3/4/5) [ 0 : 7 ] 67 * - shift (0..31) [ 8 : 12 ] 68 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 69 * - val (0..7) [ 16 : 18 ] 70 * 71 * @param reg RCC_CCIPRx register offset 72 * @param shift Position within RCC_CCIPRx. 73 * @param mask Mask for the RCC_CCIPRx field. 74 * @param val Clock value (0, 1, ... 7). 75 */ 76 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 77 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 78 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 79 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 80 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 81 82 /** @brief RCC_CCIPRx register offset (RM0456.pdf) */ 83 #define CCIPR1_REG 0xD8 84 #define CCIPR2_REG 0xDC 85 #define CCIPR3_REG 0xE0 86 #define CCIPR4_REG 0xE4 87 #define CCIPR5_REG 0xE8 88 89 /** @brief RCC_BDCR register offset */ 90 #define BDCR_REG 0xF0 91 92 /** @brief RCC_CFGRx register offset */ 93 #define CFGR1_REG 0x1C 94 95 /** @brief Device domain clocks selection helpers */ 96 /** CCIPR1 devices */ 97 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR1_REG) 98 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR1_REG) 99 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR1_REG) 100 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR1_REG) 101 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR1_REG) 102 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR1_REG) 103 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 18, CCIPR1_REG) 104 #define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, CCIPR1_REG) 105 #define USART9_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR1_REG) 106 #define USART10_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 27, CCIPR1_REG) 107 #define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG) 108 109 /** CCIPR2 devices */ 110 #define USART11_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG) 111 #define USART12_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, CCIPR2_REG) 112 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG) 113 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR2_REG) 114 #define LPTIM3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR2_REG) 115 #define LPTIM4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 20, CCIPR2_REG) 116 #define LPTIM5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR2_REG) 117 #define LPTIM6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, CCIPR2_REG) 118 119 /** CCIPR3 devices */ 120 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG) 121 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR3_REG) 122 #define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR3_REG) 123 #define SPI4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR3_REG) 124 #define SPI5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG) 125 #define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR2_REG) 126 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR3_REG) 127 128 /** CCIPR4 devices */ 129 #define OCTOSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR4_REG) 130 #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR4_REG) 131 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR4_REG) 132 #define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR4_REG) 133 #define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CCIPR4_REG) 134 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR4_REG) 135 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR4_REG) 136 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR4_REG) 137 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR4_REG) 138 #define I3C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR4_REG) 139 140 /** CCIPR5 devices */ 141 #define ADCDAC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR5_REG) 142 #define DAC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 3, CCIPR5_REG) 143 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR5_REG) 144 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR5_REG) 145 #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR5_REG) 146 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR5_REG) 147 #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 19, CCIPR5_REG) 148 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR5_REG) 149 150 /** BDCR devices */ 151 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) 152 153 /** CFGR1 devices */ 154 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR1_REG) 155 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0xF, 18, CFGR1_REG) 156 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR1_REG) 157 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR1_REG) 158 159 /* MCO prescaler : division factor */ 160 #define MCO_PRE_DIV_1 1 161 #define MCO_PRE_DIV_2 2 162 #define MCO_PRE_DIV_3 3 163 #define MCO_PRE_DIV_4 4 164 #define MCO_PRE_DIV_5 5 165 #define MCO_PRE_DIV_6 6 166 #define MCO_PRE_DIV_7 7 167 #define MCO_PRE_DIV_8 8 168 #define MCO_PRE_DIV_9 9 169 #define MCO_PRE_DIV_10 10 170 #define MCO_PRE_DIV_11 11 171 #define MCO_PRE_DIV_12 12 172 #define MCO_PRE_DIV_13 13 173 #define MCO_PRE_DIV_14 14 174 #define MCO_PRE_DIV_15 15 175 176 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ */ 177
