1 /* 2 * Copyright 2021,2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ 9 10 /* Peripheral: 11 * range: 0 - 0xFF, starting from 0 12 * 13 * Instance: 14 * range: 0 - 0xFF, starting from 0 15 */ 16 #define IMX_CCM_PERIPHERAL_MASK 0xFF00UL 17 #define IMX_CCM_INSTANCE_MASK 0xFFUL 18 19 #define IMX_CCM_CORESYS_CLK 0 20 #define IMX_CCM_PLATFORM_CLK 0x1UL 21 #define IMX_CCM_BUS_CLK 0x2UL 22 23 /* LPUART */ 24 #define IMX_CCM_LPUART_CLK 0x300UL 25 #define IMX_CCM_LPUART1_CLK 0x300UL 26 #define IMX_CCM_LPUART0102_CLK 0x300UL 27 #define IMX_CCM_LPUART2_CLK 0x301UL 28 #define IMX_CCM_LPUART0304_CLK 0x301UL 29 #define IMX_CCM_LPUART3_CLK 0x302UL 30 #define IMX_CCM_LPUART0506_CLK 0x302UL 31 #define IMX_CCM_LPUART4_CLK 0x303UL 32 #define IMX_CCM_LPUART0708_CLK 0x303UL 33 #define IMX_CCM_LPUART5_CLK 0x304UL 34 #define IMX_CCM_LPUART0910_CLK 0x304UL 35 #define IMX_CCM_LPUART6_CLK 0x305UL 36 #define IMX_CCM_LPUART1112_CLK 0x305UL 37 #define IMX_CCM_LPUART7_CLK 0x306UL 38 #define IMX_CCM_LPUART8_CLK 0x307UL 39 #define IMX_CCM_LPUART9_CLK 0x308UL 40 #define IMX_CCM_LPUART10_CLK 0x309UL 41 #define IMX_CCM_LPUART11_CLK 0x30aUL 42 #define IMX_CCM_LPUART12_CLK 0x30bUL 43 44 /* LPI2C */ 45 #define IMX_CCM_LPI2C_CLK 0x400UL 46 #define IMX_CCM_LPI2C0102_CLK 0x400UL 47 #define IMX_CCM_LPI2C1_CLK 0x400UL 48 #define IMX_CCM_LPI2C2_CLK 0x401UL 49 #define IMX_CCM_LPI2C0304_CLK 0x401UL 50 #define IMX_CCM_LPI2C3_CLK 0x402UL 51 #define IMX_CCM_LPI2C4_CLK 0x403UL 52 #define IMX_CCM_LPI2C0506_CLK 0x402UL 53 #define IMX_CCM_LPI2C5_CLK 0x404UL 54 #define IMX_CCM_LPI2C6_CLK 0x405UL 55 #define IMX_CCM_LPI2C0708_CLK 0x403UL 56 #define IMX_CCM_LPI2C7_CLK 0x406UL 57 #define IMX_CCM_LPI2C8_CLK 0x407UL 58 59 /* LPSPI */ 60 #define IMX_CCM_LPSPI_CLK 0x500UL 61 #define IMX_CCM_LPSPI0102_CLK 0x500UL 62 #define IMX_CCM_LPSPI1_CLK 0x500UL 63 #define IMX_CCM_LPSPI2_CLK 0x501UL 64 #define IMX_CCM_LPSPI0304_CLK 0x501UL 65 #define IMX_CCM_LPSPI3_CLK 0x502UL 66 #define IMX_CCM_LPSPI4_CLK 0x503UL 67 #define IMX_CCM_LPSPI0506_CLK 0x502UL 68 #define IMX_CCM_LPSPI5_CLK 0x504UL 69 #define IMX_CCM_LPSPI6_CLK 0x505UL 70 #define IMX_CCM_LPSPI7_CLK 0x506UL 71 #define IMX_CCM_LPSPI8_CLK 0x507UL 72 73 /* USDHC */ 74 #define IMX_CCM_USDHC1_CLK 0x600UL 75 #define IMX_CCM_USDHC2_CLK 0x601UL 76 77 /* DMA */ 78 #define IMX_CCM_EDMA_CLK 0x700UL 79 #define IMX_CCM_EDMA_LPSR_CLK 0x701UL 80 #define IMX_CCM_EDMA3_CLK 0x700UL 81 #define IMX_CCM_EDMA4_CLK 0x701UL 82 83 /* PWM */ 84 #define IMX_CCM_PWM_CLK 0x800UL 85 86 /* CAN */ 87 #define IMX_CCM_CAN_CLK 0x900UL 88 #define IMX_CCM_CAN1_CLK 0x900UL 89 #define IMX_CCM_CAN2_CLK 0x901UL 90 #define IMX_CCM_CAN3_CLK 0x902UL 91 92 /* GPT */ 93 #define IMX_CCM_GPT_CLK 0x1000UL 94 #define IMX_CCM_GPT1_CLK 0x1000UL 95 #define IMX_CCM_GPT2_CLK 0x1001UL 96 #define IMX_CCM_GPT3_CLK 0x1002UL 97 #define IMX_CCM_GPT4_CLK 0x1003UL 98 #define IMX_CCM_GPT5_CLK 0x1004UL 99 #define IMX_CCM_GPT6_CLK 0x1005UL 100 101 /* SAI */ 102 #define IMX_CCM_SAI1_CLK 0x1100UL 103 #define IMX_CCM_SAI2_CLK 0x1101UL 104 #define IMX_CCM_SAI3_CLK 0x1102UL 105 #define IMX_CCM_SAI4_CLK 0x1103UL 106 107 /* ENET */ 108 #define IMX_CCM_ENET_CLK 0x1200UL 109 #define IMX_CCM_ENET_PLL 0x1201UL 110 #define IMX_CCM_ENET1G_CLK 0x1202UL 111 #define IMX_CCM_ENET1G_PLL 0x1203UL 112 113 /* FLEXSPI */ 114 #define IMX_CCM_FLEXSPI_CLK 0x1300UL 115 #define IMX_CCM_FLEXSPI2_CLK 0x1301UL 116 117 /* PIT */ 118 #define IMX_CCM_PIT_CLK 0x1400UL 119 #define IMX_CCM_PIT1_CLK 0x1401UL 120 121 /* ADC */ 122 #define IMX_CCM_LPADC1_CLK 0x1500UL 123 #define IMX_CCM_LPADC2_CLK 0x1501UL 124 125 /* TPM */ 126 #define IMX_CCM_TPM_CLK 0x1600UL 127 #define IMX_CCM_TPM1_CLK 0x1600UL 128 #define IMX_CCM_TPM2_CLK 0x1601UL 129 #define IMX_CCM_TPM3_CLK 0x1602UL 130 #define IMX_CCM_TPM4_CLK 0x1603UL 131 #define IMX_CCM_TPM5_CLK 0x1604UL 132 #define IMX_CCM_TPM6_CLK 0x1605UL 133 134 /* FLEXIO */ 135 #define IMX_CCM_FLEXIO_CLK 0x1700UL 136 #define IMX_CCM_FLEXIO1_CLK 0x1700UL 137 #define IMX_CCM_FLEXIO2_CLK 0x1701UL 138 139 /* NETC */ 140 #define IMX_CCM_NETC_CLK 0x1800UL 141 142 /* MIPI CSI2RX */ 143 #define IMX_CCM_MIPI_CSI2RX_ROOT_CLK 0x1900UL 144 #define IMX_CCM_MIPI_CSI2RX_UI_CLK 0x2000UL 145 #define IMX_CCM_MIPI_CSI2RX_ESC_CLK 0x2100UL 146 147 /* I3C */ 148 #define IMX_CCM_I3C_CLK 0x2200UL 149 #define IMX_CCM_I3C1_CLK 0x2200UL 150 #define IMX_CCM_I3C2_CLK 0x2201UL 151 152 /* QTMR */ 153 #define IMX_CCM_QTMR_CLK 0x6000UL 154 #define IMX_CCM_QTMR1_CLK 0x6000UL 155 #define IMX_CCM_QTMR2_CLK 0x6001UL 156 #define IMX_CCM_QTMR3_CLK 0x6002UL 157 #define IMX_CCM_QTMR4_CLK 0x6003UL 158 159 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */ 160
