1/* 2 * Copyright (c) 2019 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <xtensa/intel/intel_adsp_cavs.dtsi> 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "cdns,tensilica-xtensa-lx6"; 18 reg = <0>; 19 cpu-power-states = <&d3>; 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>; 22 }; 23 24 cpu1: cpu@1 { 25 device_type = "cpu"; 26 compatible = "cdns,tensilica-xtensa-lx6"; 27 reg = <1>; 28 cpu-power-states = <&d3>; 29 }; 30 31 cpu2: cpu@2 { 32 device_type = "cpu"; 33 compatible = "cdns,tensilica-xtensa-lx6"; 34 reg = <2>; 35 cpu-power-states = <&d3>; 36 }; 37 38 cpu3: cpu@3 { 39 device_type = "cpu"; 40 compatible = "cdns,tensilica-xtensa-lx6"; 41 reg = <3>; 42 cpu-power-states = <&d3>; 43 }; 44 45 power-states { 46 /* PM_STATE_SOFT_OFF can be entered only by calling 47 * pm_state_force. The procedure is triggered by IPC 48 * from the HOST (SET_DX). 49 */ 50 d3: off { 51 compatible = "zephyr,power-state"; 52 power-state-name = "soft-off"; 53 min-residency-us = <0>; 54 exit-latency-us = <0>; 55 status = "disabled"; 56 }; 57 }; 58 }; 59 60 sram0: memory@be000000 { 61 device_type = "memory"; 62 compatible = "mmio-sram"; 63 reg = <0xbe000000 DT_SIZE_K(2944)>; 64 }; 65 66 sram1: memory@be800000 { 67 device_type = "memory"; 68 compatible = "mmio-sram"; 69 reg = <0xbe800000 DT_SIZE_K(64)>; 70 }; 71 72 sysclk: system-clock { 73 compatible = "fixed-clock"; 74 clock-frequency = <38400000>; 75 #clock-cells = <0>; 76 }; 77 78 audioclk: audio-clock { 79 compatible = "fixed-clock"; 80 clock-frequency = <24576000>; 81 #clock-cells = <0>; 82 }; 83 84 pllclk: pll-clock { 85 compatible = "fixed-clock"; 86 clock-frequency = <96000000>; 87 #clock-cells = <0>; 88 }; 89 90 clkctl: clkctl { 91 compatible = "intel,adsp-shim-clkctl"; 92 adsp-clkctl-clk-wovcro = <0>; 93 adsp-clkctl-clk-lpro = <1>; 94 adsp-clkctl-clk-hpro = <2>; 95 adsp-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>; 96 adsp-clkctl-freq-mask = <0x10 0x20000000 0x80000000>; 97 adsp-clkctl-freq-default = <2>; 98 adsp-clkctl-freq-lowest = <0>; 99 wovcro-supported; 100 }; 101 102 IMR1: memory@b0000000 { 103 compatible = "intel,adsp-imr"; 104 reg = <0xB0000000 DT_SIZE_M(16)>; 105 block-size = <0x1000>; 106 zephyr,memory-region = "IMR1"; 107 }; 108 109 soc { 110 lsbpm: lsbpm@71d50 { 111 compatible = "intel,adsp-lsbpm"; 112 reg = <0x71d50 0x10>; 113 }; 114 115 hsbpm: hsbpm@71d10 { 116 compatible = "intel,adsp-hsbpm"; 117 reg = <0x71d10 0x10>; 118 }; 119 120 shim: shim@71f00 { 121 compatible = "intel,adsp-shim"; 122 reg = <0x71f00 0x100>; 123 }; 124 125 mem_window0: mem_window@71a00 { 126 compatible = "intel,adsp-mem-window"; 127 reg = <0x71a00 0x8>; 128 offset = <0x4000>; 129 memory = <&sram0>; 130 initialize; 131 read-only; 132 }; 133 mem_window1: mem_window@71a08 { 134 compatible = "intel,adsp-mem-window"; 135 reg = <0x71a08 0x8>; 136 memory = <&sram0>; 137 }; 138 139 mem_window2: mem_window@71a10 { 140 compatible = "intel,adsp-mem-window"; 141 reg = <0x71a10 0x8>; 142 memory = <&sram0>; 143 }; 144 145 mem_window3: mem_window@71a18 { 146 compatible = "intel,adsp-mem-window"; 147 reg = <0x71a18 0x8>; 148 memory = <&sram0>; 149 read-only; 150 }; 151 152 timer: timer { 153 compatible = "intel,adsp-timer"; 154 syscon = <&shim>; 155 }; 156 157 sspbase: ssp_base@71c00 { 158 compatible = "intel,cavs-sspbase"; 159 reg = <0x71C00 0x100>; 160 }; 161 162 l2lm: l2lm@71d00 { 163 compatible = "intel,cavs-l2lm"; 164 reg = <0x71d00 0x20>; 165 }; 166 167 core_intc: core_intc@0 { 168 compatible = "cdns,xtensa-core-intc"; 169 reg = <0x00 0x400>; 170 interrupt-controller; 171 #interrupt-cells = <3>; 172 }; 173 174 adsp_host_ipc: cavs_host_ipc@71e00 { 175 compatible = "intel,adsp-host-ipc"; 176 reg = <0x71e00 0x30>; 177 interrupts = <7 0 0>; 178 interrupt-parent = <&cavs_intc0>; 179 }; 180 181 cavs_intc0: cavs@78800 { 182 compatible = "intel,cavs-intc"; 183 reg = <0x78800 0x10>; 184 interrupt-controller; 185 #interrupt-cells = <3>; 186 interrupts = <6 0 0>; 187 interrupt-parent = <&core_intc>; 188 }; 189 190 cavs_intc1: cavs@78810 { 191 compatible = "intel,cavs-intc"; 192 reg = <0x78810 0x10>; 193 interrupt-controller; 194 #interrupt-cells = <3>; 195 interrupts = <0xA 0 0>; 196 interrupt-parent = <&core_intc>; 197 }; 198 199 cavs_intc2: cavs@78820 { 200 compatible = "intel,cavs-intc"; 201 reg = <0x78820 0x10>; 202 interrupt-controller; 203 #interrupt-cells = <3>; 204 interrupts = <0XD 0 0>; 205 interrupt-parent = <&core_intc>; 206 }; 207 208 cavs_intc3: cavs@78830 { 209 compatible = "intel,cavs-intc"; 210 reg = <0x78830 0x10>; 211 interrupt-controller; 212 #interrupt-cells = <3>; 213 interrupts = <0x10 0 0>; 214 interrupt-parent = <&core_intc>; 215 }; 216 217 adsp_idc: idc@1200 { 218 compatible = "intel,adsp-idc"; 219 reg = <0x1200 0x80>; 220 interrupts = <8 0 0>; 221 interrupt-parent = <&cavs_intc0>; 222 }; 223 224 tlb: tlb@3000 { 225 compatible = "intel,adsp-tlb"; 226 reg = <0x3000 0x1000>; 227 paddr-size = <11>; 228 }; 229 230 ssp0: ssp@77000 { 231 compatible = "intel,ssp"; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0x00077000 0x200 235 0x00078C00 0x008>; 236 interrupts = <0x01 0 0>; 237 interrupt-parent = <&cavs_intc3>; 238 dmas = <&lpgpdma0 2 239 &lpgpdma0 3>; 240 dma-names = "tx", "rx"; 241 ssp-index = <0>; 242 status = "okay"; 243 244 ssp00: ssp@0 { 245 compatible = "intel,ssp-dai"; 246 reg = <0x0>; 247 status = "okay"; 248 }; 249 }; 250 251 ssp1: ssp@77200 { 252 compatible = "intel,ssp"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 reg = <0x00077200 0x200 256 0x00078C00 0x008>; 257 interrupts = <0x01 0 0>; 258 interrupt-parent = <&cavs_intc3>; 259 dmas = <&lpgpdma0 4 260 &lpgpdma0 5>; 261 dma-names = "tx", "rx"; 262 ssp-index = <1>; 263 status = "okay"; 264 265 ssp10: ssp@10 { 266 compatible = "intel,ssp-dai"; 267 reg = <0x10>; 268 status = "okay"; 269 }; 270 }; 271 272 ssp2: ssp@77400 { 273 compatible = "intel,ssp"; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 reg = <0x00077400 0x200 277 0x00078C00 0x008>; 278 interrupts = <0x02 0 0>; 279 interrupt-parent = <&cavs_intc3>; 280 dmas = <&lpgpdma0 6 281 &lpgpdma0 7>; 282 dma-names = "tx", "rx"; 283 ssp-index = <2>; 284 status = "okay"; 285 286 ssp20: ssp@20 { 287 compatible = "intel,ssp-dai"; 288 reg = <0x20>; 289 status = "okay"; 290 }; 291 }; 292 293 ssp3: ssp@77600 { 294 compatible = "intel,ssp"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 reg = <0x00077600 0x200 298 0x00078C00 0x008>; 299 interrupts = <0x03 0 0>; 300 interrupt-parent = <&cavs_intc3>; 301 dmas = <&lpgpdma0 8 302 &lpgpdma0 9>; 303 dma-names = "tx", "rx"; 304 ssp-index = <3>; 305 status = "okay"; 306 307 ssp30: ssp@30 { 308 compatible = "intel,ssp-dai"; 309 reg = <0x30>; 310 status = "okay"; 311 }; 312 }; 313 314 ssp4: ssp@77800 { 315 compatible = "intel,ssp"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 reg = <0x00077800 0x200 319 0x00078C00 0x008>; 320 interrupts = <0x03 0 0>; 321 interrupt-parent = <&cavs_intc3>; 322 dmas = <&lpgpdma0 10 323 &lpgpdma0 11>; 324 dma-names = "tx", "rx"; 325 ssp-index = <4>; 326 status = "okay"; 327 328 ssp40: ssp@40 { 329 compatible = "intel,ssp-dai"; 330 reg = <0x40>; 331 status = "okay"; 332 }; 333 }; 334 335 ssp5: ssp@77a00 { 336 compatible = "intel,ssp"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 reg = <0x00077A00 0x200 340 0x00078C00 0x008>; 341 interrupts = <0x03 0 0>; 342 interrupt-parent = <&cavs_intc3>; 343 dmas = <&lpgpdma0 12 344 &lpgpdma0 13>; 345 dma-names = "tx", "rx"; 346 ssp-index = <5>; 347 status = "okay"; 348 349 ssp50: ssp@50 { 350 compatible = "intel,ssp-dai"; 351 reg = <0x50>; 352 status = "okay"; 353 }; 354 }; 355 356 /* 357 * FIXME this is modeling individual alh channels/instances 358 * with node labels, which has problems. A better representation 359 * is discussed here: 360 * 361 * https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009 362 */ 363 alh0: alh0@71000 { 364 compatible = "intel,alh-dai"; 365 reg = <0x00071000 0x00071200>; 366 status = "okay"; 367 }; 368 369 alh1: alh1@71000 { 370 compatible = "intel,alh-dai"; 371 reg = <0x00071000 0x00071200>; 372 status = "okay"; 373 }; 374 375 alh2: alh2@71000 { 376 compatible = "intel,alh-dai"; 377 reg = <0x00071000 0x00071200>; 378 status = "okay"; 379 }; 380 381 alh3: alh3@71000 { 382 compatible = "intel,alh-dai"; 383 reg = <0x00071000 0x00071200>; 384 status = "okay"; 385 }; 386 387 alh4: alh4@71000 { 388 compatible = "intel,alh-dai"; 389 reg = <0x00071000 0x00071200>; 390 status = "okay"; 391 }; 392 393 alh5: alh5@71000 { 394 compatible = "intel,alh-dai"; 395 reg = <0x00071000 0x00071200>; 396 status = "okay"; 397 }; 398 399 alh6: alh6@71000 { 400 compatible = "intel,alh-dai"; 401 reg = <0x00071000 0x00071200>; 402 status = "okay"; 403 }; 404 405 alh7: alh7@71000 { 406 compatible = "intel,alh-dai"; 407 reg = <0x00071000 0x00071200>; 408 status = "okay"; 409 }; 410 411 alh8: alh8@71000 { 412 compatible = "intel,alh-dai"; 413 reg = <0x00071000 0x00071200>; 414 status = "okay"; 415 }; 416 417 alh9: alh9@71000 { 418 compatible = "intel,alh-dai"; 419 reg = <0x00071000 0x00071200>; 420 status = "okay"; 421 }; 422 423 alh10: alh10@71000 { 424 compatible = "intel,alh-dai"; 425 reg = <0x00071000 0x00071200>; 426 status = "okay"; 427 }; 428 429 alh11: alh11@71000 { 430 compatible = "intel,alh-dai"; 431 reg = <0x00071000 0x00071200>; 432 status = "okay"; 433 }; 434 435 alh12: alh12@71000 { 436 compatible = "intel,alh-dai"; 437 reg = <0x00071000 0x00071200>; 438 status = "okay"; 439 }; 440 441 alh13: alh13@71000 { 442 compatible = "intel,alh-dai"; 443 reg = <0x00071000 0x00071200>; 444 status = "okay"; 445 }; 446 447 alh14: alh14@71000 { 448 compatible = "intel,alh-dai"; 449 reg = <0x00071000 0x00071200>; 450 status = "okay"; 451 }; 452 453 alh15: alh15@71000 { 454 compatible = "intel,alh-dai"; 455 reg = <0x00071000 0x00071200>; 456 status = "okay"; 457 }; 458 459 dmic0: dmic0@10000 { 460 compatible = "intel,dai-dmic"; 461 reg = <0x10000 0x8000>; 462 shim = <0x71E80>; 463 fifo = <0x0008>; 464 interrupts = <0x08 0 0>; 465 interrupt-parent = <&cavs_intc3>; 466 }; 467 468 dmic1: dmic1@10000 { 469 compatible = "intel,dai-dmic"; 470 reg = <0x10000 0x8000>; 471 shim = <0x71E80>; 472 fifo = <0x0108>; 473 interrupts = <0x09 0 0>; 474 interrupt-parent = <&cavs_intc3>; 475 }; 476 }; 477 478 hdas { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 482 hda0: hda@0 { 483 compatible = "intel,hda-dai"; 484 status = "okay"; 485 reg = <0>; 486 }; 487 hda1: hda@1 { 488 compatible = "intel,hda-dai"; 489 status = "okay"; 490 reg = <1>; 491 }; 492 hda2: hda@2 { 493 compatible = "intel,hda-dai"; 494 status = "okay"; 495 reg = <2>; 496 }; 497 hda3: hda@3 { 498 compatible = "intel,hda-dai"; 499 status = "okay"; 500 reg = <3>; 501 }; 502 hda4: hda@4 { 503 compatible = "intel,hda-dai"; 504 status = "okay"; 505 reg = <4>; 506 }; 507 hda5: hda@5 { 508 compatible = "intel,hda-dai"; 509 status = "okay"; 510 reg = <5>; 511 }; 512 hda6: hda@6 { 513 compatible = "intel,hda-dai"; 514 status = "okay"; 515 reg = <6>; 516 }; 517 hda7: hda@7 { 518 compatible = "intel,hda-dai"; 519 status = "okay"; 520 reg = <7>; 521 }; 522 hda8: hda@8 { 523 compatible = "intel,hda-dai"; 524 status = "okay"; 525 reg = <8>; 526 }; 527 hda9: hda@9 { 528 compatible = "intel,hda-dai"; 529 status = "okay"; 530 reg = <9>; 531 }; 532 hda10: hda@a { 533 compatible = "intel,hda-dai"; 534 status = "okay"; 535 reg = <0x0a>; 536 }; 537 hda11: hda@b { 538 compatible = "intel,hda-dai"; 539 status = "okay"; 540 reg = <0x0b>; 541 }; 542 hda12: hda@c { 543 compatible = "intel,hda-dai"; 544 status = "okay"; 545 reg = <0x0c>; 546 }; 547 hda13: hda@d { 548 compatible = "intel,hda-dai"; 549 status = "okay"; 550 reg = <0x0d>; 551 }; 552 hda14: hda@e { 553 compatible = "intel,hda-dai"; 554 status = "okay"; 555 reg = <0x0e>; 556 }; 557 hda15: hda@f { 558 compatible = "intel,hda-dai"; 559 status = "okay"; 560 reg = <0x0f>; 561 }; 562 }; 563}; 564
