1/*
2 * Copyright (c) 2023 Meta
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16		cpu@0 {
17			clock-frequency = <0>;
18			compatible = "renode,virt", "riscv";
19			device_type = "cpu";
20			reg = <0>;
21			riscv,isa = "rv32imac_zicsr_zifencei";
22			hlic: interrupt-controller {
23				compatible = "riscv,cpu-intc";
24				#address-cells = <0>;
25				#interrupt-cells = <1>;
26				interrupt-controller;
27			};
28		};
29	};
30
31	soc {
32		#address-cells = <1>;
33		#size-cells = <1>;
34		compatible = "renode,virt-soc", "simple-bus";
35		ranges;
36
37		flash0: flash@80000000 {
38			compatible = "soc-nv-flash";
39			reg = <0x80000000 DT_SIZE_M(4)>;
40		};
41
42		sram0: memory@80400000 {
43			compatible = "mmio-sram";
44			reg = <0x80400000 DT_SIZE_M(4)>;
45		};
46
47		clint: clint@2000000 {
48			compatible = "sifive,clint0";
49			interrupts-extended = <&hlic 3>, <&hlic 7>;
50			reg = <0x2000000 0x10000>;
51		};
52
53		mtimer: timer@200bff8 {
54			compatible = "riscv,machine-timer";
55			interrupts-extended = <&hlic 7>;
56			reg = <0x200bff8 0x8 0x2004000 0x8>;
57			reg-names = "mtime", "mtimecmp";
58		};
59
60		plic0: interrupt-controller@c000000 {
61			compatible = "sifive,plic-1.0.0";
62			#address-cells = <0>;
63			#interrupt-cells = <2>;
64			interrupt-controller;
65			interrupts-extended = <&hlic 11>;
66			reg = <0xc000000 0x04000000>;
67			riscv,max-priority = <1>;
68			riscv,ndev = <1023>;
69		};
70
71		plic1: interrupt-controller@8000000 {
72			compatible = "sifive,plic-1.0.0";
73			#address-cells = <0>;
74			#interrupt-cells = <2>;
75			interrupt-controller;
76			interrupts-extended = <&hlic 4>;
77			reg = <0x8000000 0x04000000>;
78			riscv,max-priority = <1>;
79			riscv,ndev = <1023>;
80		};
81
82		uart0: uart@10000000 {
83			interrupts = < 0x0a 1 >;
84			interrupt-parent = < &plic0 >;
85			clock-frequency = <150000000>;
86			current-speed = <115200>;
87			reg = < 0x10000000 0x100 >;
88			compatible = "ns16550";
89			reg-shift = < 0 >;
90			status = "disabled";
91		};
92
93		uart1: uart@10000100 {
94			interrupts = < 0x0a 1 >;
95			interrupt-parent = < &plic1 >;
96			clock-frequency = <150000000>;
97			current-speed = <115200>;
98			reg = < 0x10000100 0x100 >;
99			compatible = "ns16550";
100			reg-shift = < 0 >;
101			status = "disabled";
102		};
103	};
104};
105