1/*
2 * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <skeleton.dtsi>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11
12/ {
13	chosen {
14		zephyr,entropy = &trng;
15	};
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "neorv32,cpu", "riscv";
23			reg = <0>;
24			device_type = "cpu";
25
26			intc: interrupt-controller {
27				compatible = "riscv,cpu-intc";
28				interrupt-controller;
29				#address-cells = <1>;
30				#interrupt-cells = <1>;
31
32				firq: firq {
33					#address-cells = <1>;
34					interrupt-map-mask = <0x0 0xffffffff>;
35					interrupt-map = <
36						0  0 &intc 0 16
37						0  1 &intc 0 17
38						0  2 &intc 0 18
39						0  3 &intc 0 19
40						0  4 &intc 0 20
41						0  5 &intc 0 21
42						0  6 &intc 0 22
43						0  7 &intc 0 23
44						0  8 &intc 0 24
45						0  9 &intc 0 25
46						0 10 &intc 0 26
47						0 11 &intc 0 27
48						0 12 &intc 0 28
49						0 13 &intc 0 29
50						0 14 &intc 0 30
51						0 15 &intc 0 31
52					>;
53					#interrupt-cells = <1>;
54				};
55			};
56		};
57	};
58
59	soc {
60		compatible = "simple-bus";
61		interrupt-parent = <&firq>;
62		#address-cells = <1>;
63		#size-cells = <1>;
64		ranges;
65
66		imem: memory@0 {
67			compatible = "soc-nv-flash", "mmio-sram";
68			status = "disabled";
69		};
70
71		dmem: memory@80000000 {
72			compatible = "mmio-sram";
73			status = "disabled";
74		};
75
76		bootrom: rom@ffe00000 {
77			compatible = "neorv32,bootrom", "mmio-sram";
78			status = "disabled";
79			reg = <0xffe00000 0x10000>;
80		};
81
82		clint: clint@fff40000 {
83			compatible = "neorv32,clint", "sifive,clint0";
84			status = "disabled";
85			reg = <0xfff40000 0x10000>;
86			interrupts-extended = <&intc 3>;
87		};
88
89		mtimer: timer@fff4bff8 {
90			compatible = "riscv,machine-timer";
91			status = "disabled";
92			reg = <0xfff4bff8 0x8 0xfff44000 0x8>;
93			reg-names = "mtime", "mtimecmp";
94			interrupts-extended = <&intc 7>;
95		};
96
97		uart0: serial@fff50000 {
98			compatible = "neorv32,uart";
99			status = "disabled";
100			reg = <0xfff50000 0x10000>;
101			interrupts = <2>, <3>;
102			interrupt-names = "RX", "TX";
103			syscon = <&sysinfo>;
104		};
105
106		uart1: serial@fff60000 {
107			compatible = "neorv32,uart";
108			status = "disabled";
109			reg = <0xfff60000 0x10000>;
110			interrupts = <4>, <5>;
111			interrupt-names = "RX", "TX";
112			syscon = <&sysinfo>;
113		};
114
115		trng: rng@fffa0000 {
116			compatible = "neorv32,trng";
117			status = "disabled";
118			reg = <0xfffa0000 0x10000>;
119			syscon = <&sysinfo>;
120		};
121
122		gpio: gpio@fffc0000 {
123			compatible = "neorv32,gpio";
124			status = "disabled";
125			reg = <0xfffc0000 0x10000>;
126			syscon = <&sysinfo>;
127			gpio-controller;
128			ngpios = <32>;
129			#gpio-cells = <2>;
130		};
131
132		sysinfo: syscon@fffe0000 {
133			compatible = "neorv-sysinfo", "syscon";
134			status = "okay";
135			reg = <0xfffe0000 0x10000>;
136		};
137	};
138};
139