1/*
2 * Copyright (c) 2018 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14		cpu@0 {
15			clock-frequency = <0>;
16			compatible = "microchip,miv", "riscv";
17			device_type = "cpu";
18			reg = <0>;
19			riscv,isa = "rv32ima_zicsr_zifencei";
20			hlic: interrupt-controller {
21				compatible = "riscv,cpu-intc";
22				#address-cells = <0>;
23				#interrupt-cells = <1>;
24				interrupt-controller;
25			};
26		};
27	};
28
29	soc {
30		#address-cells = <1>;
31		#size-cells = <1>;
32		compatible = "microchip,miv-soc", "simple-bus";
33		ranges;
34
35		flash0: flash@80000000 {
36			compatible = "soc-nv-flash";
37			reg = <0x80000000 0x40000>;
38		};
39
40		sram0: memory@80040000 {
41			compatible = "mmio-sram";
42			reg = <0x80040000 0x40000>;
43		};
44
45		clint: clint@44000000 {
46			compatible = "sifive,clint0";
47			interrupts-extended = <&hlic 3>, <&hlic 7>;
48			reg = <0x44000000 0x10000>;
49		};
50
51		mtimer: timer@4400bff8 {
52			compatible = "riscv,machine-timer";
53			interrupts-extended = <&hlic 7>;
54			reg = <0x4400bff8 0x8 0x44004000 0x8>;
55			reg-names = "mtime", "mtimecmp";
56		};
57
58		plic: interrupt-controller@40000000 {
59			compatible = "sifive,plic-1.0.0";
60			#address-cells = <0>;
61			#interrupt-cells = <2>;
62			interrupt-controller;
63			interrupts-extended = <&hlic 11>;
64			reg = <0x40000000 0x04000000>;
65			riscv,max-priority = <1>;
66			riscv,ndev = <31>;
67		};
68
69		uart0: uart@70001000 {
70			compatible = "microchip,coreuart";
71			reg = <0x70001000 0x1000>;
72			status = "disabled";
73			current-speed = <0>;
74			clock-frequency = <0>;
75		};
76	};
77};
78