1# Copyright 2018-2023, NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: NXP FlexSPI controller
5
6compatible: "nxp,imx-flexspi"
7
8include: [spi-controller.yaml, pinctrl-device.yaml]
9
10properties:
11  reg:
12    required: true
13
14  interrupts:
15    required: true
16
17  ahb-bufferable:
18    type: boolean
19    description: |
20      Enable AHB bufferable write access by setting register field
21      AHBCR[BUFFERABLEEN].
22
23  ahb-cacheable:
24    type: boolean
25    description: |
26      Enable AHB cacheable read access by setting register field
27      AHBCR[CACHEABLEEN].
28
29  ahb-prefetch:
30    type: boolean
31    description: |
32      Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
33
34  ahb-read-addr-opt:
35    type: boolean
36    description: |
37      Remove burst start address alignment limitation by setting register
38      field AHBCR[READADDROPT].
39
40  combination-mode:
41    type: boolean
42    description: |
43      Combine port A and port B data pins to support octal mode access by
44      setting register field MCR0[COMBINATIONEN].
45
46  sck-differential-clock:
47    type: boolean
48    description: |
49      Enable/disable SCKB pad use as SCKA differential clock output,
50      when enabled, Port B flash access is not available.
51
52  rx-clock-source:
53    type: int
54    default: 0
55    enum:
56      - 0 # Loopback internally
57      - 1 # Loopback from DQS pad
58      - 2 # Loopback from SCK pad
59      - 3 # External input from DQS pad
60    description: |
61      Source clock for flash read. See the RXCLKSRC field in register MCR0.
62      The default corresponds to the reset value of the register field.
63
64  rx-clock-source-b:
65    type: int
66    default: 0
67    enum:
68      - 0 # Loopback internally
69      - 1 # Loopback from DQS pad
70      - 2 # Loopback from SCK pad
71      - 3 # External input from DQS pad
72    description: |
73      Source clock for flash read on port B. Only supported by some instances
74      of this IP. See the RXCLKSRC_B field in register MCR2.
75      The default corresponds to the reset value of the register field.
76
77  rx-buffer-config:
78    type: array
79    description: |
80      Array of tuples to configure AHB RX buffers. Format is the following:
81      <prefetch priority master_id buf_size>. Pass multiple tuples to configure
82      multiple RX buffers (up to maximum supported by SOC).
83      The tuple fields correspond to the following register bitfields:
84      prefetch: AHBRXBUFxCRx[PREFETCH]
85      priority: AHBRXBUFxCRx[PRIORITY]
86      master_id: AHBRXBUFxCRx[MSTRID]
87      buf_size: AHBRXBUFxCRx[BUFSZ]
88
89  ahb-boundary:
90    type: string
91    default: "no-boundary"
92    enum:
93      - "no-boundary"
94      - "1024"
95      - "512"
96      - "256"
97    description: |
98      Sets the AHB read/write boundary. Only supported by some versions of
99      the FLEXSPI IP. When set, all memory accesses that cross an address
100      boundary of the specified size will be divided into smaller sub accesses.
101
102child-binding:
103  description: NXP FlexSPI port
104
105  include: nxp,imx-flexspi-device.yaml
106