1# Copyright (c) 2022 Georgij Cernysiov
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Flexible Memory Controller (NOR Flash/PSRAM/SRAM controller).
6
7  The FMC generates the appropriate signal timings to drive the
8  following types of memories:
9
10  * Asynchronous SRAM and ROM
11    - 8 bits
12    - 16 bits
13    - 32 bits
14  * PSRAM (Cellular RAM)
15    - Asynchronous mode
16    - Burst mode for synchronous accesses with configurable option to split burst
17      access when crossing boundary page for CRAM 1.5.
18    - Multiplexed or non-multiplexed
19  * NOR Flash memory
20    - Asynchronous mode
21    - Burst mode for synchronous accesses
22    - Multiplexed or non-multiplexed
23
24  A unique Chip Select signal (NE) is used per bank. All the other
25  signals (addresses, data and control) are shared. A wide range of
26  devices is supported through programmable timings.
27
28  Refer to the reference manual for more details.
29
30  The FMC NOR/PSRAM controller is defined below the FMC node and banks are
31  defined as child nodes of the FMC NOR/PSRAM controller node.
32
33  You can enable the controller in devicetree as follows:
34
35  &fmc {
36    status = "okay";
37    pinctrl-0 = <&fmc_nwe_pd5 &fmc_noe_pd4 ...>;
38    pinctrl-names = "default";
39
40    sram {
41      status = "okay";
42      compatible = "st,stm32-fmc-nor-psram";
43
44      #address-cells = <1>;
45      #size-cells = <0>;
46
47      sram2@2 {
48        reg = <0x2>;
49        st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
50                      STM32_FMC_MEMORY_TYPE_SRAM
51                      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
52                      STM32_FMC_BURST_ACCESS_MODE_DISABLE
53                      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
54                      STM32_FMC_WAIT_TIMING_BEFORE_WS
55                      STM32_FMC_WRITE_OPERATION_ENABLE
56                      STM32_FMC_WAIT_SIGNAL_DISABLE
57                      STM32_FMC_EXTENDED_MODE_DISABLE
58                      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
59                      STM32_FMC_WRITE_BURST_DISABLE
60                      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
61                      STM32_FMC_WRITE_FIFO_DISABLE
62                      STM32_FMC_PAGE_SIZE_NONE>;
63        st,timing = <4 2 3 0 16 17 STM32_FMC_ACCESS_MODE_A>;
64      };
65    };
66  };
67
68  Use constants defined in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
69
70compatible: "st,stm32-fmc-nor-psram"
71
72include: base.yaml
73
74properties:
75  "#address-cells":
76    required: true
77    const: 1
78
79  "#size-cells":
80    required: true
81    const: 0
82
83child-binding:
84  description: NOR/PSRAM bank.
85
86  properties:
87    reg:
88      type: int
89      required: true
90
91    st,control:
92      type: array
93      required: true
94      description: |
95        SRAM/NOR-Flash control register (FMC_BCRx).
96
97        Contains control information of each memory bank,
98        used for SRAMs, PSRAM and NOR Flash memories.
99
100        Expected fields, in order:
101
102        * MUXEN - Address/data multiplexing enable bit.
103        * MTYP  - Memory type.
104        * MWID  - Memory data bus width.
105        * FACCEN - Flash access enable.
106        * BURSTEN - Burst enable bit.
107        * WAITPOL - Wait signal polarity bit.
108        * WAITCFG - Wait timing configuration.
109        * WREN - Write enable bit.
110        * WAITEN - Wait enable bit.
111        * EXTMOD - Extended mode enable.
112                   If set, then 'st,timing-ext' shall be provided.
113        * ASYNCWAIT -  Wait signal during asynchronous transfers.
114        * CPSIZE - Cellular RAM (CRAM) 1.5 Page Size.
115        * CBURSTRW - Write burst enable.
116        * CCLKEN - Continuous Clock Enable.
117        * WFDIS - Write FIFO Disable.
118        * BMAP - FMC bank mapping.
119
120    st,timing:
121      type: array
122      required: true
123      description: |
124        SRAM/NOR-Flash (read) timing register (FMC_BTRx).
125
126        If the EXTMOD is set (see control register FMC_BCRx), then
127        FMC_BTRx register is partitioned for write and read access.
128        That means, use this property to configure read accesses and
129        'st,timing-ext' to configure write accesses.
130
131        Expected fields, in order:
132
133        * ADDSET  - Address setup phase duration.
134                    Number of HCLK cycles to configure the duration of
135                    the address setup time. This parameter can be a value
136                    between Min_Data = 0 and Max_Data = 15.
137                    Note: Not used with synchronous NOR Flash memories.
138        * ADDHLD  - Address-hold phase duration.
139                    Number of HCLK cycles to configure the duration of
140                    the address hold time. This parameter can be a value
141                    between Min_Data = 1 and Max_Data = 15.
142                    Note: Not used with synchronous NOR Flash memories.
143        * DATAST  - Data-phase duration.
144                    Number of HCLK cycles to configure the duration of
145                    the data setup time. This parameter can be a value
146                    between Min_Data = 1 and Max_Data = 255.
147                    Note: Used for SRAMs, ROMs and asynchronous multiplexed
148                    NOR Flash memories.
149        * BUSTURN - Bus turnaround phase duration.
150                    Number of HCLK cycles to configure the duration of
151                    the bus turnaround. This parameter can be a value
152                    between Min_Data = 0 and Max_Data = 15.
153                    Note: Only used for multiplexed NOR Flash memories.
154        * CLKDIV  - Clock divide ratio (for FMC_CLK signal).
155                    Period of CLK clock output signal, expressed in number of
156                    HCLK cycles. This parameter can be a value
157                    between Min_Data = 2 and Max_Data = 16.
158                    Note: Not used for asynchronous NOR Flash, SRAM or ROM
159                    accesses.
160        * DATLAT  - Data latency for synchronous memory.
161                    Number of memory clock cycles to issue to the memory
162                    before getting the first data.
163                    The value depends on the memory type as shown below:
164                    - It must be set to 0 in case of a CRAM
165                    - It is don't care in asynchronous NOR, SRAM or ROM accesses
166                    - It may assume a value between Min_Data = 2 and Max_Data = 17
167                      in NOR Flash memories with synchronous burst mode enable
168        * ACCMOD  - Access mode.
169                    See access mode defines
170                    in dt-bindings/memory-controller/stm32-fmc-nor-psram.h.
171
172    st,timing-ext:
173      type: array
174      default: [0xF, 0xF, 0xFF, 0xF, 0x0] # reset state
175      description: |
176        SRAM/NOR-Flash (write) timing register (FMC_BWTRx).
177
178        Expected fields, in order:
179
180        * ADDSET  - Address setup phase duration.
181                    Reset state: 15 (0xF).
182        * ADDHLD  - Address-hold phase duration.
183                    Reset state: 15 (0xF).
184        * DATAST  - Data-phase duration.
185                    Reset state: 255 (0xFF).
186        * BUSTURN - Bus turnaround phase duration.
187                    Reset state: 15 (0xF).
188        * ACCMOD  - Access mode.
189                    Reset state: 0 (0x0).
190
191        Refer to 'st,timing' for detailed field descriptions.
192
193        This property is applied only when EXTMOD is set
194        (see control register FMC_BCRx).
195
196        If absent, then reset state values are used.
197