1/* 2 * Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6#include <mem.h> 7#include <arm/armv7-a.dtsi> 8#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 9#include <zephyr/dt-bindings/ethernet/xlnx_gem.h> 10 11/ { 12 soc { 13 interrupt-parent = <&gic>; 14 15 ocm_low: memory@1000 { 16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 17 reg = <0x00001000 DT_SIZE_K(188)>; 18 zephyr,memory-region = "OCM_LOW"; 19 }; 20 21 ocm_high: memory@fffc0000 { 22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; 23 reg = <0xFFFC0000 DT_SIZE_K(256)>; 24 zephyr,memory-region = "OCM_HIGH"; 25 }; 26 27 arch_timer: timer@f8f00200 { 28 compatible = "arm,armv8-timer"; 29 status = "okay"; 30 interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; 31 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE 32 IRQ_DEFAULT_PRIORITY>, 33 <GIC_PPI 14 IRQ_TYPE_EDGE 34 IRQ_DEFAULT_PRIORITY>, 35 <GIC_PPI 11 IRQ_TYPE_EDGE 36 IRQ_DEFAULT_PRIORITY>, 37 <GIC_PPI 10 IRQ_TYPE_EDGE 38 IRQ_DEFAULT_PRIORITY>; 39 reg = <0xf8f00200 0x1C>; 40 }; 41 42 gic: interrupt-controller@f8f01000 { 43 compatible = "arm,gic-v1", "arm,gic"; 44 status = "okay"; 45 reg = <0xf8f01000 0x1000>, 46 <0xf8f00100 0x100>; 47 interrupt-controller; 48 #interrupt-cells = <4>; 49 }; 50 51 gem0: ethernet@e000b000 { 52 compatible = "xlnx,gem"; 53 status = "disabled"; 54 reg = <0xe000b000 0x1000>, 55 <0xf8000140 0x4>; 56 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL 57 IRQ_DEFAULT_PRIORITY>, 58 <GIC_SPI 23 IRQ_TYPE_LEVEL 59 IRQ_DEFAULT_PRIORITY>; 60 interrupt-names = "irq_0", "irq_1"; 61 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 62 phy-poll-interval = <1000>; 63 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 64 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 65 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 66 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 67 hw-rx-buffer-offset = <0>; 68 hw-tx-buffer-size-full; 69 rx-buffer-descriptors = <32>; 70 tx-buffer-descriptors = <32>; 71 rx-buffer-size = <512>; 72 tx-buffer-size = <512>; 73 discard-rx-fcs; 74 unicast-hash; 75 full-duplex; 76 }; 77 78 gem1: ethernet@e000c000 { 79 compatible = "xlnx,gem"; 80 status = "disabled"; 81 reg = <0xe000c000 0x1000>, 82 <0xf8000144 0x4>; 83 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL 84 IRQ_DEFAULT_PRIORITY>, 85 <GIC_SPI 46 IRQ_TYPE_LEVEL 86 IRQ_DEFAULT_PRIORITY>; 87 interrupt-names = "irq_0", "irq_1"; 88 mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; 89 phy-poll-interval = <1000>; 90 link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; 91 amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; 92 amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; 93 hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; 94 hw-rx-buffer-offset = <0>; 95 hw-tx-buffer-size-full; 96 rx-buffer-descriptors = <32>; 97 tx-buffer-descriptors = <32>; 98 rx-buffer-size = <512>; 99 tx-buffer-size = <512>; 100 discard-rx-fcs; 101 unicast-hash; 102 full-duplex; 103 }; 104 105 uart0: uart@e0000000 { 106 compatible = "xlnx,xuartps"; 107 status = "disabled"; 108 reg = <0xe0000000 0x4c>; 109 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL 110 IRQ_DEFAULT_PRIORITY>; 111 interrupt-names = "irq_0"; 112 }; 113 114 uart1: uart@e0001000 { 115 compatible = "xlnx,xuartps"; 116 status = "disabled"; 117 reg = <0xe0001000 0x4c>; 118 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL 119 IRQ_DEFAULT_PRIORITY>; 120 interrupt-names = "irq_0"; 121 }; 122 123 psgpio: gpio@e000a000 { 124 compatible = "xlnx,ps-gpio"; 125 status = "disabled"; 126 reg = <0xe000a000 0x1000>; 127 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL 128 IRQ_DEFAULT_PRIORITY>; 129 interrupt-names = "irq_0"; 130 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 psgpio_bank0: psgpio_bank@0 { 135 compatible = "xlnx,ps-gpio-bank"; 136 reg = <0x0>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 ngpios = <32>; 140 status = "okay"; 141 }; 142 143 psgpio_bank1: psgpio_bank@1 { 144 compatible = "xlnx,ps-gpio-bank"; 145 reg = <0x1>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 ngpios = <22>; 149 status = "okay"; 150 }; 151 152 psgpio_bank2: psgpio_bank@2 { 153 compatible = "xlnx,ps-gpio-bank"; 154 reg = <0x2>; 155 gpio-controller; 156 #gpio-cells = <2>; 157 ngpios = <32>; 158 status = "okay"; 159 }; 160 161 psgpio_bank3: psgpio_bank@3 { 162 compatible = "xlnx,ps-gpio-bank"; 163 reg = <0x3>; 164 gpio-controller; 165 #gpio-cells = <2>; 166 ngpios = <32>; 167 status = "okay"; 168 }; 169 }; 170 }; 171 172 slcr: slcr@f8000000 { 173 #address-cells = <1>; 174 #size-cells = <1>; 175 compatible = "xlnx,zynq-slcr", "syscon"; 176 reg = <0xf8000000 0x1000>; 177 ranges; 178 179 pinctrl0: pinctrl@700 { 180 compatible = "xlnx,pinctrl-zynq"; 181 reg = <0x700 0x200>; 182 syscon = <&slcr>; 183 }; 184 }; 185}; 186
