1/*
2 * Copyright 2023-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <mem.h>
9#include <zephyr/dt-bindings/clock/nxp_s32k344_clock.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-m7";
20			reg = <0>;
21		};
22
23		cpu@1 {
24			device_type = "cpu";
25			compatible = "arm,cortex-m7";
26			reg = <1>;
27		};
28
29		mpu: mpu@e000ed90 {
30			compatible = "arm,armv7m-mpu";
31			reg = <0xe000ed90 0x40>;
32		};
33	};
34
35	/* Dummy pinctrl node, filled with pin mux options at board level */
36	pinctrl: pinctrl {
37		compatible = "nxp,s32k3-pinctrl";
38		status = "okay";
39	};
40
41	soc {
42		interrupt-parent = <&nvic>;
43
44		itcm: memory@0 {
45			compatible = "zephyr,memory-region", "arm,itcm";
46			reg = <0x00000000 DT_SIZE_K(64)>;
47			zephyr,memory-region = "ITCM";
48		};
49
50		dtcm: memory@20000000 {
51			compatible = "zephyr,memory-region", "arm,dtcm";
52			reg = <0x20000000 DT_SIZE_K(128)>;
53			zephyr,memory-region = "DTCM";
54		};
55
56		sram0_1: sram0_1@20400000 {
57			compatible = "mmio-sram";
58			reg = <0x20400000 DT_SIZE_K(320)>;
59		};
60
61		/*
62		 * Last 48Kb is reserved by Secure BAF, application core cannot access it.
63		 *
64		 * Do not assign the compatible for this now, when Flash API is implemented,
65		 * need to check if "soc-nv-flash" can be used or a new binding need to be
66		 * created, based on it.
67		 */
68		flash0: flash@400000 {
69			reg = <0x00400000 DT_SIZE_K(4048)>;
70			status = "disabled";
71		};
72
73		clock: clock-controller@402c8000 {
74			compatible = "nxp,s32-clock";
75			reg = <0x402c8000 0x4000>,
76				<0x402cc000 0x4000>,
77				<0x402d0000 0x4000>,
78				<0x402d4000 0x4000>,
79				<0x402d8000 0x4000>,
80				<0x402e0000 0x4000>;
81			#clock-cells = <1>;
82			status = "okay";
83		};
84
85		siul2_0: siul2@40290000 {
86			reg = <0x40290000 0x10000>;
87			#address-cells = <1>;
88			#size-cells = <1>;
89
90			eirq0: eirq@40290010 {
91				compatible = "nxp,s32-siul2-eirq";
92				reg = <0x40290010 0xb4>;
93				#address-cells = <0>;
94				interrupts = <53 0>, <54 0>, <55 0>, <56 0>;
95				interrupt-controller;
96				#interrupt-cells = <2>;
97				status = "disabled";
98			};
99
100			gpioa_l: gpio@40291702 {
101				compatible = "nxp,s32-gpio";
102				reg = <0x40291702 0x02>, <0x40290240 0x40>;
103				reg-names = "pgpdo", "mscr";
104				interrupt-parent = <&eirq0>;
105				interrupts = <0 0>, <1 1>, <2 2>, <3 3>, <4 4>,
106					<5 5>, <6 6>, <7 7>, <8 16>, <9 17>,
107					<10 18>, <11 19>, <12 20>, <13 21>,
108					<14 22>, <15 23>;
109				nxp,wkpu = <&wkpu>;
110				nxp,wkpu-interrupts = <1 9>, <2 4>, <6 19>,
111					<8 27>, <9 25>, <13 8>, <15 24>;
112				gpio-controller;
113				#gpio-cells = <2>;
114				ngpios = <16>;
115				status = "disabled";
116			};
117
118			gpioa_h: gpio@40291700 {
119				compatible = "nxp,s32-gpio";
120				reg = <0x40291700 0x02>, <0x40290280 0x40>;
121				reg-names = "pgpdo", "mscr";
122				interrupt-parent = <&eirq0>;
123				interrupts = <0 4>, <2 0>, <3 1>, <4 2>,
124					<5 3>, <9 5>, <12 6>, <14 7>;
125				nxp,wkpu = <&wkpu>;
126				nxp,wkpu-interrupts = <0 35>, <4 63>, <9 38>,
127					<10 39>, <14 41>;
128				gpio-controller;
129				#gpio-cells = <2>;
130				ngpios = <16>;
131				status = "disabled";
132			};
133
134			gpiob_l: gpio@40291706 {
135				compatible = "nxp,s32-gpio";
136				reg = <0x40291706 0x02>, <0x402902c0 0x40>;
137				reg-names = "pgpdo", "mscr";
138				interrupt-parent = <&eirq0>;
139				interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>,
140					<5 13>, <8 14>, <9 15>, <10 24>, <11 25>,
141					<12 26>, <13 27>, <14 28>, <15 29>;
142				nxp,wkpu = <&wkpu>;
143				nxp,wkpu-interrupts = <0 11>, <2 12>, <8 29>,
144					<9 21>, <11 20>, <12 16>, <13 15>, <15 37>;
145				gpio-controller;
146				#gpio-cells = <2>;
147				ngpios = <16>;
148				gpio-reserved-ranges = <6 2>;
149				status = "disabled";
150			};
151
152			gpiob_h: gpio@40291704 {
153				compatible = "nxp,s32-gpio";
154				reg = <0x40291704 0x02>, <0x40290300 0x40>;
155				reg-names = "pgpdo", "mscr";
156				interrupt-parent = <&eirq0>;
157				interrupts = <0 30>, <1 31>, <5 8>, <6 9>, <7 10>,
158					<8 11>, <9 12>, <10 13>, <12 14>, <15 15>;
159				nxp,wkpu = <&wkpu>;
160				nxp,wkpu-interrupts = <0 17>, <1 18>, <3 42>,
161					<5 43>, <7 44>, <10 45>, <12 46>;
162				gpio-controller;
163				#gpio-cells = <2>;
164				ngpios = <16>;
165				status = "disabled";
166			};
167
168			gpioc_l: gpio@4029170a {
169				compatible = "nxp,s32-gpio";
170				reg = <0x4029170a 0x02>, <0x40290340 0x40>;
171				reg-names = "pgpdo", "mscr";
172				interrupt-parent = <&eirq0>;
173				interrupts = <0 1>, <1 1>, <2 2>, <3 3>, <4 4>,
174					<5 5>, <6 6>, <7 7>, <8 16>, <9 17>,
175					<10 18>, <11 19>, <12 20>, <13 21>,
176					<14 22>, <15 23>;
177				nxp,wkpu = <&wkpu>;
178				nxp,wkpu-interrupts = <6 7>, <7 6>, <9 14>, <11 22>;
179				gpio-controller;
180				#gpio-cells = <2>;
181				ngpios = <16>;
182				status = "disabled";
183			};
184
185			gpioc_h: gpio@40291708 {
186				compatible = "nxp,s32-gpio";
187				reg = <0x40291708 0x02>, <0x40290380 0x40>;
188				reg-names = "pgpdo", "mscr";
189				interrupt-parent = <&eirq0>;
190				interrupts = <4 16>, <5 17>, <7 18>, <8 19>,
191					<9 20>, <10 21>, <11 22>, <13 23>;
192				nxp,wkpu = <&wkpu>;
193				nxp,wkpu-interrupts = <2 40>, <4 47>, <7 48>,
194					<8 50>, <9 49>, <10 52>, <13 51>, <15 53>;
195				gpio-controller;
196				#gpio-cells = <2>;
197				ngpios = <16>;
198				status = "disabled";
199			};
200
201			gpiod_l: gpio@4029170e {
202				compatible = "nxp,s32-gpio";
203				reg = <0x4029170e 0x02>, <0x402903c0 0x40>;
204				reg-names = "pgpdo", "mscr";
205				interrupt-parent = <&eirq0>;
206				interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>,
207					<5 13>, <6 14>, <7 15>, <8 24>,
208					<9 25>, <10 26>, <11 27>, <12 28>,
209					<13 29>, <14 30>, <15 31>;
210				nxp,wkpu = <&wkpu>;
211				nxp,wkpu-interrupts = <0 10>, <2 13>, <3 5>,
212					<4 26>, <13 28>;
213				gpio-controller;
214				#gpio-cells = <2>;
215				ngpios = <16>;
216				status = "disabled";
217			};
218
219			gpiod_h: gpio@4029170c {
220				compatible = "nxp,s32-gpio";
221				reg = <0x4029170c 0x02>, <0x40290400 0x40>;
222				reg-names = "pgpdo", "mscr";
223				interrupt-parent = <&eirq0>;
224				interrupts = <1 24>, <4 25>, <5 26>, <6 27>,
225					<7 28>, <8 29>, <11 30>, <12 31>;
226				nxp,wkpu = <&wkpu>;
227				nxp,wkpu-interrupts = <4 58>, <7 54>, <11 55>,
228					<13 56>, <15 57>;
229				gpio-controller;
230				#gpio-cells = <2>;
231				ngpios = <16>;
232				status = "disabled";
233			};
234
235			gpioe_l: gpio@40291712 {
236				compatible = "nxp,s32-gpio";
237				reg = <0x40291712 0x02>, <0x40290440 0x40>;
238				reg-names = "pgpdo", "mscr";
239				interrupt-parent = <&eirq0>;
240				interrupts = <0 0>, <1 1>, <2 2>, <3 3>,
241					<4 4>, <5 5>, <6 6>, <8 7>,
242					<9 8>, <10 9>, <11 10>, <12 11>,
243					<13 12>, <14 13>, <15 14>;
244				nxp,wkpu = <&wkpu>;
245				nxp,wkpu-interrupts = <0 30>, <2 31>, <5 36>,
246					<6 33>, <11 32>, <14 34>;
247				gpio-controller;
248				#gpio-cells = <2>;
249				ngpios = <16>;
250				status = "disabled";
251			};
252
253			gpioe_h: gpio@40291710 {
254				compatible = "nxp,s32-gpio";
255				reg = <0x40291710 0x02>, <0x40290480 0x40>;
256				reg-names = "pgpdo", "mscr";
257				interrupt-parent = <&eirq0>;
258				interrupts = <0 15>;
259				nxp,wkpu = <&wkpu>;
260				nxp,wkpu-interrupts = <0 23>, <2 59>, <5 60>,
261					<7 61>, <9 62>;
262				gpio-controller;
263				#gpio-cells = <2>;
264				ngpios = <16>;
265				status = "disabled";
266			};
267
268			gpiof_l: gpio@40291716 {
269				compatible = "nxp,s32-gpio";
270				reg = <0x40291716 0x02>, <0x402904c0 0x40>;
271				reg-names = "pgpdo", "mscr";
272				interrupt-parent = <&eirq0>;
273				interrupts = <0 0>, <1 1>, <2 2>, <3 3>,
274					<4 4>, <5 5>, <6 6>, <7 7>,
275					<8 16>, <9 17>, <10 18>, <11 19>,
276					<12 20>, <13 21>, <14 22>, <15 23>;
277				gpio-controller;
278				#gpio-cells = <2>;
279				ngpios = <16>;
280				status = "disabled";
281			};
282
283			gpiof_h: gpio@40291714 {
284				compatible = "nxp,s32-gpio";
285				reg = <0x40291714 0x02>, <0x40290500 0x40>;
286				reg-names = "pgpdo", "mscr";
287				gpio-controller;
288				#gpio-cells = <2>;
289				ngpios = <16>;
290				status = "disabled";
291			};
292
293			gpiog_l: gpio@4029171a {
294				compatible = "nxp,s32-gpio";
295				reg = <0x4029171a 0x02>, <0x40290540 0x40>;
296				reg-names = "pgpdo", "mscr";
297				interrupt-parent = <&eirq0>;
298				interrupts = <0 8>, <1 9>, <2 10>, <3 11>,
299					<4 12>, <5 13>, <6 14>, <7 15>,
300					<8 24>, <9 25>, <10 26>, <11 27>,
301					<12 28>, <13 29>, <14 30>, <15 31>;
302				gpio-controller;
303				#gpio-cells = <2>;
304				ngpios = <16>;
305				status = "disabled";
306			};
307
308			gpiog_h: gpio@40291718 {
309				compatible = "nxp,s32-gpio";
310				reg = <0x40291718 0x02>, <0x40290580 0x40>;
311				reg-names = "pgpdo", "mscr";
312				gpio-controller;
313				#gpio-cells = <2>;
314				ngpios = <16>;
315				status = "disabled";
316			};
317		};
318
319		wkpu: wkpu@402b4000 {
320			compatible = "nxp,s32-wkpu";
321			reg = <0x402b4000 0x4000>;
322			interrupts = <83 0>;
323			status = "disabled";
324		};
325
326		lpuart0: uart@40328000 {
327			compatible = "nxp,lpuart";
328			reg = <0x40328000 0x4000>;
329			interrupts = <141 0>;
330			clocks = <&clock NXP_S32_LPUART0_CLK>;
331			status = "disabled";
332		};
333
334		lpuart1: uart@4032c000 {
335			compatible = "nxp,lpuart";
336			reg = <0x4032c000 0x4000>;
337			interrupts = <142 0>;
338			clocks = <&clock NXP_S32_LPUART1_CLK>;
339			status = "disabled";
340		};
341
342		lpuart2: uart@40330000 {
343			compatible = "nxp,lpuart";
344			reg = <0x40330000 0x4000>;
345			interrupts = <143 0>;
346			clocks = <&clock NXP_S32_LPUART2_CLK>;
347			status = "disabled";
348		};
349
350		lpuart3: uart@40334000 {
351			compatible = "nxp,lpuart";
352			reg = <0x40334000 0x4000>;
353			interrupts = <144 0>;
354			clocks = <&clock NXP_S32_LPUART3_CLK>;
355			status = "disabled";
356		};
357
358		lpuart4: uart@40338000 {
359			compatible = "nxp,lpuart";
360			reg = <0x40338000 0x4000>;
361			interrupts = <145 0>;
362			clocks = <&clock NXP_S32_LPUART4_CLK>;
363			status = "disabled";
364		};
365
366		lpuart5: uart@4033c000 {
367			compatible = "nxp,lpuart";
368			reg = <0x4033c000 0x4000>;
369			interrupts = <146 0>;
370			clocks = <&clock NXP_S32_LPUART5_CLK>;
371			status = "disabled";
372		};
373
374		lpuart6: uart@40340000 {
375			compatible = "nxp,lpuart";
376			reg = <0x40340000 0x4000>;
377			interrupts = <147 0>;
378			clocks = <&clock NXP_S32_LPUART6_CLK>;
379			status = "disabled";
380		};
381
382		lpuart7: uart@40344000 {
383			compatible = "nxp,lpuart";
384			reg = <0x40344000 0x4000>;
385			interrupts = <148 0>;
386			clocks = <&clock NXP_S32_LPUART7_CLK>;
387			status = "disabled";
388		};
389
390		lpuart8: uart@4048c000 {
391			compatible = "nxp,lpuart";
392			reg = <0x4048c000 0x4000>;
393			interrupts = <149 0>;
394			clocks = <&clock NXP_S32_LPUART8_CLK>;
395			status = "disabled";
396		};
397
398		lpuart9: uart@40490000 {
399			compatible = "nxp,lpuart";
400			reg = <0x40490000 0x4000>;
401			interrupts = <150 0>;
402			clocks = <&clock NXP_S32_LPUART9_CLK>;
403			status = "disabled";
404		};
405
406		lpuart10: uart@40494000 {
407			compatible = "nxp,lpuart";
408			reg = <0x40494000 0x4000>;
409			interrupts = <151 0>;
410			clocks = <&clock NXP_S32_LPUART10_CLK>;
411			status = "disabled";
412		};
413
414		lpuart11: uart@40498000 {
415			compatible = "nxp,lpuart";
416			reg = <0x40498000 0x4000>;
417			interrupts = <152 0>;
418			clocks = <&clock NXP_S32_LPUART11_CLK>;
419			status = "disabled";
420		};
421
422		lpuart12: uart@4049c000 {
423			compatible = "nxp,lpuart";
424			reg = <0x4049c000 0x4000>;
425			interrupts = <153 0>;
426			clocks = <&clock NXP_S32_LPUART12_CLK>;
427			status = "disabled";
428		};
429
430		lpuart13: uart@404a0000 {
431			compatible = "nxp,lpuart";
432			reg = <0x404a0000 0x4000>;
433			interrupts = <154 0>;
434			clocks = <&clock NXP_S32_LPUART13_CLK>;
435			status = "disabled";
436		};
437
438		lpuart14: uart@404a4000 {
439			compatible = "nxp,lpuart";
440			reg = <0x404a4000 0x4000>;
441			interrupts = <155 0>;
442			clocks = <&clock NXP_S32_LPUART14_CLK>;
443			status = "disabled";
444		};
445
446		lpuart15: uart@404a8000 {
447			compatible = "nxp,lpuart";
448			reg = <0x404a8000 0x4000>;
449			interrupts = <156 0>;
450			clocks = <&clock NXP_S32_LPUART15_CLK>;
451			status = "disabled";
452		};
453
454		qspi0: qspi@404cc000 {
455			compatible = "nxp,s32-qspi";
456			reg = <0x404cc000 0x4000>;
457			#address-cells = <1>;
458			#size-cells = <0>;
459			status = "disabled";
460		};
461
462		flexcan0: can@40304000 {
463			compatible = "nxp,flexcan-fd", "nxp,flexcan";
464			reg = <0x40304000 0x4000>;
465			clocks = <&clock NXP_S32_FLEXCANA_CLK>;
466			clk-source = <0>;
467			interrupts = <109 0>, <110 0>, <111 0>, <112 0>;
468			interrupt-names = "ored", "ored_0_31_mb",
469						"ored_32_63_mb", "ored_64_95_mb";
470			status = "disabled";
471		};
472
473		flexcan1: can@40308000 {
474			compatible = "nxp,flexcan-fd", "nxp,flexcan";
475			reg = <0x40308000 0x4000>;
476			clocks = <&clock NXP_S32_FLEXCANA_CLK>;
477			clk-source = <0>;
478			interrupts = <113 0>, <114 0>, <115 0>;
479			interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb";
480			status = "disabled";
481		};
482
483		flexcan2: can@4030c000 {
484			compatible = "nxp,flexcan-fd", "nxp,flexcan";
485			reg = <0x4030c000 0x4000>;
486			clocks = <&clock NXP_S32_FLEXCANA_CLK>;
487			clk-source = <0>;
488			interrupts = <116 0>, <117 0>, <118 0>;
489			interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb";
490			status = "disabled";
491		};
492
493		flexcan3: can@40310000 {
494			compatible = "nxp,flexcan-fd", "nxp,flexcan";
495			reg = <0x40310000 0x4000>;
496			clocks = <&clock NXP_S32_FLEXCANB_CLK>;
497			clk-source = <0>;
498			interrupts = <119 0>, <120 0>;
499			interrupt-names = "ored", "ored_0_31_mb";
500			status = "disabled";
501		};
502
503		flexcan4: can@40314000 {
504			compatible = "nxp,flexcan-fd", "nxp,flexcan";
505			reg = <0x40314000 0x4000>;
506			clocks = <&clock NXP_S32_FLEXCANB_CLK>;
507			clk-source = <0>;
508			interrupts = <121 0>, <122 0>;
509			interrupt-names = "ored", "ored_0_31_mb";
510			status = "disabled";
511		};
512
513		flexcan5: can@40318000 {
514			compatible = "nxp,flexcan-fd", "nxp,flexcan";
515			reg = <0x40318000 0x4000>;
516			clocks = <&clock NXP_S32_FLEXCANB_CLK>;
517			clk-source = <0>;
518			interrupts = <123 0>, <124 0>;
519			interrupt-names = "ored", "ored_0_31_mb";
520			status = "disabled";
521		};
522
523		lpi2c0: i2c@40350000 {
524			compatible = "nxp,lpi2c";
525			reg = <0x40350000 0x10000>;
526			clocks = <&clock NXP_S32_LPI2C0_CLK>;
527			#address-cells = <1>;
528			#size-cells = <0>;
529			interrupts = <161 0>;
530			status = "disabled";
531		};
532
533		lpi2c1: i2c@40354000 {
534			compatible = "nxp,lpi2c";
535			reg = <0x40354000 0x10000>;
536			clocks = <&clock NXP_S32_LPI2C1_CLK>;
537			#address-cells = <1>;
538			#size-cells = <0>;
539			interrupts = <162 0>;
540			status = "disabled";
541		};
542
543		adc0: adc@400a0000 {
544			compatible = "nxp,s32-adc-sar";
545			reg = <0x400a0000 0x1000>;
546			interrupts = <180 0>;
547			#io-channel-cells = <1>;
548			status = "disabled";
549		};
550
551		adc1: adc@400a4000 {
552			compatible = "nxp,s32-adc-sar";
553			reg = <0x400a4000 0x1000>;
554			interrupts = <181 0>;
555			#io-channel-cells = <1>;
556			status = "disabled";
557		};
558
559		adc2: adc@400a8000 {
560			compatible = "nxp,s32-adc-sar";
561			reg = <0x400a8000 0x1000>;
562			interrupts = <182 0>;
563			#io-channel-cells = <1>;
564			status = "disabled";
565		};
566
567		lpspi0: spi@40358000 {
568			compatible = "nxp,lpspi";
569			reg = <0x40358000 0x4000>;
570			interrupts = <165 0>;
571			clocks = <&clock NXP_S32_LPSPI0_CLK>;
572			#address-cells = <1>;
573			#size-cells = <0>;
574			tx-fifo-size = <4>;
575			rx-fifo-size = <4>;
576			status = "disabled";
577		};
578
579		lpspi1: spi@4035c000 {
580			compatible = "nxp,lpspi";
581			reg = <0x4035c000 0x4000>;
582			interrupts = <166 0>;
583			clocks = <&clock NXP_S32_LPSPI1_CLK>;
584			#address-cells = <1>;
585			#size-cells = <0>;
586			tx-fifo-size = <4>;
587			rx-fifo-size = <4>;
588			status = "disabled";
589		};
590
591		lpspi2: spi@40360000 {
592			compatible = "nxp,lpspi";
593			reg = <0x40360000 0x4000>;
594			interrupts = <167 0>;
595			clocks = <&clock NXP_S32_LPSPI2_CLK>;
596			#address-cells = <1>;
597			#size-cells = <0>;
598			tx-fifo-size = <4>;
599			rx-fifo-size = <4>;
600			status = "disabled";
601		};
602
603		lpspi3: spi@40364000 {
604			compatible = "nxp,lpspi";
605			reg = <0x40364000 0x4000>;
606			interrupts = <168 0>;
607			clocks = <&clock NXP_S32_LPSPI3_CLK>;
608			#address-cells = <1>;
609			#size-cells = <0>;
610			tx-fifo-size = <4>;
611			rx-fifo-size = <4>;
612			status = "disabled";
613		};
614
615		lpspi4: spi@404bc000 {
616			compatible = "nxp,lpspi";
617			reg = <0x404bc000 0x4000>;
618			interrupts = <169 0>;
619			clocks = <&clock NXP_S32_LPSPI4_CLK>;
620			#address-cells = <1>;
621			#size-cells = <0>;
622			tx-fifo-size = <4>;
623			rx-fifo-size = <4>;
624			status = "disabled";
625		};
626
627		lpspi5: spi@404c0000 {
628			compatible = "nxp,lpspi";
629			reg = <0x404c0000 0x4000>;
630			interrupts = <170 0>;
631			clocks = <&clock NXP_S32_LPSPI5_CLK>;
632			#address-cells = <1>;
633			#size-cells = <0>;
634			tx-fifo-size = <4>;
635			rx-fifo-size = <4>;
636			status = "disabled";
637		};
638
639		emac0: ethernet@40480000 {
640			reg = <0x40480000 0x4000>;
641			compatible = "nxp,s32-gmac";
642			interrupts = <105 0>, <106 0>, <107 0>, <108 0>;
643			interrupt-names = "common", "tx", "rx", "safety";
644			status = "disabled";
645		};
646
647		mdio0: mdio@40480200 {
648			reg = <0x40480200 0x8>;
649			compatible = "nxp,s32-gmac-mdio";
650			clocks = <&clock NXP_S32_AIPS_PLAT_CLK>;
651			#address-cells = <1>;
652			#size-cells = <0>;
653			status = "disabled";
654		};
655
656		edma0: dma-controller@4020c000 {
657			compatible = "nxp,mcux-edma";
658			nxp,version = <3>;
659			reg = <0x4020c000 0x3000>, <0x40280000 0x4000>, <0x40284000 0x4000>;
660			dma-channels = <32>;
661			dma-requests = <64>;
662			dmamux-reg-offset = <3>;
663			channel-gap = <12 127>;
664			#dma-cells = <2>;
665			nxp,mem2mem;
666			interrupts = <4 0>, <5 0>, <6 0>, <7 0>,
667				     <8 0>, <9 0>, <10 0>, <11 0>,
668				     <12 0>, <13 0>, <14 0>, <15 0>,
669				     <16 0>, <17 0>, <18 0>, <19 0>,
670				     <20 0>, <21 0>, <22 0>, <23 0>,
671				     <24 0>, <25 0>, <26 0>, <27 0>,
672				     <28 0>, <29 0>, <30 0>, <31 0>,
673				     <32 0>, <33 0>, <34 0>, <35 0>;
674			no-error-irq;
675			status = "disabled";
676		};
677
678		emios0: emios@40088000 {
679			compatible = "nxp,s32-emios";
680			reg = <0x40088000 0x4000>;
681			clocks = <&clock NXP_S32_EMIOS0_CLK>;
682			interrupts = <61 0>, <62 0>, <63 0>,
683					<64 0>, <65 0>, <66 0>;
684			interrupt-names = "0_0", "0_1", "0_2",
685					"0_3", "0_4", "0_5";
686			internal-cnt = <0xC101FF>;
687			status = "disabled";
688
689			master_bus {
690				emios0_bus_a: emios0_bus_a {
691					channel = <23>;
692					bus-type = "BUS_A";
693					channel-mask = <0x07FFFFF>;
694					status = "disabled";
695				};
696
697				emios0_bus_b: emios0_bus_b {
698					channel = <0>;
699					bus-type = "BUS_B";
700					channel-mask = <0x00000FE>;
701					status = "disabled";
702				};
703
704				emios0_bus_c: emios0_bus_c {
705					channel = <8>;
706					bus-type = "BUS_C";
707					channel-mask = <0x0000FE00>;
708					status = "disabled";
709				};
710
711				emios0_bus_d: emios0_bus_d {
712					channel = <16>;
713					bus-type = "BUS_D";
714					channel-mask = <0x00FE0000>;
715					status = "disabled";
716				};
717
718				emios0_bus_f: emios0_bus_f {
719					channel = <22>;
720					bus-type = "BUS_F";
721					channel-mask = <0x0BFFFFF>;
722					status = "disabled";
723				};
724			};
725
726			pwm {
727				compatible = "nxp,s32-emios-pwm";
728				#pwm-cells = <3>;
729				status = "disabled";
730			};
731		};
732
733		emios1: emios@4008c000 {
734			compatible = "nxp,s32-emios";
735			reg = <0x4008c000 0x4000>;
736			clocks = <&clock NXP_S32_EMIOS1_CLK>;
737			interrupts = <69 0>, <70 0>, <71 0>,
738					<72 0>, <73 0>, <74 0>;
739			interrupt-names = "1_0", "1_1", "1_2",
740					"1_3", "1_4", "1_5";
741			internal-cnt = <0xC10101>;
742			status = "disabled";
743
744			master_bus {
745				emios1_bus_a: emios1_bus_a {
746					channel = <23>;
747					bus-type = "BUS_A";
748					channel-mask = <0x07FFFFF>;
749					status = "disabled";
750				};
751
752				emios1_bus_b: emios1_bus_b {
753					channel = <0>;
754					bus-type = "BUS_B";
755					channel-mask = <0x00000FE>;
756					status = "disabled";
757				};
758
759				emios1_bus_c: emios1_bus_c {
760					channel = <8>;
761					bus-type = "BUS_C";
762					channel-mask = <0x0000FE00>;
763					status = "disabled";
764				};
765
766				emios1_bus_d: emios1_bus_d {
767					channel = <16>;
768					bus-type = "BUS_D";
769					channel-mask = <0x00FE0000>;
770					status = "disabled";
771				};
772
773				emios1_bus_f: emios1_bus_f {
774					channel = <22>;
775					channel-mask = <0x0BFFFFF>;
776					bus-type = "BUS_F";
777					status = "disabled";
778				};
779			};
780
781			pwm {
782				compatible = "nxp,s32-emios-pwm";
783				#pwm-cells = <3>;
784				status = "disabled";
785			};
786		};
787
788		emios2: emios@40090000 {
789			compatible = "nxp,s32-emios";
790			reg = <0x40090000 0x4000>;
791			clocks = <&clock NXP_S32_EMIOS2_CLK>;
792			interrupts = <77 0>, <78 0>, <79 0>,
793					<80 0>, <81 0>, <82 0>;
794			interrupt-names = "2_0", "2_1", "2_2",
795					"2_3", "2_4", "2_5";
796			internal-cnt = <0xC10101>;
797			status = "disabled";
798
799			master_bus {
800				emios2_bus_a: emios2_bus_a {
801					channel = <23>;
802					bus-type = "BUS_A";
803					channel-mask = <0x07FFFFF>;
804					status = "disabled";
805				};
806
807				emios2_bus_b: emios2_bus_b {
808					channel = <0>;
809					bus-type = "BUS_B";
810					channel-mask = <0x00000FE>;
811					status = "disabled";
812				};
813
814				emios2_bus_c: emios2_bus_c {
815					channel = <8>;
816					bus-type = "BUS_C";
817					channel-mask = <0x0000FE00>;
818					status = "disabled";
819				};
820
821				emios2_bus_d: emios2_bus_d {
822					channel = <16>;
823					bus-type = "BUS_D";
824					channel-mask = <0x00FE0000>;
825					status = "disabled";
826				};
827
828				emios2_bus_f: emios2_bus_f {
829					channel = <22>;
830					bus-type = "BUS_F";
831					channel-mask = <0x0BFFFFF>;
832					status = "disabled";
833				};
834			};
835
836			pwm {
837				compatible = "nxp,s32-emios-pwm";
838				#pwm-cells = <3>;
839				status = "disabled";
840			};
841		};
842
843		flexio0: flexio@40324000 {
844			compatible = "nxp,flexio";
845			reg = <0x40324000 0x4000>;
846			interrupts = <139 0>;
847			clocks = <&clock NXP_S32_FLEXIO0_CLK>;
848			status = "disabled";
849
850			flexio0_pwm {
851				compatible = "nxp,flexio-pwm";
852				#pwm-cells = <3>;
853				status = "disabled";
854			};
855		};
856
857		lcu0: lcu@40098000 {
858			compatible = "nxp,s32-lcu";
859			reg = <0x40098000 0x4000>;
860			status = "disabled";
861		};
862
863		lcu1: lcu@4009c000 {
864			compatible = "nxp,s32-lcu";
865			reg = <0x4009c000 0x4000>;
866			status = "disabled";
867		};
868
869		trgmux: trgmux@40080000 {
870			compatible = "nxp,s32-trgmux";
871			reg = <0x40080000 0x4000>;
872			status = "disabled";
873		};
874
875		pmc: pmc@402e8000 {
876			compatible = "nxp,s32k3-pmc";
877			reg = <0x402e8000 0x4000>;
878		};
879
880		mc_me: mc_me@402dc000 {
881			compatible = "nxp,s32-mc-me";
882			reg = <0x402dc000 0x4000>;
883		};
884
885		mc_rgm: mc_rgm@4028c000 {
886			compatible = "nxp,s32-mc-rgm";
887			reg = <0x4028c000 0x4000>;
888			func-reset-threshold = <0>;
889			dest-reset-threshold = <0>;
890		};
891
892		swt0: watchdog@40270000 {
893			compatible = "nxp,s32-swt";
894			reg = <0x40270000 0x4000>;
895			interrupts = <42 0>;
896			clocks = <&clock NXP_S32_SIRC_CLK>;
897			service-mode = "fixed";
898			status = "okay";
899		};
900
901		stm0: stm@40274000 {
902			compatible = "nxp,s32-sys-timer";
903			reg = <0x40274000 0x10000>;
904			interrupts = <39 0>;
905			clocks = <&clock NXP_S32_STM0_CLK>;
906			status = "disabled";
907		};
908
909		stm1: stm@40474000 {
910			compatible = "nxp,s32-sys-timer";
911			reg = <0x40474000 0x10000>;
912			interrupts = <40 0>;
913			clocks = <&clock NXP_S32_STM1_CLK>;
914			status = "disabled";
915		};
916	};
917};
918
919&nvic {
920	arm,num-irq-priority-bits = <4>;
921};
922