1/* 2 * Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/i2c/i2c.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/clock/atmel_sam_pmc.h> 11 12/ { 13 aliases { 14 watchdog0 = &wdt; 15 }; 16 17 chosen { 18 zephyr,flash-controller = &flashcalw; 19 zephyr,entropy = &trng; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-m4"; 29 reg = <0>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 mpu: mpu@e000ed90 { 34 compatible = "arm,armv7m-mpu"; 35 reg = <0xe000ed90 0x40>; 36 }; 37 }; 38 }; 39 40 sram0: memory@20000000 { 41 compatible = "mmio-sram"; 42 }; 43 44 /** 45 * HRAM1 are 4k SRAM that can be used by PicoCache or just extra 46 * memory available. The PicoCache will be keep disable to ensures 47 * deterministic behaviour. That way the extra memory can be 48 * exclusive for USB descriptors 49 */ 50 sram1: memory@21000000 { 51 compatible = "zephyr,memory-region", "mmio-sram"; 52 reg = <0x21000000 DT_SIZE_K(4)>; 53 zephyr,memory-region = "SRAM1"; 54 }; 55 56 soc { 57 pmc: pmc@400e0000 { 58 compatible = "atmel,sam-pmc"; 59 reg = <0x400e0000 0x740>; 60 interrupts = <22 0>; 61 #clock-cells = <2>; 62 status = "okay"; 63 }; 64 65 flashcalw: flash-controller@400a0000 { 66 compatible = "atmel,sam4l-flashcalw-controller"; 67 reg = <0x400a0000 0x400>; 68 interrupts = <0 0>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 72 flash0: flash@0 { 73 compatible = "soc-nv-flash"; 74 75 write-block-size = <8>; 76 erase-block-size = <512>; 77 }; 78 79 /* 80 * No driver implemented yet, keeped it disabled 81 */ 82 status = "disabled"; 83 }; 84 85 twim0: twim@40018000 { 86 compatible = "atmel,sam-i2c-twim"; 87 clock-frequency = <I2C_BITRATE_STANDARD>; 88 reg = <0x40018000 0x4000>; 89 interrupts = <61 0>; 90 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 91 status = "disabled"; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 }; 95 twim1: twim@4001c000 { 96 compatible = "atmel,sam-i2c-twim"; 97 clock-frequency = <I2C_BITRATE_STANDARD>; 98 reg = <0x4001c000 0x4000>; 99 interrupts = <63 0>; 100 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 101 status = "disabled"; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 }; 105 twim2: twim@40078000 { 106 compatible = "atmel,sam-i2c-twim"; 107 clock-frequency = <I2C_BITRATE_STANDARD>; 108 reg = <0x40078000 0x4000>; 109 interrupts = <77 0>; 110 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 111 status = "disabled"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 }; 115 twim3: twim@4007c000 { 116 compatible = "atmel,sam-i2c-twim"; 117 clock-frequency = <I2C_BITRATE_STANDARD>; 118 reg = <0x4007c000 0x4000>; 119 interrupts = <78 0>; 120 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 121 status = "disabled"; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 }; 125 126 spi0: spi@40008000 { 127 compatible = "atmel,sam-spi"; 128 reg = <0x40008000 0x4000>; 129 interrupts = <54 0>; 130 clocks = <&pmc PMC_TYPE_PERIPHERAL 1>; 131 status = "disabled"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 }; 135 136 usart0: usart@40024000 { 137 compatible = "atmel,sam-usart"; 138 reg = <0x40024000 0x4000>; 139 interrupts = <65 1>; 140 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 141 status = "disabled"; 142 }; 143 usart1: usart@40028000 { 144 compatible = "atmel,sam-usart"; 145 reg = <0x40028000 0x4000>; 146 interrupts = <66 1>; 147 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 148 status = "disabled"; 149 }; 150 usart2: usart@4002c000 { 151 compatible = "atmel,sam-usart"; 152 reg = <0x4002c000 0x4000>; 153 interrupts = <67 1>; 154 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 155 status = "disabled"; 156 }; 157 usart3: usart@40030000 { 158 compatible = "atmel,sam-usart"; 159 reg = <0x40030000 0x4000>; 160 interrupts = <68 1>; 161 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 162 status = "disabled"; 163 }; 164 165 usbc: usbd@400a5000 { 166 compatible = "atmel,sam-usbc"; 167 reg = <0x400a5000 0x1000>; 168 interrupts = <18 5>; 169 interrupt-names = "usbc"; 170 maximum-speed = "full-speed"; 171 num-bidir-endpoints = <8>; 172 clocks = <&pmc PMC_TYPE_PERIPHERAL 101>; 173 status = "disabled"; 174 }; 175 176 pinctrl: pinctrl@400e1000 { 177 compatible = "atmel,sam-pinctrl"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0x400e1000 0x400e1000 0x800>; 181 182 gpioa: gpio@400e1000 { 183 compatible = "atmel,sam4l-gpio"; 184 reg = <0x400e1000 0x200>; 185 interrupts = <25 1>, <26 1>, <27 1>, <28 1>; 186 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 187 gpio-controller; 188 #gpio-cells = <2>; 189 #atmel,pin-cells = <2>; 190 }; 191 gpiob: gpio@400e1200 { 192 compatible = "atmel,sam4l-gpio"; 193 reg = <0x400e1200 0x200>; 194 interrupts = <29 1>, <30 1>, <31 1>, <32 1>; 195 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 #atmel,pin-cells = <2>; 199 }; 200 gpioc: gpio@400e1400 { 201 compatible = "atmel,sam4l-gpio"; 202 reg = <0x400e1400 0x200>; 203 interrupts = <33 1>, <34 1>, <35 1>, <36 1>; 204 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 #atmel,pin-cells = <2>; 208 }; 209 }; 210 211 tc0: tc@40010000 { 212 compatible = "atmel,sam-tc"; 213 reg = <0x40010000 0x100>; 214 interrupts = <55 0 215 56 0 216 57 0>; 217 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 218 status = "disabled"; 219 }; 220 221 tc1: tc@40014000 { 222 compatible = "atmel,sam-tc"; 223 reg = <0x40014000 0x100>; 224 interrupts = <58 0 225 59 0 226 60 0>; 227 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 228 status = "disabled"; 229 }; 230 231 trng: random@40068000 { 232 compatible = "atmel,sam-trng"; 233 reg = <0x40068000 0x4000>; 234 interrupts = <73 0>; 235 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 236 status = "okay"; 237 }; 238 239 uid: device_uid@80020c { 240 compatible = "atmel,sam4l-uid"; 241 reg = <0x80020c 0xf>; 242 status = "okay"; 243 }; 244 245 wdt: watchdog@400f0c00 { 246 compatible = "atmel,sam4l-watchdog"; 247 reg = <0x400f0c00 0x400>; 248 interrupts = <44 1>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 99>; 250 status = "okay"; 251 }; 252 }; 253}; 254 255&nvic { 256 arm,num-irq-priority-bits = <4>; 257}; 258
