1 /*
2  * Copyright (c) 2022 Intel Corporation
3  * Copyright (c) 2025 Croxel Inc.
4  * Copyright (c) 2025 CogniPilot Foundation
5  *
6  * SPDX-License-Identifier: Apache-2.0
7  */
8 
9 #ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_REG_H_
10 #define ZEPHYR_DRIVERS_SENSOR_ICM45686_REG_H_
11 
12 #include <zephyr/sys/util.h>
13 #include <zephyr/sys/byteorder.h>
14 
15 /* Address value has a read bit */
16 #define REG_SPI_READ_BIT BIT(7)
17 
18 /* Registers */
19 /* Register Bank 0 */
20 #define REG_ACCEL_DATA_X1_UI			0x00
21 #define REG_ACCEL_DATA_X0_UI			0x01
22 #define REG_ACCEL_DATA_Y1_UI			0x02
23 #define REG_ACCEL_DATA_Y0_UI			0x03
24 #define REG_ACCEL_DATA_Z1_UI			0x04
25 #define REG_ACCEL_DATA_Z0_UI			0x05
26 #define REG_GYRO_DATA_X1_UI			0x06
27 #define REG_GYRO_DATA_X0_UI			0x07
28 #define REG_GYRO_DATA_Y1_UI			0x08
29 #define REG_GYRO_DATA_Y0_UI			0x09
30 #define REG_GYRO_DATA_Z1_UI			0x0A
31 #define REG_GYRO_DATA_Z0_UI			0x0B
32 #define REG_TEMP_DATA1_UI			0x0C
33 #define REG_TEMP_DATA0_UI			0x0D
34 #define REG_PWR_MGMT0				0x10
35 #define REG_FIFO_COUNT_0			0x12
36 #define REG_FIFO_COUNT_1			0x13
37 #define REG_FIFO_DATA				0x14
38 #define REG_INT1_CONFIG0			0x16
39 #define REG_INT1_CONFIG1			0x17
40 #define REG_INT1_CONFIG2			0x18
41 #define REG_INT1_STATUS0			0x19
42 #define REG_INT1_STATUS1			0x1A
43 #define REG_ACCEL_CONFIG0			0x1B
44 #define REG_GYRO_CONFIG0			0x1C
45 #define REG_FIFO_CONFIG0			0x1D
46 #define REG_FIFO_CONFIG1_0			0x1E
47 #define REG_FIFO_CONFIG1_1			0x1F
48 #define REG_FIFO_CONFIG2			0x20
49 #define REG_FIFO_CONFIG3			0x21
50 #define REG_FIFO_CONFIG4			0x22
51 #define REG_DRIVE_CONFIG0			0x32
52 #define REG_WHO_AM_I				0x72
53 #define REG_IREG_ADDR_15_8			0x7C
54 #define REG_IREG_ADDR_7_0			0x7D
55 #define REG_IREG_DATA				0x7E
56 #define REG_MISC2				0x7F
57 
58 /* User Bank IPREG_SYS1 - Gyro-related config settings */
59 #define REG_IPREG_SYS1_OFFSET			0xA400
60 #define REG_IPREG_SYS1_REG_172			0xAC
61 
62 /* User Bank IPREG_SYS2 - Accel-related config settings */
63 #define REG_IPREG_SYS2_OFFSET			0xA500
64 #define REG_IPREG_SYS2_REG_131			0x83
65 
66 /* Helper Macros for register manipulation */
67 #define REG_PWR_MGMT0_ACCEL_MODE(val)			((val) & BIT_MASK(2))
68 #define REG_PWR_MGMT0_GYRO_MODE(val)			(((val) & BIT_MASK(2)) << 2)
69 
70 #define REG_ACCEL_CONFIG0_ODR(val)			((val) & BIT_MASK(4))
71 #define REG_ACCEL_CONFIG0_FS(val)			(((val) & BIT_MASK(3)) << 4)
72 
73 #define REG_GYRO_CONFIG0_ODR(val)			((val) & BIT_MASK(4))
74 #define REG_GYRO_CONFIG0_FS(val)			(((val) & BIT_MASK(4)) << 4)
75 
76 #define REG_DRIVE_CONFIG0_SPI_SLEW(val)			(((val) & BIT_MASK(2)) << 1)
77 
78 #define REG_MISC2_SOFT_RST(val)				((val << 1) & BIT(1))
79 
80 #define REG_IPREG_SYS1_REG_172_GYRO_LPFBW_SEL(val)	(val & BIT_MASK(3))
81 
82 #define REG_IPREG_SYS2_REG_131_ACCEL_LPFBW_SEL(val)	(val & BIT_MASK(3))
83 
84 #define REG_INT1_CONFIG0_STATUS_EN_DRDY(val)		(((val) & BIT_MASK(1)) << 2)
85 #define REG_INT1_CONFIG0_STATUS_EN_FIFO_THS(val)	(((val) & BIT_MASK(1)) << 1)
86 #define REG_INT1_CONFIG0_STATUS_EN_FIFO_FULL(val)	((val) & BIT_MASK(1))
87 
88 #define REG_INT1_CONFIG2_EN_OPEN_DRAIN(val)		(((val) & BIT_MASK(1)) << 2)
89 #define REG_INT1_CONFIG2_EN_LATCH_MODE(val)		(((val) & BIT_MASK(1)) << 1)
90 #define REG_INT1_CONFIG2_EN_ACTIVE_HIGH(val)		((val) & BIT_MASK(1))
91 
92 #define REG_INT1_STATUS0_DRDY(val)			(((val) & BIT_MASK(1)) << 2)
93 #define REG_INT1_STATUS0_FIFO_THS(val)			(((val) & BIT_MASK(1)) << 1)
94 #define REG_INT1_STATUS0_FIFO_FULL(val)			((val) & BIT_MASK(1))
95 
96 #define REG_FIFO_CONFIG0_FIFO_MODE_BYPASS		0
97 #define REG_FIFO_CONFIG0_FIFO_MODE_STREAM		1
98 #define REG_FIFO_CONFIG0_FIFO_MODE_STOP_ON_FULL		2
99 
100 #define REG_FIFO_CONFIG0_FIFO_DEPTH_2K			0x07
101 #define REG_FIFO_CONFIG0_FIFO_DEPTH_8K			0x1F
102 
103 #define REG_FIFO_CONFIG0_FIFO_MODE(val)			(((val) & BIT_MASK(2)) << 6)
104 #define REG_FIFO_CONFIG0_FIFO_DEPTH(val)		((val) & BIT_MASK(6))
105 
106 #define REG_FIFO_CONFIG1_0_FIFO_WM_THS(val)		((val) & BIT_MASK(8))
107 #define REG_FIFO_CONFIG1_1_FIFO_WM_THS(val)		(((val) >> 8) & BIT_MASK(8))
108 
109 #define REG_FIFO_CONFIG2_FIFO_FLUSH(val)		(((val) & BIT_MASK(1)) << 7)
110 #define REG_FIFO_CONFIG2_FIFO_WM_GT_THS(val)		(((val) & BIT_MASK(1)) << 3)
111 
112 #define REG_FIFO_CONFIG3_FIFO_HIRES_EN(val)		(((val) & BIT_MASK(1)) << 3)
113 #define REG_FIFO_CONFIG3_FIFO_GYRO_EN(val)		(((val) & BIT_MASK(1)) << 2)
114 #define REG_FIFO_CONFIG3_FIFO_ACCEL_EN(val)		(((val) & BIT_MASK(1)) << 1)
115 #define REG_FIFO_CONFIG3_FIFO_EN(val)			((val) & BIT_MASK(1))
116 
117 /* Misc. Defines */
118 #define WHO_AM_I_ICM45686 0xE9
119 
120 #define REG_IREG_PREPARE_WRITE_ARRAY(base, reg, val)	{((base) >> 8) & 0xFF, reg, val}
121 
122 #define FIFO_HEADER_EXT_HEADER_EN(val)			(((val) & BIT_MASK(1)) << 7)
123 #define FIFO_HEADER_ACCEL_EN(val)			(((val) & BIT_MASK(1)) << 6)
124 #define FIFO_HEADER_GYRO_EN(val)			(((val) & BIT_MASK(1)) << 5)
125 #define FIFO_HEADER_HIRES_EN(val)			(((val) & BIT_MASK(1)) << 4)
126 
127 #define FIFO_NO_DATA					0x8000
128 #define FIFO_COUNT_MAX_HIGH_RES				104
129 
130 #endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_REG_H_ */
131