1 /* 2 * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_REG_H 7 #define ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_REG_H 8 9 #include <zephyr/sys/util_macro.h> 10 /* REGISTERS */ 11 /* Status and measurent output */ 12 #define MLX90394_REG_STAT1 0x00 13 #define MLX90394_REG_BXL 0x01 14 #define MLX90394_REG_BXH 0x02 15 #define MLX90394_REG_BYL 0x03 16 #define MLX90394_REG_BYH 0x04 17 #define MLX90394_REG_BZL 0x05 18 #define MLX90394_REG_BZH 0x06 19 #define MLX90394_REG_STAT2 0x07 20 #define MLX90394_REG_TL 0x08 21 #define MLX90394_REG_TH 0x09 22 23 /* Who Am I registers */ 24 #define MLX90394_REG_CID 0x0A 25 #define MLX90394_REG_DID 0x0B 26 27 /* Control registers */ 28 #define MLX90394_REG_CTRL1 0x0E 29 #define MLX90394_REG_CTRL2 0x0F 30 #define MLX90394_REG_CTRL3 0x14 31 #define MLX90394_REG_CTRL4 0x15 32 33 /* Reset register */ 34 #define MLX90394_REG_RST 0x11 35 36 /* Wake On Change registers */ 37 #define MLX90394_REG_WOC_XL 0x58 38 #define MLX90394_REG_WOC_XH 0x59 39 #define MLX90394_REG_WOC_YL 0x5A 40 #define MLX90394_REG_WOC_YH 0x5B 41 #define MLX90394_REG_WOC_ZL 0x5C 42 #define MLX90394_REG_WOC_ZH 0x5D 43 44 /* VALUES */ 45 /* STAT1 values RO */ 46 #define MLX90394_STAT1_DRDY BIT(0) 47 #define MLX90394_STAT1_DOR BIT(3) 48 #define MLX90394_STAT1_RT BIT(3) 49 #define MLX90394_STAT1_INT BIT(4) 50 #define MLX90394_STAT1_DEFAULT (MLX90394_STAT1_RT) 51 52 /* STAT2 values RO */ 53 #define MLX90394_STAT2_HOVF_X BIT(0) 54 #define MLX90394_STAT2_HOVF_Y BIT(1) 55 #define MLX90394_STAT2_HOVF_Z BIT(2) 56 #define MLX90394_STAT2_DOR BIT(3) 57 #define MLX90394_STAT2_DEFAULT 0 58 59 /* Who-I-Am register values RO */ 60 #define MLX90394_CID 0x94 61 #define MLX90394_DID 0xaa 62 63 /* Write this value to reset Register soft resets the chip RW */ 64 #define MLX90394_RST 0x06 65 66 /* CTRL1 values RW */ 67 #define MLX90394_CTRL1_X_EN_BIT 4 68 #define MLX90394_CTRL1_Y_EN_BIT 5 69 #define MLX90394_CTRL1_Z_EN_BIT 6 70 #define MLX90394_CTRL1_MODE GENMASK(3, 0) 71 #define MLX90394_CTRL1_MODE_SINGLE 1 72 #define MLX90394_CTRL1_X_EN BIT(MLX90394_CTRL1_X_EN_BIT) 73 #define MLX90394_CTRL1_Y_EN BIT(MLX90394_CTRL1_Y_EN_BIT) 74 #define MLX90394_CTRL1_Z_EN BIT(MLX90394_CTRL1_Z_EN_BIT) 75 #define MLX90394_CTRL1_SWOK BIT(7) 76 #define MLX90394_CTRL1_PREP(MODE, X_EN, Y_EN, Z_EN, SWOK) \ 77 (FIELD_PREP(MLX90394_CTRL1_MODE, MODE) | FIELD_PREP(MLX90394_CTRL1_X_EN, X_EN) | \ 78 FIELD_PREP(MLX90394_CTRL1_Y_EN, Y_EN) | FIELD_PREP(MLX90394_CTRL1_Z_EN, Z_EN) | \ 79 FIELD_PREP(MLX90394_CTRL1_SWOK, SWOK)) 80 #define MLX90394_CTRL1_DEFAULT MLX90394_CTRL1_PREP(0, 1, 1, 1, 0) 81 82 /* CTRL2 values RW */ 83 enum mlx90394_reg_config_val { 84 MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_CURRENT = 0, 85 MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE, 86 MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE 87 }; 88 #define MLX90394_CTRL2_WOC_MODE GENMASK(1, 0) 89 #define MLX90394_CTRL2_INTREPB BIT(2) 90 #define MLX90394_CTRL2_INTB_SCL_B BIT(3) 91 #define MLX90394_CTRL2_INTDUR GENMASK(5, 4) 92 #define MLX90394_CTRL2_CONFIG GENMASK(7, 6) 93 #define MLX90394_CTRL2_PREP(WOC_MODE, INTREPB, INTB_SCL_B, INTDUR, CONFIG) \ 94 (FIELD_PREP(MLX90394_CTRL2_WOC_MODE, WOC_MODE) | \ 95 FIELD_PREP(MLX90394_CTRL2_INTREPB, INTREPB) | \ 96 FIELD_PREP(MLX90394_CTRL2_INTB_SCL_B, INTB_SCL_B) | \ 97 FIELD_PREP(MLX90394_CTRL2_INTDUR, INTDUR) | FIELD_PREP(MLX90394_CTRL2_CONFIG, CONFIG)) 98 #define MLX90394_CTRL2_DEFAULT \ 99 MLX90394_CTRL2_PREP(0, 0, 1, 0, MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE) 100 101 /* CTRL3 values RW */ 102 #define MLX90394_CTRL3_DIG_FILT_TEMP GENMASK(2, 0) 103 #define MLX90394_CTRL3_DIG_FILT_HALL_XY GENMASK(5, 3) 104 #define MLX90394_CTRL3_OSR_TEMP BIT(6) 105 #define MLX90394_CTRL3_OSR_HALL BIT(7) 106 #define MLX90394_CTRL3_PREP(DIG_FILT_TEMP, DIG_FILT_HALL_XY, OSR_TEMP, OSR_HALL) \ 107 (FIELD_PREP(MLX90394_CTRL3_DIG_FILT_TEMP, DIG_FILT_TEMP) | \ 108 FIELD_PREP(MLX90394_CTRL3_DIG_FILT_HALL_XY, DIG_FILT_HALL_XY) | \ 109 FIELD_PREP(MLX90394_CTRL3_OSR_TEMP, OSR_TEMP) | \ 110 FIELD_PREP(MLX90394_CTRL3_OSR_HALL, OSR_HALL)) 111 #define MLX90394_CTRL3_DEFAULT MLX90394_CTRL3_PREP(1, 4, 1, 1) 112 113 /* CTRL4 values RW BIT(6) has to be always 0 so it is not included here */ 114 #define MLX90394_CTRL4_T_EN_BIT 5 115 #define MLX90394_CTRL4_DIG_FILT_HALL_Z GENMASK(2, 0) 116 #define MLX90394_CTRL4_DRDY_EN BIT(3) 117 #define MLX90394_CTRL4_T_EN BIT(MLX90394_CTRL4_T_EN_BIT) 118 #define MLX90394_CTRL4_PREP(DIG_FILT_HALL_Z, DRDY_EN, T_EN) \ 119 (FIELD_PREP(MLX90394_CTRL4_DIG_FILT_HALL_Z, DIG_FILT_HALL_Z) | \ 120 FIELD_PREP(MLX90394_CTRL4_DRDY_EN, DRDY_EN) | FIELD_PREP(MLX90394_CTRL4_T_EN, T_EN) | \ 121 BIT(4) | BIT(7)) 122 #define MLX90394_CTRL4_DEFAULT MLX90394_CTRL4_PREP(5, 0, 0) 123 124 /* helper function to modify only one field */ 125 #define MLX90394_FIELD_MOD(mask, new_field_val, val) \ 126 ((val & ~mask) | FIELD_PREP(mask, new_field_val)) 127 128 #endif /* ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_REG_H */ 129
