1 /*
2 * Copyright (c) 2021 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/drivers/pinctrl.h>
8
9 #include <hal/nrf_gpio.h>
10 #ifdef CONFIG_SOC_NRF54H20_GPD
11 #include <nrf/gpd.h>
12 #endif
13
14 BUILD_ASSERT(((NRF_PULL_NONE == NRF_GPIO_PIN_NOPULL) &&
15 (NRF_PULL_DOWN == NRF_GPIO_PIN_PULLDOWN) &&
16 (NRF_PULL_UP == NRF_GPIO_PIN_PULLUP)),
17 "nRF pinctrl pull settings do not match HAL values");
18
19 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(GPIO_PIN_CNF_DRIVE0_E0)
20 #define NRF_DRIVE_COUNT (NRF_DRIVE_E0E1 + 1)
21 #else
22 #define NRF_DRIVE_COUNT (NRF_DRIVE_H0D1 + 1)
23 #endif
24 static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
25 [NRF_DRIVE_S0S1] = NRF_GPIO_PIN_S0S1,
26 [NRF_DRIVE_H0S1] = NRF_GPIO_PIN_H0S1,
27 [NRF_DRIVE_S0H1] = NRF_GPIO_PIN_S0H1,
28 [NRF_DRIVE_H0H1] = NRF_GPIO_PIN_H0H1,
29 [NRF_DRIVE_D0S1] = NRF_GPIO_PIN_D0S1,
30 [NRF_DRIVE_D0H1] = NRF_GPIO_PIN_D0H1,
31 [NRF_DRIVE_S0D1] = NRF_GPIO_PIN_S0D1,
32 [NRF_DRIVE_H0D1] = NRF_GPIO_PIN_H0D1,
33 #if defined(GPIO_PIN_CNF_DRIVE_E0E1) || defined(GPIO_PIN_CNF_DRIVE0_E0)
34 [NRF_DRIVE_E0E1] = NRF_GPIO_PIN_E0E1,
35 #endif
36 };
37
38 /* value to indicate pin level doesn't need initialization */
39 #define NO_WRITE UINT32_MAX
40
41 #define PSEL_DISCONNECTED 0xFFFFFFFFUL
42
43 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uart) || defined(CONFIG_NRFX_UART)
44 #define NRF_PSEL_UART(reg, line) ((NRF_UART_Type *)reg)->PSEL##line
45 #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_uarte) || defined(CONFIG_NRFX_UARTE)
46 #include <hal/nrf_uarte.h>
47 #define NRF_PSEL_UART(reg, line) ((NRF_UARTE_Type *)reg)->PSEL.line
48 #endif
49
50 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spi) || defined(CONFIG_NRFX_SPI)
51 #define NRF_PSEL_SPIM(reg, line) ((NRF_SPI_Type *)reg)->PSEL##line
52 #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spim) || defined(CONFIG_NRFX_SPIM)
53 #include <hal/nrf_spim.h>
54 #define NRF_PSEL_SPIM(reg, line) ((NRF_SPIM_Type *)reg)->PSEL.line
55 #endif
56
57 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_spis) || defined(CONFIG_NRFX_SPIS)
58 #include <hal/nrf_spis.h>
59 #if defined(NRF51)
60 #define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL##line
61 #else
62 #define NRF_PSEL_SPIS(reg, line) ((NRF_SPIS_Type *)reg)->PSEL.line
63 #endif
64 #endif
65
66 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twi) || defined(CONFIG_NRFX_TWI)
67 #if !defined(TWI_PSEL_SCL_CONNECT_Pos)
68 #define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL##line
69 #else
70 #define NRF_PSEL_TWIM(reg, line) ((NRF_TWI_Type *)reg)->PSEL.line
71 #endif
72 #elif DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twim) || defined(CONFIG_NRFX_TWIM)
73 #include <hal/nrf_twim.h>
74 #define NRF_PSEL_TWIM(reg, line) ((NRF_TWIM_Type *)reg)->PSEL.line
75 #endif
76
77 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_i2s) || defined(CONFIG_NRFX_I2S)
78 #define NRF_PSEL_I2S(reg, line) ((NRF_I2S_Type *)reg)->PSEL.line
79 #endif
80
81 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pdm) || defined(CONFIG_NRFX_PDM)
82 #define NRF_PSEL_PDM(reg, line) ((NRF_PDM_Type *)reg)->PSEL.line
83 #endif
84
85 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_pwm) || defined(CONFIG_NRFX_PWM)
86 #define NRF_PSEL_PWM(reg, line) ((NRF_PWM_Type *)reg)->PSEL.line
87 #endif
88
89 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qdec) || defined(CONFIG_NRFX_QDEC)
90 #define NRF_PSEL_QDEC(reg, line) ((NRF_QDEC_Type *)reg)->PSEL.line
91 #endif
92
93 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_qspi) || defined(CONFIG_NRFX_QSPI)
94 #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
95 #endif
96
97 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twis) || defined(CONFIG_NRFX_TWIS)
98 #include <hal/nrf_twis.h>
99 #define NRF_PSEL_TWIS(reg, line) ((NRF_TWIS_Type *)reg)->PSEL.line
100 #endif
101
102 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) || defined(CONFIG_NRFX_GRTC)
103 #if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_fast_frequency_hz)
104 #define NRF_GRTC_CLKOUT_FAST 1
105 #endif
106 #if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_32k)
107 #define NRF_GRTC_CLKOUT_SLOW 1
108 #endif
109 #endif
110
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)111 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
112 uintptr_t reg)
113 {
114 #ifdef CONFIG_SOC_NRF54H20_GPD
115 bool gpd_requested = false;
116 #endif
117
118 for (uint8_t i = 0U; i < pin_cnt; i++) {
119 nrf_gpio_pin_drive_t drive;
120 uint8_t drive_idx = NRF_GET_DRIVE(pins[i]);
121 uint32_t psel = NRF_GET_PIN(pins[i]);
122 uint32_t write = NO_WRITE;
123 nrf_gpio_pin_dir_t dir;
124 nrf_gpio_pin_input_t input;
125
126 if (drive_idx < ARRAY_SIZE(drive_modes)) {
127 drive = drive_modes[drive_idx];
128 } else {
129 return -EINVAL;
130 }
131
132 if (psel == NRF_PIN_DISCONNECTED) {
133 psel = PSEL_DISCONNECTED;
134 }
135
136 switch (NRF_GET_FUN(pins[i])) {
137 #if defined(NRF_PSEL_UART)
138 case NRF_FUN_UART_TX:
139 NRF_PSEL_UART(reg, TXD) = psel;
140 write = 1U;
141 dir = NRF_GPIO_PIN_DIR_OUTPUT;
142 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
143 break;
144 case NRF_FUN_UART_RX:
145 NRF_PSEL_UART(reg, RXD) = psel;
146 dir = NRF_GPIO_PIN_DIR_INPUT;
147 input = NRF_GPIO_PIN_INPUT_CONNECT;
148 break;
149 case NRF_FUN_UART_RTS:
150 NRF_PSEL_UART(reg, RTS) = psel;
151 write = 1U;
152 dir = NRF_GPIO_PIN_DIR_OUTPUT;
153 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
154 break;
155 case NRF_FUN_UART_CTS:
156 NRF_PSEL_UART(reg, CTS) = psel;
157 dir = NRF_GPIO_PIN_DIR_INPUT;
158 input = NRF_GPIO_PIN_INPUT_CONNECT;
159 break;
160 #endif /* defined(NRF_PSEL_UART) */
161 #if defined(NRF_PSEL_SPIM)
162 case NRF_FUN_SPIM_SCK:
163 NRF_PSEL_SPIM(reg, SCK) = psel;
164 write = 0U;
165 dir = NRF_GPIO_PIN_DIR_OUTPUT;
166 input = NRF_GPIO_PIN_INPUT_CONNECT;
167 break;
168 case NRF_FUN_SPIM_MOSI:
169 NRF_PSEL_SPIM(reg, MOSI) = psel;
170 write = 0U;
171 dir = NRF_GPIO_PIN_DIR_OUTPUT;
172 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
173 break;
174 case NRF_FUN_SPIM_MISO:
175 NRF_PSEL_SPIM(reg, MISO) = psel;
176 dir = NRF_GPIO_PIN_DIR_INPUT;
177 input = NRF_GPIO_PIN_INPUT_CONNECT;
178 break;
179 #endif /* defined(NRF_PSEL_SPIM) */
180 #if defined(NRF_PSEL_SPIS)
181 case NRF_FUN_SPIS_SCK:
182 NRF_PSEL_SPIS(reg, SCK) = psel;
183 dir = NRF_GPIO_PIN_DIR_INPUT;
184 input = NRF_GPIO_PIN_INPUT_CONNECT;
185 break;
186 case NRF_FUN_SPIS_MOSI:
187 NRF_PSEL_SPIS(reg, MOSI) = psel;
188 dir = NRF_GPIO_PIN_DIR_INPUT;
189 input = NRF_GPIO_PIN_INPUT_CONNECT;
190 break;
191 case NRF_FUN_SPIS_MISO:
192 NRF_PSEL_SPIS(reg, MISO) = psel;
193 dir = NRF_GPIO_PIN_DIR_INPUT;
194 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
195 break;
196 case NRF_FUN_SPIS_CSN:
197 NRF_PSEL_SPIS(reg, CSN) = psel;
198 dir = NRF_GPIO_PIN_DIR_INPUT;
199 input = NRF_GPIO_PIN_INPUT_CONNECT;
200 break;
201 #endif /* defined(NRF_PSEL_SPIS) */
202 #if defined(NRF_PSEL_TWIM)
203 case NRF_FUN_TWIM_SCL:
204 NRF_PSEL_TWIM(reg, SCL) = psel;
205 if (drive == NRF_GPIO_PIN_S0S1) {
206 /* Override the default drive setting with one
207 * suitable for TWI/TWIM peripherals (S0D1).
208 * This drive cannot be used always so that
209 * users are able to select e.g. H0D1 or E0E1
210 * in devicetree.
211 */
212 drive = NRF_GPIO_PIN_S0D1;
213 }
214 dir = NRF_GPIO_PIN_DIR_INPUT;
215 input = NRF_GPIO_PIN_INPUT_CONNECT;
216 break;
217 case NRF_FUN_TWIM_SDA:
218 NRF_PSEL_TWIM(reg, SDA) = psel;
219 if (drive == NRF_GPIO_PIN_S0S1) {
220 drive = NRF_GPIO_PIN_S0D1;
221 }
222 dir = NRF_GPIO_PIN_DIR_INPUT;
223 input = NRF_GPIO_PIN_INPUT_CONNECT;
224 break;
225 #endif /* defined(NRF_PSEL_TWIM) */
226 #if defined(NRF_PSEL_I2S)
227 case NRF_FUN_I2S_SCK_M:
228 NRF_PSEL_I2S(reg, SCK) = psel;
229 write = 0U;
230 dir = NRF_GPIO_PIN_DIR_OUTPUT;
231 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
232 break;
233 case NRF_FUN_I2S_SCK_S:
234 NRF_PSEL_I2S(reg, SCK) = psel;
235 dir = NRF_GPIO_PIN_DIR_INPUT;
236 input = NRF_GPIO_PIN_INPUT_CONNECT;
237 break;
238 case NRF_FUN_I2S_LRCK_M:
239 NRF_PSEL_I2S(reg, LRCK) = psel;
240 write = 0U;
241 dir = NRF_GPIO_PIN_DIR_OUTPUT;
242 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
243 break;
244 case NRF_FUN_I2S_LRCK_S:
245 NRF_PSEL_I2S(reg, LRCK) = psel;
246 dir = NRF_GPIO_PIN_DIR_INPUT;
247 input = NRF_GPIO_PIN_INPUT_CONNECT;
248 break;
249 case NRF_FUN_I2S_SDIN:
250 NRF_PSEL_I2S(reg, SDIN) = psel;
251 dir = NRF_GPIO_PIN_DIR_INPUT;
252 input = NRF_GPIO_PIN_INPUT_CONNECT;
253 break;
254 case NRF_FUN_I2S_SDOUT:
255 NRF_PSEL_I2S(reg, SDOUT) = psel;
256 write = 0U;
257 dir = NRF_GPIO_PIN_DIR_OUTPUT;
258 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
259 break;
260 case NRF_FUN_I2S_MCK:
261 NRF_PSEL_I2S(reg, MCK) = psel;
262 write = 0U;
263 dir = NRF_GPIO_PIN_DIR_OUTPUT;
264 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
265 break;
266 #endif /* defined(NRF_PSEL_I2S) */
267 #if defined(NRF_PSEL_PDM)
268 case NRF_FUN_PDM_CLK:
269 NRF_PSEL_PDM(reg, CLK) = psel;
270 write = 0U;
271 dir = NRF_GPIO_PIN_DIR_OUTPUT;
272 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
273 break;
274 case NRF_FUN_PDM_DIN:
275 NRF_PSEL_PDM(reg, DIN) = psel;
276 dir = NRF_GPIO_PIN_DIR_INPUT;
277 input = NRF_GPIO_PIN_INPUT_CONNECT;
278 break;
279 #endif /* defined(NRF_PSEL_PDM) */
280 #if defined(NRF_PSEL_PWM)
281 case NRF_FUN_PWM_OUT0:
282 NRF_PSEL_PWM(reg, OUT[0]) = psel;
283 write = NRF_GET_INVERT(pins[i]);
284 dir = NRF_GPIO_PIN_DIR_OUTPUT;
285 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
286 break;
287 case NRF_FUN_PWM_OUT1:
288 NRF_PSEL_PWM(reg, OUT[1]) = psel;
289 write = NRF_GET_INVERT(pins[i]);
290 dir = NRF_GPIO_PIN_DIR_OUTPUT;
291 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
292 break;
293 case NRF_FUN_PWM_OUT2:
294 NRF_PSEL_PWM(reg, OUT[2]) = psel;
295 write = NRF_GET_INVERT(pins[i]);
296 dir = NRF_GPIO_PIN_DIR_OUTPUT;
297 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
298 break;
299 case NRF_FUN_PWM_OUT3:
300 NRF_PSEL_PWM(reg, OUT[3]) = psel;
301 write = NRF_GET_INVERT(pins[i]);
302 dir = NRF_GPIO_PIN_DIR_OUTPUT;
303 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
304 break;
305 #endif /* defined(NRF_PSEL_PWM) */
306 #if defined(NRF_PSEL_QDEC)
307 case NRF_FUN_QDEC_A:
308 NRF_PSEL_QDEC(reg, A) = psel;
309 dir = NRF_GPIO_PIN_DIR_INPUT;
310 input = NRF_GPIO_PIN_INPUT_CONNECT;
311 break;
312 case NRF_FUN_QDEC_B:
313 NRF_PSEL_QDEC(reg, B) = psel;
314 dir = NRF_GPIO_PIN_DIR_INPUT;
315 input = NRF_GPIO_PIN_INPUT_CONNECT;
316 break;
317 case NRF_FUN_QDEC_LED:
318 NRF_PSEL_QDEC(reg, LED) = psel;
319 dir = NRF_GPIO_PIN_DIR_INPUT;
320 input = NRF_GPIO_PIN_INPUT_CONNECT;
321 break;
322 #endif /* defined(NRF_PSEL_QDEC) */
323 #if defined(NRF_PSEL_QSPI)
324 case NRF_FUN_QSPI_SCK:
325 NRF_PSEL_QSPI(reg, SCK) = psel;
326 dir = NRF_GPIO_PIN_DIR_INPUT;
327 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
328 break;
329 case NRF_FUN_QSPI_CSN:
330 NRF_PSEL_QSPI(reg, CSN) = psel;
331 write = 1U;
332 dir = NRF_GPIO_PIN_DIR_OUTPUT;
333 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
334 break;
335 case NRF_FUN_QSPI_IO0:
336 NRF_PSEL_QSPI(reg, IO0) = psel;
337 dir = NRF_GPIO_PIN_DIR_INPUT;
338 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
339 break;
340 case NRF_FUN_QSPI_IO1:
341 NRF_PSEL_QSPI(reg, IO1) = psel;
342 dir = NRF_GPIO_PIN_DIR_INPUT;
343 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
344 break;
345 case NRF_FUN_QSPI_IO2:
346 NRF_PSEL_QSPI(reg, IO2) = psel;
347 dir = NRF_GPIO_PIN_DIR_INPUT;
348 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
349 break;
350 case NRF_FUN_QSPI_IO3:
351 NRF_PSEL_QSPI(reg, IO3) = psel;
352 write = 1U;
353 dir = NRF_GPIO_PIN_DIR_OUTPUT;
354 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
355 break;
356 #endif /* defined(NRF_PSEL_QSPI) */
357 #if defined(NRF_GRTC_CLKOUT_FAST)
358 case NRF_FUN_GRTC_CLKOUT_FAST:
359 #if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC)
360 nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_GRTC);
361 #endif
362 dir = NRF_GPIO_PIN_DIR_OUTPUT;
363 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
364 break;
365 #endif /* defined(NRF_GRTC_CLKOUT_FAST) */
366 #if defined(NRF_GRTC_CLKOUT_SLOW)
367 case NRF_FUN_GRTC_CLKOUT_32K:
368 #if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC)
369 nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_GRTC);
370 #endif
371 dir = NRF_GPIO_PIN_DIR_OUTPUT;
372 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
373 break;
374 #endif /* defined(NRF_GRTC_CLKOUT_SLOW) */
375 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can)
376 /* Pin routing is controlled by secure domain, via UICR */
377 case NRF_FUN_CAN_TX:
378 dir = NRF_GPIO_PIN_DIR_OUTPUT;
379 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
380 break;
381 case NRF_FUN_CAN_RX:
382 dir = NRF_GPIO_PIN_DIR_INPUT;
383 input = NRF_GPIO_PIN_INPUT_CONNECT;
384 break;
385 #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */
386 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_exmif)
387 /* Pin routing is controlled by secure domain, via UICR */
388 case NRF_FUN_EXMIF_CK:
389 case NRF_FUN_EXMIF_DQ0:
390 case NRF_FUN_EXMIF_DQ1:
391 case NRF_FUN_EXMIF_DQ2:
392 case NRF_FUN_EXMIF_DQ3:
393 case NRF_FUN_EXMIF_DQ4:
394 case NRF_FUN_EXMIF_DQ5:
395 case NRF_FUN_EXMIF_DQ6:
396 case NRF_FUN_EXMIF_DQ7:
397 case NRF_FUN_EXMIF_CS0:
398 case NRF_FUN_EXMIF_CS1:
399 case NRF_FUN_EXMIF_RWDS:
400 dir = NRF_GPIO_PIN_DIR_INPUT;
401 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
402 break;
403 #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_exmif) */
404 #if defined(NRF_PSEL_TWIS)
405 case NRF_FUN_TWIS_SCL:
406 NRF_PSEL_TWIS(reg, SCL) = psel;
407 if (drive == NRF_GPIO_PIN_S0S1) {
408 drive = NRF_GPIO_PIN_S0D1;
409 }
410 dir = NRF_GPIO_PIN_DIR_INPUT;
411 input = NRF_GPIO_PIN_INPUT_CONNECT;
412 break;
413 case NRF_FUN_TWIS_SDA:
414 NRF_PSEL_TWIS(reg, SDA) = psel;
415 if (drive == NRF_GPIO_PIN_S0S1) {
416 drive = NRF_GPIO_PIN_S0D1;
417 }
418 dir = NRF_GPIO_PIN_DIR_INPUT;
419 input = NRF_GPIO_PIN_INPUT_CONNECT;
420 break;
421 #endif /* defined(NRF_PSEL_TWIS) */
422 default:
423 return -ENOTSUP;
424 }
425
426 /* configure GPIO properties */
427 if (psel != PSEL_DISCONNECTED) {
428 uint32_t pin = psel;
429
430 #ifdef CONFIG_SOC_NRF54H20_GPD
431 if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) {
432 if (!gpd_requested) {
433 int ret;
434
435 ret = nrf_gpd_request(NRF_GPD_SLOW_ACTIVE);
436 if (ret < 0) {
437 return ret;
438 }
439 gpd_requested = true;
440 }
441
442 nrf_gpio_pin_retain_disable(pin);
443 }
444 #endif /* CONFIG_SOC_NRF54H20_GPD */
445
446 if (write != NO_WRITE) {
447 nrf_gpio_pin_write(pin, write);
448 }
449
450 /* force input and disconnected buffer for low power */
451 if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
452 dir = NRF_GPIO_PIN_DIR_INPUT;
453 input = NRF_GPIO_PIN_INPUT_DISCONNECT;
454 }
455
456 nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
457 drive, NRF_GPIO_PIN_NOSENSE);
458 #if NRF_GPIO_HAS_CLOCKPIN
459 nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i]));
460 #endif
461 #ifdef CONFIG_SOC_NRF54H20_GPD
462 if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) {
463 nrf_gpio_pin_retain_enable(pin);
464 }
465 #endif /* CONFIG_SOC_NRF54H20_GPD */
466 }
467 }
468
469 #ifdef CONFIG_SOC_NRF54H20_GPD
470 if (gpd_requested) {
471 int ret;
472
473 ret = nrf_gpd_release(NRF_GPD_SLOW_ACTIVE);
474 if (ret < 0) {
475 return ret;
476 }
477 }
478 #endif
479
480 return 0;
481 }
482
