1 /* 2 * Copyright (c) 2023 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ 8 #define ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ 9 10 #include <zephyr/device.h> 11 #include "jesd216.h" 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /* UMA operation flags */ 18 #define NPCX_UMA_ACCESS_WRITE BIT(0) 19 #define NPCX_UMA_ACCESS_READ BIT(1) 20 #define NPCX_UMA_ACCESS_ADDR BIT(2) 21 22 /* Valid value of Dn_NADDRB that sets the number of address bytes in a transaction */ 23 #define NPCX_DEV_NUM_ADDR_1BYTE 1 24 #define NPCX_DEV_NUM_ADDR_2BYTE 2 25 #define NPCX_DEV_NUM_ADDR_3BYTE 3 26 #define NPCX_DEV_NUM_ADDR_4BYTE 4 27 28 #define NPCX_SPI_F_CS0 0 29 #define NPCX_SPI_F_CS1 1 30 31 enum NPCX_SPI_DEV_SIZE { 32 NPCX_SPI_DEV_SIZE_1M, 33 NPCX_SPI_DEV_SIZE_2M, 34 NPCX_SPI_DEV_SIZE_4M, 35 NPCX_SPI_DEV_SIZE_8M, 36 NPCX_SPI_DEV_SIZE_16M, 37 NPCX_SPI_DEV_SIZE_32M, 38 NPCX_SPI_DEV_SIZE_64M, 39 NPCX_SPI_DEV_SIZE_128M, 40 }; 41 42 /* UMA operation configuration for a SPI device */ 43 struct npcx_uma_cfg { 44 uint8_t opcode; 45 uint8_t *tx_buf; 46 size_t tx_count; 47 uint8_t *rx_buf; 48 size_t rx_count; 49 union { 50 uint32_t u32; 51 uint8_t u8[4]; 52 } addr; 53 }; 54 55 /* QSPI bus configuration for a SPI device */ 56 struct npcx_qspi_cfg { 57 /* Type of Quad Enable bit in status register */ 58 enum jesd216_dw15_qer_type qer_type; 59 /* Pinctrl for QSPI bus */ 60 const struct pinctrl_dev_config *pcfg; 61 /* Enter four bytes address mode value */ 62 uint8_t enter_4ba; 63 /* SPI read access type of Direct Read Access mode */ 64 uint8_t rd_mode; 65 bool is_logical_low_dev; 66 uint8_t spi_dev_sz; 67 /* Configurations for the Quad-SPI peripherals */ 68 int flags; 69 }; 70 71 /** 72 * @brief Execute UMA transactions on qspi bus 73 * 74 * @param dev Pointer to the device structure for qspi bus controller instance. 75 * @param cfg Pointer to the configuration of UMA transactions. 76 * @param flags Flags to be used during transactions. 77 * @retval 0 on success, -EPERM if an UMA transaction is not permitted. 78 */ 79 int qspi_npcx_fiu_uma_transceive(const struct device *dev, struct npcx_uma_cfg *cfg, 80 uint32_t flags); 81 82 /** 83 * @brief Lock the mutex of npcx qspi bus controller and apply its configuration 84 * 85 * @param dev Pointer to the device structure for qspi bus controller instance. 86 * @param cfg Pointer to the configuration for the device on qspi bus. 87 * @param operation Qspi bus operation for the device. 88 */ 89 void qspi_npcx_fiu_mutex_lock_configure(const struct device *dev, 90 const struct npcx_qspi_cfg *cfg, 91 const uint32_t operation); 92 93 /** 94 * @brief Unlock the mutex of npcx qspi bus controller. 95 * 96 * @param dev Pointer to the device structure for qspi bus controller instance. 97 */ 98 void qspi_npcx_fiu_mutex_unlock(const struct device *dev); 99 100 /** 101 * @brief Set the size of the address space allocated for SPI device. 102 * 103 * @param dev Pointer to the device structure for qspi bus controller instance. 104 * @param cfg Pointer to the configuration for the device on qspi bus. 105 */ 106 void qspi_npcx_fiu_set_spi_size(const struct device *dev, const struct npcx_qspi_cfg *cfg); 107 108 #ifdef __cplusplus 109 } 110 #endif 111 112 #endif /* ZEPHYR_DRIVERS_FLASH_NPCX_FIU_QSPI_H_ */ 113
