1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __INTEL_DAI_DRIVER_SSP_H__ 8 #define __INTEL_DAI_DRIVER_SSP_H__ 9 10 #define SSP_IP_VER_1_0 0x10000 /* cAVS */ 11 #define SSP_IP_VER_1_5 0x10500 /* ACE15 */ 12 #define SSP_IP_VER_2_0 0x20000 /* ACE20 */ 13 #define SSP_IP_VER_3_0 0x30000 /* ACE30 */ 14 15 /* SSP IP version defined by CONFIG_SOC*/ 16 #if defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS) 17 #define SSP_IP_VER SSP_IP_VER_1_0 18 #elif defined(CONFIG_SOC_INTEL_ACE15_MTPM) 19 #define SSP_IP_VER SSP_IP_VER_1_5 20 #elif defined(CONFIG_SOC_INTEL_ACE20_LNL) 21 #define SSP_IP_VER SSP_IP_VER_2_0 22 #elif defined(CONFIG_SOC_INTEL_ACE30) 23 #define SSP_IP_VER SSP_IP_VER_3_0 24 #else 25 #error "Unknown SSP IP" 26 #endif 27 28 #include <stdint.h> 29 #include <zephyr/drivers/dai.h> 30 #include "dai-params-intel-ipc3.h" 31 #include "dai-params-intel-ipc4.h" 32 33 #define DAI_INTEL_SSP_MASK(b_hi, b_lo) \ 34 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo)) 35 #define DAI_INTEL_SSP_SET_BIT(b, x) (((x) & 1) << (b)) 36 #define DAI_INTEL_SSP_SET_BITS(b_hi, b_lo, x) \ 37 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo)) 38 #define DAI_INTEL_SSP_GET_BIT(b, x) \ 39 (((x) & (1ULL << (b))) >> (b)) 40 #define DAI_INTEL_SSP_GET_BITS(b_hi, b_lo, x) \ 41 (((x) & MASK(b_hi, b_lo)) >> (b_lo)) 42 43 /* ssp_freq array constants */ 44 #define DAI_INTEL_SSP_NUM_FREQ 3 45 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1) 46 #define DAI_INTEL_SSP_DEFAULT_IDX 1 47 48 /* the SSP port fifo depth */ 49 #define DAI_INTEL_SSP_FIFO_DEPTH 32 50 51 /* the watermark for the SSP fifo depth setting */ 52 #define DAI_INTEL_SSP_FIFO_WATERMARK 8 53 54 /* minimal SSP port delay in cycles */ 55 #define DAI_INTEL_SSP_PLATFORM_DELAY 1600 56 /* minimal SSP port delay in useconds */ 57 #define DAI_INTEL_SSP_PLATFORM_DELAY_US 42 58 #define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY 12 59 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8 60 61 /** \brief Number of SSP MCLKs available */ 62 #define DAI_INTEL_SSP_NUM_MCLK 2 63 64 #define DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR 0x0 65 #define DAI_INTEL_SSP_CLOCK_AUDIO_CARDINAL 0x1 66 #define DAI_INTEL_SSP_CLOCK_PLL_FIXED 0x2 67 68 #if defined(CONFIG_SOC_INTEL_ACE15_MTPM) || defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS) 69 #include "ssp_regs_v1.h" 70 #elif defined(CONFIG_SOC_INTEL_ACE20_LNL) 71 #include "ssp_regs_v2.h" 72 #elif defined(CONFIG_SOC_INTEL_ACE30) 73 #include "ssp_regs_v3.h" 74 #else 75 #error "Missing ssp definitions" 76 #endif 77 78 #if SSP_IP_VER == SSP_IP_VER_1_0 79 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly. 80 * Even in the case of M/N, the actual clock source can be XTAL, 81 * Audio cardinal clock (24.576) or 96 MHz PLL. 82 * The MN block is not really the source of clocks, but rather 83 * an intermediate component. 84 * Input for source is shared by all outputs coming from that source 85 * and once it's in use, it can be adjusted only with dividers. 86 * In order to change input, the source should not be in use, that's why 87 * it's necessary to keep track of BCLKs sources to know when it's safe 88 * to change shared input clock. 89 */ 90 enum bclk_source { 91 MN_BCLK_SOURCE_NONE = 0, /**< port is not using any clock */ 92 MN_BCLK_SOURCE_MN, /**< port is using clock driven by M/N */ 93 MN_BCLK_SOURCE_XTAL, /**< port is using XTAL directly */ 94 }; 95 #endif 96 97 struct dai_intel_ssp_mn { 98 uint32_t base; 99 /**< keep track of which MCLKs are in use to know when it's safe to 100 * change shared clock 101 */ 102 int mclk_sources_ref[DAI_INTEL_SSP_NUM_MCLK]; 103 int mclk_rate[DAI_INTEL_SSP_NUM_MCLK]; 104 int mclk_source_clock; 105 106 #if SSP_IP_VER == SSP_IP_VER_1_0 107 enum bclk_source bclk_sources[(CONFIG_DAI_INTEL_SSP_NUM_BASE + 108 CONFIG_DAI_INTEL_SSP_NUM_EXT)]; 109 int bclk_source_mn_clock; 110 #endif 111 112 struct k_spinlock lock; /**< lock mechanism */ 113 }; 114 115 struct dai_intel_ssp_freq_table { 116 uint32_t freq; 117 uint32_t ticks_per_msec; 118 }; 119 120 struct dai_intel_ssp_plat_fifo_data { 121 uint32_t offset; 122 uint32_t width; 123 uint32_t depth; 124 uint32_t watermark; 125 uint32_t handshake; 126 }; 127 128 struct dai_intel_ssp_plat_data { 129 uint32_t ssp_index; 130 int acquire_count; 131 bool is_initialized; 132 bool is_power_en; 133 uint32_t base; 134 uint32_t ip_base; 135 uint32_t shim_base; 136 #if SSP_IP_VER > SSP_IP_VER_1_5 137 uint32_t hdamlssp_base; 138 uint32_t i2svss_base; 139 uint32_t link_clock; 140 #endif 141 int irq; 142 const char *irq_name; 143 uint32_t flags; 144 struct dai_intel_ssp_plat_fifo_data fifo[2]; 145 struct dai_intel_ssp_mn *mn_inst; 146 struct dai_intel_ssp_freq_table *ftable; 147 uint32_t *fsources; 148 uint32_t clk_active; 149 struct dai_intel_ipc3_ssp_params params; 150 }; 151 152 struct dai_intel_ssp_pdata { 153 uint32_t sscr0; 154 uint32_t sscr1; 155 uint32_t psp; 156 struct dai_config config; 157 struct dai_properties props; 158 }; 159 160 struct dai_intel_ssp { 161 uint32_t dai_index; 162 uint32_t ssp_index; 163 uint32_t tdm_slot_group; 164 uint32_t state[2]; 165 struct k_spinlock lock; /**< locking mechanism */ 166 int sref; /**< simple ref counter, guarded by lock */ 167 struct dai_intel_ssp_plat_data *ssp_plat_data; 168 void *priv_data; 169 }; 170 171 #endif 172
