1 /*
2  * Copyright (c) 2022 Vestas Wind Systems A/S
3  * Copyright (c) 2020 Alexander Wachter
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/drivers/pinctrl.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/sys/__assert.h>
15 #include <soc.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18 
19 LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
20 
21 #define DT_DRV_COMPAT st_stm32_fdcan
22 
23 /*
24  * The STMicroelectronics STM32 FDCAN definitions correspond to those found in the
25  * STMicroelectronics STM32G4 Series Reference manual (RM0440), Rev 7.
26  *
27  * This controller uses a Bosch M_CAN like register layout, but some registers are unimplemented,
28  * some registers are mapped to other register offsets, and some registers have had their bit fields
29  * remapped.
30  *
31  * Apart from the definitions below please note the following limitations:
32  * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
33  * - CCCR register VMM and UTSU bits are not available.
34  * - TXBC register TFQS, NDTB, and TBSA fields are not available.
35  */
36 
37 /* Interrupt register */
38 #define CAN_STM32FD_IR_ARA  BIT(23)
39 #define CAN_STM32FD_IR_PED  BIT(22)
40 #define CAN_STM32FD_IR_PEA  BIT(21)
41 #define CAN_STM32FD_IR_WDI  BIT(20)
42 #define CAN_STM32FD_IR_BO   BIT(19)
43 #define CAN_STM32FD_IR_EW   BIT(18)
44 #define CAN_STM32FD_IR_EP   BIT(17)
45 #define CAN_STM32FD_IR_ELO  BIT(16)
46 #define CAN_STM32FD_IR_TOO  BIT(15)
47 #define CAN_STM32FD_IR_MRAF BIT(14)
48 #define CAN_STM32FD_IR_TSW  BIT(13)
49 #define CAN_STM32FD_IR_TEFL BIT(12)
50 #define CAN_STM32FD_IR_TEFF BIT(11)
51 #define CAN_STM32FD_IR_TEFN BIT(10)
52 #define CAN_STM32FD_IR_TFE  BIT(9)
53 #define CAN_STM32FD_IR_TCF  BIT(8)
54 #define CAN_STM32FD_IR_TC   BIT(7)
55 #define CAN_STM32FD_IR_HPM  BIT(6)
56 #define CAN_STM32FD_IR_RF1L BIT(5)
57 #define CAN_STM32FD_IR_RF1F BIT(4)
58 #define CAN_STM32FD_IR_RF1N BIT(3)
59 #define CAN_STM32FD_IR_RF0L BIT(2)
60 #define CAN_STM32FD_IR_RF0F BIT(1)
61 #define CAN_STM32FD_IR_RF0N BIT(0)
62 
63 /* Interrupt Enable register */
64 #define CAN_STM32FD_IE_ARAE  BIT(23)
65 #define CAN_STM32FD_IE_PEDE  BIT(22)
66 #define CAN_STM32FD_IE_PEAE  BIT(21)
67 #define CAN_STM32FD_IE_WDIE  BIT(20)
68 #define CAN_STM32FD_IE_BOE   BIT(19)
69 #define CAN_STM32FD_IE_EWE   BIT(18)
70 #define CAN_STM32FD_IE_EPE   BIT(17)
71 #define CAN_STM32FD_IE_ELOE  BIT(16)
72 #define CAN_STM32FD_IE_TOOE  BIT(15)
73 #define CAN_STM32FD_IE_MRAFE BIT(14)
74 #define CAN_STM32FD_IE_TSWE  BIT(13)
75 #define CAN_STM32FD_IE_TEFLE BIT(12)
76 #define CAN_STM32FD_IE_TEFFE BIT(11)
77 #define CAN_STM32FD_IE_TEFNE BIT(10)
78 #define CAN_STM32FD_IE_TFEE  BIT(9)
79 #define CAN_STM32FD_IE_TCFE  BIT(8)
80 #define CAN_STM32FD_IE_TCE   BIT(7)
81 #define CAN_STM32FD_IE_HPME  BIT(6)
82 #define CAN_STM32FD_IE_RF1LE BIT(5)
83 #define CAN_STM32FD_IE_RF1FE BIT(4)
84 #define CAN_STM32FD_IE_RF1NE BIT(3)
85 #define CAN_STM32FD_IE_RF0LE BIT(2)
86 #define CAN_STM32FD_IE_RF0FE BIT(1)
87 #define CAN_STM32FD_IE_RF0NE BIT(0)
88 
89 /* Interrupt Line Select register */
90 #define CAN_STM32FD_ILS_PERR    BIT(6)
91 #define CAN_STM32FD_ILS_BERR    BIT(5)
92 #define CAN_STM32FD_ILS_MISC    BIT(4)
93 #define CAN_STM32FD_ILS_TFERR   BIT(3)
94 #define CAN_STM32FD_ILS_SMSG    BIT(2)
95 #define CAN_STM32FD_ILS_RXFIFO1 BIT(1)
96 #define CAN_STM32FD_ILS_RXFIFO0 BIT(0)
97 
98 /* Global filter configuration register */
99 #define CAN_STM32FD_RXGFC      0x080
100 #define CAN_STM32FD_RXGFC_LSE  GENMASK(27, 24)
101 #define CAN_STM32FD_RXGFC_LSS  GENMASK(20, 16)
102 #define CAN_STM32FD_RXGFC_F0OM BIT(9)
103 #define CAN_STM32FD_RXGFC_F1OM BIT(8)
104 #define CAN_STM32FD_RXGFC_ANFS GENMASK(5, 4)
105 #define CAN_STM32FD_RXGFC_ANFE GENMASK(3, 2)
106 #define CAN_STM32FD_RXGFC_RRFS BIT(1)
107 #define CAN_STM32FD_RXGFC_RRFE BIT(0)
108 
109 /* Extended ID AND Mask register */
110 #define CAN_STM32FD_XIDAM 0x084
111 
112 /* High Priority Message Status register */
113 #define CAN_STM32FD_HPMS 0x088
114 
115 /* Rx FIFO 0 Status register */
116 #define CAN_STM32FD_RXF0S 0x090
117 
118 /* Rx FIFO 0 Acknowledge register */
119 #define CAN_STM32FD_RXF0A 0x094
120 
121 /* Rx FIFO 1 Status register */
122 #define CAN_STM32FD_RXF1S 0x098
123 
124 /* Rx FIFO 1 Acknowledge register */
125 #define CAN_STM32FD_RXF1A 0x09C
126 
127 /* Tx Buffer Configuration register */
128 #define CAN_STM32FD_TXBC_TFQM BIT(24)
129 
130 /* Tx Buffer Request Pending register */
131 #define CAN_STM32FD_TXBRP 0x0C8
132 
133 /* Tx Buffer Add Request register */
134 #define CAN_STM32FD_TXBAR 0x0CC
135 
136 /* Tx Buffer Cancellation Request register */
137 #define CAN_STM32FD_TXBCR 0x0D0
138 
139 /* Tx Buffer Transmission Occurred register */
140 #define CAN_STM32FD_TXBTO 0x0D4
141 
142 /* Tx Buffer Cancellation Finished register */
143 #define CAN_STM32FD_TXBCF 0x0D8
144 
145 /* Tx Buffer Transmission Interrupt Enable register */
146 #define CAN_STM32FD_TXBTIE 0x0DC
147 
148 /* Tx Buffer Cancellation Finished Interrupt Enable register */
149 #define CAN_STM32FD_TXBCIE 0x0E0
150 
151 /* Tx Event FIFO Status register */
152 #define CAN_STM32FD_TXEFS 0x0E4
153 
154 /* Tx Event FIFO Acknowledge register */
155 #define CAN_STM32FD_TXEFA 0x0E8
156 
157 /* Register address indicating unsupported register */
158 #define CAN_STM32FD_REGISTER_UNSUPPORTED UINT16_MAX
159 
160 /* This symbol takes the value 1 if one of the device instances */
161 /* is configured in dts with a domain clock */
162 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
163 #define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 1
164 #else
165 #define STM32_CANFD_DOMAIN_CLOCK_SUPPORT 0
166 #endif
167 
168 struct can_stm32fd_config {
169 	mm_reg_t base;
170 	mem_addr_t mram;
171 	size_t pclk_len;
172 	const struct stm32_pclken *pclken;
173 	void (*config_irq)(void);
174 	const struct pinctrl_dev_config *pcfg;
175 	uint8_t clock_divider;
176 };
177 
can_stm32fd_remap_reg(uint16_t reg)178 static inline uint16_t can_stm32fd_remap_reg(uint16_t reg)
179 {
180 	uint16_t remap;
181 
182 	switch (reg) {
183 	case CAN_MCAN_SIDFC:
184 		__fallthrough;
185 	case CAN_MCAN_XIDFC:
186 		__fallthrough;
187 	case CAN_MCAN_NDAT1:
188 		__fallthrough;
189 	case CAN_MCAN_NDAT2:
190 		__fallthrough;
191 	case CAN_MCAN_RXF0C:
192 		__fallthrough;
193 	case CAN_MCAN_RXBC:
194 		__fallthrough;
195 	case CAN_MCAN_RXF1C:
196 		__fallthrough;
197 	case CAN_MCAN_RXESC:
198 		__fallthrough;
199 	case CAN_MCAN_TXESC:
200 		__fallthrough;
201 	case CAN_MCAN_TXEFC:
202 		__ASSERT_NO_MSG(false);
203 		remap = CAN_STM32FD_REGISTER_UNSUPPORTED;
204 		break;
205 	case CAN_MCAN_XIDAM:
206 		remap = CAN_STM32FD_XIDAM;
207 		break;
208 	case CAN_MCAN_RXF0S:
209 		remap = CAN_STM32FD_RXF0S;
210 		break;
211 	case CAN_MCAN_RXF0A:
212 		remap = CAN_STM32FD_RXF0A;
213 		break;
214 	case CAN_MCAN_RXF1S:
215 		remap = CAN_STM32FD_RXF1S;
216 		break;
217 	case CAN_MCAN_RXF1A:
218 		remap = CAN_STM32FD_RXF1A;
219 		break;
220 	case CAN_MCAN_TXBRP:
221 		remap = CAN_STM32FD_TXBRP;
222 		break;
223 	case CAN_MCAN_TXBAR:
224 		remap = CAN_STM32FD_TXBAR;
225 		break;
226 	case CAN_MCAN_TXBCR:
227 		remap = CAN_STM32FD_TXBCR;
228 		break;
229 	case CAN_MCAN_TXBTO:
230 		remap = CAN_STM32FD_TXBTO;
231 		break;
232 	case CAN_MCAN_TXBCF:
233 		remap = CAN_STM32FD_TXBCF;
234 		break;
235 	case CAN_MCAN_TXBTIE:
236 		remap = CAN_STM32FD_TXBTIE;
237 		break;
238 	case CAN_MCAN_TXBCIE:
239 		remap = CAN_STM32FD_TXBCIE;
240 		break;
241 	case CAN_MCAN_TXEFS:
242 		remap = CAN_STM32FD_TXEFS;
243 		break;
244 	case CAN_MCAN_TXEFA:
245 		remap = CAN_STM32FD_TXEFA;
246 		break;
247 	default:
248 		/* No register address remap needed */
249 		remap = reg;
250 		break;
251 	};
252 
253 	return remap;
254 }
255 
can_stm32fd_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)256 static int can_stm32fd_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
257 {
258 	const struct can_mcan_config *mcan_config = dev->config;
259 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
260 	uint16_t remap;
261 	uint32_t bits;
262 	int err;
263 
264 	remap = can_stm32fd_remap_reg(reg);
265 	if (remap == CAN_STM32FD_REGISTER_UNSUPPORTED) {
266 		return -ENOTSUP;
267 	}
268 
269 	err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits);
270 	if (err != 0) {
271 		return err;
272 	}
273 
274 	*val = 0U;
275 
276 	switch (reg) {
277 	case CAN_MCAN_IR:
278 		__fallthrough;
279 	case CAN_MCAN_IE:
280 		/* Remap IR/IE bits, ignoring unsupported bits */
281 		/* Group 1 map bits 23-16 (stm32fd) to 29-22 (mcan) */
282 		*val |= ((bits & GENMASK(23, 16)) << 6);
283 
284 		/* Group 2 map bits 15-11 (stm32fd) to 18-14 (mcan) */
285 		*val |= ((bits & GENMASK(15, 11)) << 3);
286 
287 		/* Group 3 map bits 10-4 (stm32fd) to 12-6 (mcan) */
288 		*val |= ((bits & GENMASK(10, 4)) << 2);
289 
290 		/* Group 4 map bits 3-1 (stm32fd) to 4-2 (mcan) */
291 		*val |= ((bits & GENMASK(3, 1)) << 1);
292 
293 		/* Group 5 map bits 0 (mcan) to 0 (stm32fd) */
294 		*val |= ((bits & GENMASK(0, 0)) << 0);
295 		break;
296 	case CAN_MCAN_ILS:
297 		/* Only remap ILS groups used in can_mcan.c */
298 		if ((bits & CAN_STM32FD_ILS_RXFIFO1) != 0U) {
299 			*val |= CAN_MCAN_ILS_RF1LL | CAN_MCAN_ILS_RF1FL | CAN_MCAN_ILS_RF1NL;
300 		}
301 
302 		if ((bits & CAN_STM32FD_ILS_RXFIFO0) != 0U) {
303 			*val |= CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF0FL | CAN_MCAN_ILS_RF0NL;
304 		}
305 		break;
306 	case CAN_MCAN_GFC:
307 		/* Map fields from RXGFC excluding STM32 FDCAN LSS and LSE fields */
308 		*val = bits & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |
309 		       CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE);
310 		break;
311 	default:
312 		/* No field remap needed */
313 		*val = bits;
314 		break;
315 	};
316 
317 	return 0;
318 }
319 
can_stm32fd_write_reg(const struct device * dev,uint16_t reg,uint32_t val)320 static int can_stm32fd_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
321 {
322 	const struct can_mcan_config *mcan_config = dev->config;
323 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
324 	uint32_t bits = 0U;
325 	uint16_t remap;
326 
327 	remap = can_stm32fd_remap_reg(reg);
328 	if (remap == CAN_STM32FD_REGISTER_UNSUPPORTED) {
329 		return -ENOTSUP;
330 	}
331 
332 	switch (reg) {
333 	case CAN_MCAN_IR:
334 		__fallthrough;
335 	case CAN_MCAN_IE:
336 		/* Remap IR/IE bits, ignoring unsupported bits */
337 		/* Group 1 map bits 29-22 (mcan) to 23-16 (stm32fd) */
338 		bits |= ((val & GENMASK(29, 22)) >> 6);
339 
340 		/* Group 2 map bits 18-14 (mcan) to 15-11 (stm32fd) */
341 		bits |= ((val & GENMASK(18, 14)) >> 3);
342 
343 		/* Group 3 map bits 12-6 (mcan) to 10-4 (stm32fd) */
344 		bits |= ((val & GENMASK(12, 6)) >> 2);
345 
346 		/* Group 4 map bits 4-2 (mcan) to 3-1 (stm32fd) */
347 		bits |= ((val & GENMASK(4, 2)) >> 1);
348 
349 		/* Group 5 map bits 0 (mcan) to 0 (stm32fd) */
350 		bits |= ((val & GENMASK(0, 0)) >> 0);
351 		break;
352 	case CAN_MCAN_ILS:
353 		/* Only remap ILS groups used in can_mcan.c */
354 		if ((val & (CAN_MCAN_ILS_RF1LL | CAN_MCAN_ILS_RF1FL | CAN_MCAN_ILS_RF1NL)) != 0U) {
355 			bits |= CAN_STM32FD_ILS_RXFIFO1;
356 		}
357 
358 		if ((val & (CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF0FL | CAN_MCAN_ILS_RF0NL)) != 0U) {
359 			bits |= CAN_STM32FD_ILS_RXFIFO0;
360 		}
361 		break;
362 	case CAN_MCAN_GFC:
363 		/* Map fields to RXGFC including STM32 FDCAN LSS and LSE fields */
364 		bits |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |
365 			FIELD_PREP(CAN_STM32FD_RXGFC_LSE, CONFIG_CAN_MAX_EXT_ID_FILTER);
366 		bits |= val & (CAN_MCAN_GFC_ANFS | CAN_MCAN_GFC_ANFE |
367 			CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE);
368 		break;
369 	default:
370 		/* No field remap needed */
371 		bits = val;
372 		break;
373 	};
374 
375 	return can_mcan_sys_write_reg(stm32fd_config->base, remap, bits);
376 }
377 
can_stm32fd_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)378 static int can_stm32fd_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
379 {
380 	const struct can_mcan_config *mcan_config = dev->config;
381 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
382 
383 	return can_mcan_sys_read_mram(stm32fd_config->mram, offset, dst, len);
384 }
385 
can_stm32fd_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)386 static int can_stm32fd_write_mram(const struct device *dev, uint16_t offset, const void *src,
387 				size_t len)
388 {
389 	const struct can_mcan_config *mcan_config = dev->config;
390 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
391 
392 	return can_mcan_sys_write_mram(stm32fd_config->mram, offset, src, len);
393 }
394 
can_stm32fd_clear_mram(const struct device * dev,uint16_t offset,size_t len)395 static int can_stm32fd_clear_mram(const struct device *dev, uint16_t offset, size_t len)
396 {
397 	const struct can_mcan_config *mcan_config = dev->config;
398 	const struct can_stm32fd_config *stm32fd_config = mcan_config->custom;
399 
400 	return can_mcan_sys_clear_mram(stm32fd_config->mram, offset, len);
401 }
402 
can_stm32fd_get_core_clock(const struct device * dev,uint32_t * rate)403 static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
404 {
405 	uint32_t rate_tmp;
406 	const struct can_mcan_config *mcan_cfg = dev->config;
407 	const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
408 	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
409 
410 	ARG_UNUSED(dev);
411 	if (!device_is_ready(clk)) {
412 		return -ENODEV;
413 	}
414 
415 	if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {
416 		if (clock_control_get_rate(clk,
417 			 (clock_control_subsys_t) &stm32fd_cfg->pclken[1],
418 			  &rate_tmp) < 0) {
419 			LOG_ERR("Failed call clock_control_get_rate(pclk[1])");
420 			return -EIO;
421 		}
422 	} else {
423 		if (clock_control_get_rate(clk,
424 			 (clock_control_subsys_t) &stm32fd_cfg->pclken[0],
425 			  &rate_tmp) < 0) {
426 			LOG_ERR("Failed call clock_control_get_rate(pclk[0])");
427 			return -EIO;
428 		}
429 	}
430 
431 	if (FDCAN_CONFIG->CKDIV == 0) {
432 		*rate = rate_tmp;
433 	} else {
434 		*rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1);
435 	}
436 
437 	return 0;
438 }
439 
can_stm32fd_clock_enable(const struct device * dev)440 static int can_stm32fd_clock_enable(const struct device *dev)
441 {
442 	int ret;
443 	const struct can_mcan_config *mcan_cfg = dev->config;
444 	const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
445 	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
446 
447 	if (!device_is_ready(clk)) {
448 		return -ENODEV;
449 	}
450 
451 	if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {
452 		ret = clock_control_configure(clk,
453 				(clock_control_subsys_t)&stm32fd_cfg->pclken[1],
454 				NULL);
455 		if (ret < 0) {
456 			LOG_ERR("Could not select can_stm32fd domain clock");
457 			return ret;
458 		}
459 	}
460 
461 	ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]);
462 	if (ret < 0) {
463 		return ret;
464 	}
465 
466 	if (stm32fd_cfg->clock_divider != 0) {
467 		can_mcan_enable_configuration_change(dev);
468 		FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1;
469 	}
470 
471 	return 0;
472 }
473 
can_stm32fd_init(const struct device * dev)474 static int can_stm32fd_init(const struct device *dev)
475 {
476 	const struct can_mcan_config *mcan_cfg = dev->config;
477 	const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
478 	uint32_t rxgfc;
479 	int ret;
480 
481 	/* Configure dt provided device signals when available */
482 	ret = pinctrl_apply_state(stm32fd_cfg->pcfg, PINCTRL_STATE_DEFAULT);
483 	if (ret < 0) {
484 		LOG_ERR("CAN pinctrl setup failed (%d)", ret);
485 		return ret;
486 	}
487 
488 	ret = can_stm32fd_clock_enable(dev);
489 	if (ret < 0) {
490 		LOG_ERR("Could not turn on CAN clock (%d)", ret);
491 		return ret;
492 	}
493 
494 	can_mcan_enable_configuration_change(dev);
495 
496 	/* Setup STM32 FDCAN Global Filter Configuration register */
497 	ret = can_mcan_read_reg(dev, CAN_STM32FD_RXGFC, &rxgfc);
498 	if (ret != 0) {
499 		return ret;
500 	}
501 
502 	rxgfc |= FIELD_PREP(CAN_STM32FD_RXGFC_LSS, CONFIG_CAN_MAX_STD_ID_FILTER) |
503 		 FIELD_PREP(CAN_STM32FD_RXGFC_LSE, CONFIG_CAN_MAX_EXT_ID_FILTER);
504 
505 	ret = can_mcan_write_reg(dev, CAN_STM32FD_RXGFC, rxgfc);
506 	if (ret != 0) {
507 		return ret;
508 	}
509 
510 	/* Setup STM32 FDCAN Tx buffer configuration register */
511 	ret = can_mcan_write_reg(dev, CAN_MCAN_TXBC, CAN_STM32FD_TXBC_TFQM);
512 	if (ret != 0) {
513 		return ret;
514 	}
515 
516 	ret = can_mcan_init(dev);
517 	if (ret != 0) {
518 		return ret;
519 	}
520 
521 	stm32fd_cfg->config_irq();
522 
523 	return ret;
524 }
525 
526 static DEVICE_API(can, can_stm32fd_driver_api) = {
527 	.get_capabilities = can_mcan_get_capabilities,
528 	.start = can_mcan_start,
529 	.stop = can_mcan_stop,
530 	.set_mode = can_mcan_set_mode,
531 	.set_timing = can_mcan_set_timing,
532 	.send = can_mcan_send,
533 	.add_rx_filter = can_mcan_add_rx_filter,
534 	.remove_rx_filter = can_mcan_remove_rx_filter,
535 	.get_state = can_mcan_get_state,
536 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
537 	.recover = can_mcan_recover,
538 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
539 	.get_core_clock = can_stm32fd_get_core_clock,
540 	.get_max_filters = can_mcan_get_max_filters,
541 	.set_state_change_callback = can_mcan_set_state_change_callback,
542 	.timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
543 	.timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
544 #ifdef CONFIG_CAN_FD_MODE
545 	.set_timing_data = can_mcan_set_timing_data,
546 	.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
547 	.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
548 #endif /* CONFIG_CAN_FD_MODE */
549 };
550 
551 static const struct can_mcan_ops can_stm32fd_ops = {
552 	.read_reg = can_stm32fd_read_reg,
553 	.write_reg = can_stm32fd_write_reg,
554 	.read_mram = can_stm32fd_read_mram,
555 	.write_mram = can_stm32fd_write_mram,
556 	.clear_mram = can_stm32fd_clear_mram,
557 };
558 
559 #define CAN_STM32FD_BUILD_ASSERT_MRAM_CFG(inst)					\
560 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_STD_FILTER_ELEMENTS(inst) == 28,	\
561 		     "Standard filter elements must be 28");			\
562 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_EXT_FILTER_ELEMENTS(inst) == 8,	\
563 		     "Extended filter elements must be 8");			\
564 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_FIFO0_ELEMENTS(inst) == 3,	\
565 		     "Rx FIFO 0 elements must be 3");				\
566 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_FIFO1_ELEMENTS(inst) == 3,	\
567 		     "Rx FIFO 1 elements must be 3");				\
568 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_RX_BUFFER_ELEMENTS(inst) == 0,	\
569 		     "Rx Buffer elements must be 0");				\
570 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_ELEMENTS(inst) == 3,	\
571 		     "Tx Event FIFO elements must be 3");			\
572 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst) == 3,	\
573 		     "Tx Buffer elements must be 0");
574 
575 #define CAN_STM32FD_IRQ_CFG_FUNCTION(inst)                                     \
576 static void config_can_##inst##_irq(void)                                      \
577 {                                                                              \
578 	LOG_DBG("Enable CAN" #inst " IRQ");                                    \
579 	IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, int0, irq),                      \
580 		    DT_INST_IRQ_BY_NAME(inst, int0, priority),                 \
581 		    can_mcan_line_0_isr, DEVICE_DT_INST_GET(inst), 0);         \
582 	irq_enable(DT_INST_IRQ_BY_NAME(inst, int0, irq));                      \
583 	IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, int1, irq),                      \
584 		    DT_INST_IRQ_BY_NAME(inst, int1, priority),                 \
585 		    can_mcan_line_1_isr, DEVICE_DT_INST_GET(inst), 0);         \
586 	irq_enable(DT_INST_IRQ_BY_NAME(inst, int1, irq));                      \
587 }
588 
589 #define CAN_STM32FD_CFG_INST(inst)					\
590 	BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(inst) <=	\
591 		     CAN_MCAN_DT_INST_MRAM_SIZE(inst),			\
592 		     "Insufficient Message RAM size to hold elements");	\
593 									\
594 	PINCTRL_DT_INST_DEFINE(inst);					\
595 	CAN_MCAN_CALLBACKS_DEFINE(can_stm32fd_cbs_##inst,		\
596 				  CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst), \
597 				  CONFIG_CAN_MAX_STD_ID_FILTER,		\
598 				  CONFIG_CAN_MAX_EXT_ID_FILTER);	\
599 									\
600 	static const struct stm32_pclken can_stm32fd_pclken_##inst[] =	\
601 					STM32_DT_INST_CLOCKS(inst);	\
602 									\
603 	static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
604 		.base = CAN_MCAN_DT_INST_MCAN_ADDR(inst),		\
605 		.mram = CAN_MCAN_DT_INST_MRAM_ADDR(inst),		\
606 		.pclken = can_stm32fd_pclken_##inst,			\
607 		.pclk_len = DT_INST_NUM_CLOCKS(inst),			\
608 		.config_irq = config_can_##inst##_irq,			\
609 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),		\
610 		.clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0)  \
611 	};								\
612 									\
613 	static const struct can_mcan_config can_mcan_cfg_##inst =	\
614 		CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_stm32fd_cfg_##inst, \
615 					    &can_stm32fd_ops,		\
616 					    &can_stm32fd_cbs_##inst);
617 
618 #define CAN_STM32FD_DATA_INST(inst)					\
619 	static struct can_mcan_data can_mcan_data_##inst =		\
620 		CAN_MCAN_DATA_INITIALIZER(NULL);
621 
622 #define CAN_STM32FD_DEVICE_INST(inst)						\
623 	CAN_DEVICE_DT_INST_DEFINE(inst, can_stm32fd_init, NULL,			\
624 				  &can_mcan_data_##inst, &can_mcan_cfg_##inst,	\
625 				  POST_KERNEL, CONFIG_CAN_INIT_PRIORITY,	\
626 				  &can_stm32fd_driver_api);
627 
628 #define CAN_STM32FD_INST(inst)          \
629 CAN_STM32FD_BUILD_ASSERT_MRAM_CFG(inst) \
630 CAN_STM32FD_IRQ_CFG_FUNCTION(inst)      \
631 CAN_STM32FD_CFG_INST(inst)              \
632 CAN_STM32FD_DATA_INST(inst)             \
633 CAN_STM32FD_DEVICE_INST(inst)
634 
635 DT_INST_FOREACH_STATUS_OKAY(CAN_STM32FD_INST)
636