1 /*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #include <soc.h>
7 #include <zephyr/logging/log.h>
8 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
9 #include <zephyr/drivers/pinctrl.h>
10 #include <zephyr/drivers/can.h>
11 #include <zephyr/drivers/can/transceiver.h>
12 #include "r_can_api.h"
13 #include "r_canfd.h"
14
15 LOG_MODULE_REGISTER(can_renesas_ra, CONFIG_CAN_LOG_LEVEL);
16
17 #define DT_DRV_COMPAT renesas_ra_canfd
18
19 #define CAN_RENESAS_RA_TIMING_MAX \
20 { \
21 .sjw = 128, \
22 .prop_seg = 1, \
23 .phase_seg1 = 255, \
24 .phase_seg2 = 128, \
25 .prescaler = 1024, \
26 }
27
28 #define CAN_RENESAS_RA_TIMING_MIN \
29 { \
30 .sjw = 1, \
31 .prop_seg = 1, \
32 .phase_seg1 = 2, \
33 .phase_seg2 = 2, \
34 .prescaler = 1, \
35 }
36
37 #ifdef CONFIG_CAN_FD_MODE
38 #define CAN_RENESAS_RA_TIMING_DATA_MAX \
39 { \
40 .sjw = 16, \
41 .prop_seg = 1, \
42 .phase_seg1 = 31, \
43 .phase_seg2 = 16, \
44 .prescaler = 128, \
45 }
46 #define CAN_RENESAS_RA_TIMING_DATA_MIN \
47 { \
48 .sjw = 1, \
49 .prop_seg = 1, \
50 .phase_seg1 = 2, \
51 .phase_seg2 = 2, \
52 .prescaler = 1, \
53 }
54 #endif
55
56 /* This frame ID will be reserved. Any filter using this ID may cause undefined behavior. */
57 #define CAN_RENESAS_RA_RESERVED_ID (CAN_EXT_ID_MASK)
58
59 /*
60 * Common FIFO configuration: refer to '34.2.28 CFDCFCC : Common FIFO Configuration/Control
61 * Register' - RA8M1 MCU group HWM
62 */
63 #define CANFD_CFG_COMMONFIFO0 (0U << R_CANFD_CFDCFCC_CFE_Pos) /* Common FIFO Disable */
64
65 #define CANFD_CFG_COMMONFIFO {CANFD_CFG_COMMONFIFO0}
66
67 /*
68 * RX FIFO configuration: refer to '34.2.25 CFDRFCCa : RX FIFO Configuration/Control Registers' -
69 * RA8M1 MCU group HWM
70 */
71 #define CANFD_CFG_RX_FIFO0 \
72 ((1U << R_CANFD_CFDRFCC_RFE_Pos) | /* RX FIFO Enable */ \
73 (1U << R_CANFD_CFDRFCC_RFIE_Pos) | /* RX FIFO Interrupt Enable */ \
74 (7U << R_CANFD_CFDRFCC_RFPLS_Pos) | /* RX FIFO Payload Data Size: 64 */ \
75 (3U << R_CANFD_CFDRFCC_RFDC_Pos) | /* RX FIFO Depth: 16 messages */ \
76 (1U << R_CANFD_CFDRFCC_RFIM_Pos)) /* Interrupt generated at every received message \
77 * storage \
78 */
79
80 #define CANFD_CFG_RX_FIFO1 (0U << R_CANFD_CFDRFCC_RFE_Pos) /* RX FIFO Disable */
81
82 #define CANFD_CFG_RXFIFO {CANFD_CFG_RX_FIFO0, CANFD_CFG_RX_FIFO1}
83
84 /*
85 * Global Configuration: refer to '34.2.11 CFDGCFG : Global Configuration Register' - RA8M1 MCU
86 * group HWM
87 */
88 #define CANFD_CFG_GLOBAL \
89 ((0U << R_CANFD_CFDGCFG_TPRI_Pos) | /* Transmission Priority: ID priority */ \
90 (0U << R_CANFD_CFDGCFG_DCE_Pos) | /* DLC check disabled */ \
91 (0U << R_CANFD_CFDGCFG_DCS_Pos)) /* DLL Clock Select: CANFDCLK */
92
93 /*
94 * TX Message Buffer Interrupt Enable Configuration: refer to '34.2.43 CFDTMIEC : TX Message Buffer
95 * Interrupt Enable Configuration Register' - RA8M1 MCU group HWM
96 */
97 #define CANFD_CFG_TXMB_TXI_ENABLE (BIT(0)) /* Enable TXMB0 interrupt */
98
99 /*
100 * Number and size of RX Message Buffers: refer to '34.2.23 CFDRMNB : RX Message Buffer Number
101 * Register' - RA8M1 MCU group HWM
102 */
103 #define CANFD_CFG_RXMB (0U << R_CANFD_CFDRMNB_NRXMB_Pos) /* Number of RX Message Buffers: 0 */
104
105 /*
106 * Channel Error IRQ configurations: refer to '34.2.3 CFDC0CTR : Control Register' - RA8M1 MCU group
107 * HWM
108 */
109 #define CANFD_CFG_ERR_IRQ \
110 (BIT(R_CANFD_CFDC_CTR_EWIE_Pos) | /* Error Warning Interrupt Enable */ \
111 BIT(R_CANFD_CFDC_CTR_EPIE_Pos) | /* Error Passive Interrupt Enable */ \
112 BIT(R_CANFD_CFDC_CTR_BOEIE_Pos) | /* Bus-Off Entry Interrupt Enable */ \
113 BIT(R_CANFD_CFDC_CTR_BORIE_Pos) | /* Bus-Off Recovery Interrupt Enable */ \
114 BIT(R_CANFD_CFDC_CTR_OLIE_Pos)) /* Overload Interrupt Enable */
115
116 /*
117 * Global Error IRQ configurations: refer to '34.2.12 CFDGCTR : Global Control Register' - RA8M1 MCU
118 * group HWM
119 */
120 #define CANFD_CFG_GLERR_IRQ \
121 ((3UL << R_CANFD_CFDGCTR_GMDC_Pos) | /* Global Mode Control: Keep current value */ \
122 (0UL << R_CANFD_CFDGCTR_DEIE_Pos) | /* DLC check interrupt disabled */ \
123 (0UL << R_CANFD_CFDGCTR_MEIE_Pos) | /* Message lost error interrupt disabled */ \
124 (0UL << R_CANFD_CFDGCTR_THLEIE_Pos) | /* TX history list entry lost interrupt disabled */ \
125 (0UL << R_CANFD_CFDGCTR_CMPOFIE_Pos)) /* CANFD message payload overflow flag interrupt \
126 * disabled \
127 */
128
129 /* Keycode to enable/disable accessing to AFL entry */
130 #define CFDGAFLIGNCTR_KEY_CODE (0xC4UL)
131
132 /* Default Dataphase bitrate configuration in case classic mode is enabled */
133 static const can_bit_timing_cfg_t classic_can_data_timing_default = {
134 .baud_rate_prescaler = 1,
135 .time_segment_1 = 3,
136 .time_segment_2 = 2,
137 .synchronization_jump_width = 1,
138 };
139
140 struct can_renesas_ra_global_cfg {
141 const struct device *op_clk;
142 const struct device *ram_clk;
143 const struct clock_control_ra_subsys_cfg op_subsys;
144 const struct clock_control_ra_subsys_cfg ram_subsys;
145 const unsigned int dll_min_freq;
146 const unsigned int dll_max_freq;
147 };
148
149 struct can_renesas_ra_filter {
150 bool set;
151 struct can_filter filter;
152 can_rx_callback_t rx_cb;
153 void *rx_usr_data;
154 };
155
156 struct can_renesas_ra_cfg {
157 struct can_driver_config common;
158 const struct pinctrl_dev_config *pcfg;
159 const struct device *global_dev;
160 const struct device *dll_clk;
161 const struct clock_control_ra_subsys_cfg dll_subsys;
162 const uint32_t rx_filter_num;
163 };
164
165 struct can_renesas_ra_data {
166 struct can_driver_data common;
167 struct k_mutex inst_mutex;
168 const struct device *dev;
169 can_instance_t fsp_can;
170 can_tx_callback_t tx_cb;
171 struct k_sem tx_sem;
172 void *tx_usr_data;
173 struct can_renesas_ra_filter *rx_filter;
174 can_bit_timing_cfg_t data_timing;
175 };
176
177 extern void canfd_error_isr(void);
178 extern void canfd_rx_fifo_isr(void);
179 extern void canfd_common_fifo_rx_isr(void);
180 extern void canfd_channel_tx_isr(void);
181
182 static const can_api_t *can_api = &g_canfd_on_canfd;
183
set_hw_timing_configuration(const struct device * dev,can_bit_timing_cfg_t * f_timing,const struct can_timing * z_timing)184 static inline int set_hw_timing_configuration(const struct device *dev,
185 can_bit_timing_cfg_t *f_timing,
186 const struct can_timing *z_timing)
187 {
188 struct can_renesas_ra_data *data = dev->data;
189
190 if (f_timing == NULL || z_timing == NULL) {
191 return -EINVAL;
192 }
193
194 k_mutex_lock(&data->inst_mutex, K_FOREVER);
195
196 *f_timing = (can_bit_timing_cfg_t){
197 .baud_rate_prescaler = z_timing->prescaler,
198 .time_segment_1 = z_timing->prop_seg + z_timing->phase_seg1,
199 .time_segment_2 = z_timing->phase_seg2,
200 .synchronization_jump_width = z_timing->sjw,
201 };
202
203 k_mutex_unlock(&data->inst_mutex);
204
205 return 0;
206 }
207
get_free_filter_id(const struct device * dev)208 static inline int get_free_filter_id(const struct device *dev)
209 {
210 struct can_renesas_ra_data *data = dev->data;
211 const struct can_renesas_ra_cfg *cfg = dev->config;
212
213 for (uint32_t filter_id = 0; filter_id < cfg->rx_filter_num; filter_id++) {
214 if (!data->rx_filter[filter_id].set) {
215 return filter_id;
216 }
217 }
218
219 return -ENOSPC;
220 }
221
set_afl_rule(const struct device * dev,const struct can_filter * filter,uint32_t afl_offset)222 static void set_afl_rule(const struct device *dev, const struct can_filter *filter,
223 uint32_t afl_offset)
224 {
225 struct can_renesas_ra_data *data = dev->data;
226 canfd_extended_cfg_t const *p_extend = data->fsp_can.p_cfg->p_extend;
227 canfd_afl_entry_t *afl = (canfd_afl_entry_t *)&p_extend->p_afl[afl_offset];
228
229 *afl = (canfd_afl_entry_t){.id = {.id = filter->id,
230 #ifndef CONFIG_CAN_ACCEPT_RTR
231 .frame_type = CAN_FRAME_TYPE_DATA,
232 #endif
233 .id_mode = ((filter->flags & CAN_FILTER_IDE) != 0)
234 ? CAN_ID_MODE_EXTENDED
235 : CAN_ID_MODE_STANDARD},
236 .mask = {.mask_id = filter->mask,
237 #ifdef CONFIG_CAN_ACCEPT_RTR
238 /* Accept all types of frames */
239 .mask_frame_type = 0,
240 #else
241 /* Only accept frames with the configured frametype */
242 .mask_frame_type = 1,
243 #endif
244 .mask_id_mode = ((filter->flags & CAN_FILTER_IDE) != 0)
245 ? CAN_ID_MODE_EXTENDED
246 : CAN_ID_MODE_STANDARD},
247 .destination = {.fifo_select_flags = CANFD_RX_FIFO_0}};
248
249 if (data->common.started) {
250 /* These steps help update AFL rules while CAN module running */
251 canfd_instance_ctrl_t *p_ctrl = (canfd_instance_ctrl_t *)data->fsp_can.p_ctrl;
252 R_CANFD_Type *reg = p_ctrl->p_reg;
253
254 /* Ignore AFL entry which will be changed */
255 reg->CFDGAFLIGNENT_b.IRN = afl_offset;
256 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos) |
257 BIT(R_CANFD_CFDGAFLIGNCTR_IREN_Pos));
258 reg->CFDGAFLECTR_b.AFLDAE = 1;
259
260 /* Write AFL configuration */
261 reg->CFDGAFL[afl_offset] = *(R_CANFD_CFDGAFL_Type *)afl;
262
263 /* Lock AFL entry access */
264 reg->CFDGAFLECTR_b.AFLDAE = 0;
265 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos));
266 }
267 }
268
remove_afl_rule(const struct device * dev,uint32_t afl_offset)269 static void remove_afl_rule(const struct device *dev, uint32_t afl_offset)
270 {
271 struct can_renesas_ra_data *data = dev->data;
272 canfd_extended_cfg_t const *p_extend = data->fsp_can.p_cfg->p_extend;
273 canfd_afl_entry_t *afl = (canfd_afl_entry_t *)&p_extend->p_afl[afl_offset];
274
275 /* Set the AFL ID to reserved ID */
276 *afl = (canfd_afl_entry_t){
277 .id = {.id = CAN_RENESAS_RA_RESERVED_ID, .id_mode = CAN_ID_MODE_EXTENDED},
278 .mask = {.mask_id = CAN_RENESAS_RA_RESERVED_ID,
279 .mask_id_mode = CAN_ID_MODE_EXTENDED}};
280
281 if (data->common.started) {
282 /* These steps help update AFL rules while CAN module running */
283 canfd_instance_ctrl_t *p_ctrl = (canfd_instance_ctrl_t *)data->fsp_can.p_ctrl;
284 R_CANFD_Type *reg = p_ctrl->p_reg;
285
286 /* Ignore AFL entry which will be changed */
287 reg->CFDGAFLIGNENT_b.IRN = afl_offset;
288 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos) |
289 BIT(R_CANFD_CFDGAFLIGNCTR_IREN_Pos));
290 reg->CFDGAFLECTR_b.AFLDAE = 1;
291
292 /* Change configurations for AFL entry */
293 reg->CFDGAFL[afl_offset] = *(R_CANFD_CFDGAFL_Type *)(afl);
294
295 /* Lock AFL entry access */
296 reg->CFDGAFLECTR_b.AFLDAE = 0;
297 reg->CFDGAFLIGNCTR = ((CFDGAFLIGNCTR_KEY_CODE << R_CANFD_CFDGAFLIGNCTR_KEY_Pos));
298 }
299 }
300
301 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
recover_bus(const struct device * dev,k_timeout_t timeout)302 static int recover_bus(const struct device *dev, k_timeout_t timeout)
303 {
304 struct can_renesas_ra_data *data = dev->data;
305 canfd_instance_ctrl_t *p_ctrl = data->fsp_can.p_ctrl;
306 R_CANFD_Type *reg = p_ctrl->p_reg;
307 uint32_t cfdcnctr = reg->CFDC->CTR;
308 int ret = 0;
309
310 if (reg->CFDC->ERFL_b.BOEF == 0) {
311 /* Channel bus-off entry not detected */
312 goto end;
313 }
314
315 reg->CFDC->CTR_b.BOM = 0x00; /* Switch to Normal Bus-Off mode (comply with ISO 11898-1) */
316 reg->CFDC->CTR_b.RTBO = 1; /* Force channel state to return from bus-off */
317
318 int64_t start_ticks = k_uptime_ticks();
319
320 while (reg->CFDC->ERFL_b.BORF == 0) {
321 if ((k_uptime_ticks() - start_ticks) > timeout.ticks) {
322 ret = -EAGAIN;
323 goto end;
324 }
325 }
326 end:
327 reg->CFDC->CTR = cfdcnctr; /* Restore channel configuration */
328 return ret;
329 }
330 #endif
331
can_renesas_ra_call_tx_cb(const struct device * dev,int err)332 static inline void can_renesas_ra_call_tx_cb(const struct device *dev, int err)
333 {
334 struct can_renesas_ra_data *data = dev->data;
335 can_tx_callback_t cb = data->tx_cb;
336
337 if (cb != NULL) {
338 data->tx_cb = NULL;
339 cb(dev, err, data->tx_usr_data);
340 k_sem_give(&data->tx_sem);
341 }
342 }
343
can_renesas_ra_call_rx_cb(const struct device * dev,can_callback_args_t * p_args)344 static inline void can_renesas_ra_call_rx_cb(const struct device *dev, can_callback_args_t *p_args)
345 {
346 struct can_renesas_ra_data *data = dev->data;
347 struct can_renesas_ra_filter *rx_filter = data->rx_filter;
348 const struct can_renesas_ra_cfg *cfg = dev->config;
349 struct can_frame frame = {
350 .dlc = can_bytes_to_dlc(p_args->frame.data_length_code),
351 .id = p_args->frame.id,
352 .flags = (((p_args->frame.id_mode == CAN_ID_MODE_EXTENDED) ? CAN_FRAME_IDE : 0UL) |
353 ((p_args->frame.type == CAN_FRAME_TYPE_REMOTE) ? CAN_FRAME_RTR : 0UL) |
354 ((p_args->frame.options & CANFD_FRAME_OPTION_FD) != 0 ? CAN_FRAME_FDF
355 : 0UL) |
356 ((p_args->frame.options & CANFD_FRAME_OPTION_ERROR) != 0 ? CAN_FRAME_ESI
357 : 0UL) |
358 ((p_args->frame.options & CANFD_FRAME_OPTION_BRS) != 0 ? CAN_FRAME_BRS
359 : 0UL)),
360 };
361
362 memcpy(frame.data, p_args->frame.data, p_args->frame.data_length_code);
363
364 for (uint32_t i = 0; i < cfg->rx_filter_num; i++) {
365 can_rx_callback_t cb = rx_filter->rx_cb;
366 void *usr_data = rx_filter->rx_usr_data;
367
368 if (cb == NULL) {
369 rx_filter++;
370 continue; /* this filter has not set yet */
371 }
372
373 if (!can_frame_matches_filter(&frame, &rx_filter->filter)) {
374 rx_filter++;
375 continue; /* filter did not match */
376 }
377
378 cb(dev, &frame, usr_data);
379 break;
380 }
381 }
382
can_renesas_ra_call_state_change_cb(const struct device * dev,enum can_state state)383 static inline void can_renesas_ra_call_state_change_cb(const struct device *dev,
384 enum can_state state)
385 {
386 struct can_renesas_ra_data *data = dev->data;
387 can_info_t can_info;
388
389 if (FSP_SUCCESS != can_api->infoGet(data->fsp_can.p_ctrl, &can_info)) {
390 LOG_DBG("get state info failed");
391 return;
392 }
393
394 struct can_bus_err_cnt err_cnt = {
395 .rx_err_cnt = can_info.error_count_receive,
396 .tx_err_cnt = can_info.error_count_transmit,
397 };
398
399 data->common.state_change_cb(dev, state, err_cnt, data->common.state_change_cb_user_data);
400 }
401
can_renesas_ra_get_capabilities(const struct device * dev,can_mode_t * cap)402 static int can_renesas_ra_get_capabilities(const struct device *dev, can_mode_t *cap)
403 {
404 ARG_UNUSED(dev);
405 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK;
406
407 #ifdef CONFIG_CAN_FD_MODE
408 *cap |= CAN_MODE_FD;
409 #endif
410
411 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
412 *cap |= CAN_MODE_MANUAL_RECOVERY;
413 #endif
414
415 return 0;
416 }
417
can_renesas_ra_start(const struct device * dev)418 static int can_renesas_ra_start(const struct device *dev)
419 {
420 struct can_renesas_ra_data *data = dev->data;
421 const struct device *transceiver_dev = can_get_transceiver(dev);
422 int ret = 0;
423
424 if (!device_is_ready(dev)) {
425 return -EIO;
426 }
427
428 if (data->common.started) {
429 return -EALREADY;
430 }
431
432 if (((transceiver_dev != NULL) &&
433 can_transceiver_enable(transceiver_dev, data->common.mode))) {
434 LOG_DBG("CAN transceiver enable failed");
435 return -EIO;
436 }
437
438 k_mutex_lock(&data->inst_mutex, K_FOREVER);
439 canfd_extended_cfg_t *p_extend = (canfd_extended_cfg_t *)data->fsp_can.p_cfg->p_extend;
440
441 p_extend->p_data_timing =
442 (can_bit_timing_cfg_t *)((data->common.mode & CAN_MODE_FD) != 0
443 ? &data->data_timing
444 : &classic_can_data_timing_default);
445
446 if (FSP_SUCCESS != can_api->close(data->fsp_can.p_ctrl)) {
447 LOG_DBG("CAN close failed");
448 ret = -EIO;
449 goto end;
450 }
451
452 if (FSP_SUCCESS != can_api->open(data->fsp_can.p_ctrl, data->fsp_can.p_cfg)) {
453 LOG_DBG("CAN open failed");
454 ret = -EIO;
455 goto end;
456 }
457
458 if ((data->common.mode & CAN_MODE_LOOPBACK) != 0) {
459 if (FSP_SUCCESS != can_api->modeTransition(data->fsp_can.p_ctrl,
460 CAN_OPERATION_MODE_NORMAL,
461 CAN_TEST_MODE_LOOPBACK_INTERNAL)) {
462 LOG_DBG("CAN mode change failed");
463 ret = -EIO;
464 goto end;
465 }
466 }
467
468 data->common.started = true;
469 end:
470 k_mutex_unlock(&data->inst_mutex);
471 return ret;
472 }
473
can_renesas_ra_stop(const struct device * dev)474 static int can_renesas_ra_stop(const struct device *dev)
475 {
476 struct can_renesas_ra_data *data = dev->data;
477 const struct device *transceiver_dev = can_get_transceiver(dev);
478 int ret = 0;
479
480 if (!data->common.started) {
481 return -EALREADY;
482 }
483
484 k_mutex_lock(&data->inst_mutex, K_FOREVER);
485
486 if (FSP_SUCCESS != can_api->modeTransition(data->fsp_can.p_ctrl, CAN_OPERATION_MODE_HALT,
487 CAN_TEST_MODE_DISABLED)) {
488 LOG_DBG("CAN stop failed");
489 ret = -EIO;
490 goto end;
491 }
492
493 if (((transceiver_dev != NULL) && can_transceiver_disable(transceiver_dev))) {
494 LOG_DBG("CAN transceiver disable failed");
495 ret = -EIO;
496 goto end;
497 }
498
499 if (data->tx_cb != NULL) {
500 data->tx_cb = NULL;
501 k_sem_give(&data->tx_sem);
502 }
503
504 data->common.started = false;
505
506 end:
507 k_mutex_unlock(&data->inst_mutex);
508 return ret;
509 }
510
can_renesas_ra_set_mode(const struct device * dev,can_mode_t mode)511 static int can_renesas_ra_set_mode(const struct device *dev, can_mode_t mode)
512 {
513 struct can_renesas_ra_data *data = dev->data;
514 int ret = 0;
515
516 if (data->common.started) {
517 /* CAN controller should be in stopped state */
518 return -EBUSY;
519 }
520
521 k_mutex_lock(&data->inst_mutex, K_FOREVER);
522
523 can_mode_t caps = 0;
524
525 ret = can_renesas_ra_get_capabilities(dev, &caps);
526 if (ret != 0) {
527 goto end;
528 }
529
530 if ((mode & ~caps) != 0) {
531 ret = -ENOTSUP;
532 goto end;
533 }
534
535 data->common.mode = mode;
536
537 end:
538 k_mutex_unlock(&data->inst_mutex);
539 return ret;
540 }
541
can_renesas_ra_set_timing(const struct device * dev,const struct can_timing * timing)542 static int can_renesas_ra_set_timing(const struct device *dev, const struct can_timing *timing)
543 {
544 struct can_renesas_ra_data *data = dev->data;
545
546 if (data->common.started) {
547 /* Device is not in stopped state */
548 return -EBUSY;
549 }
550
551 return set_hw_timing_configuration(dev, data->fsp_can.p_cfg->p_bit_timing, timing);
552 }
553
can_renesas_ra_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)554 static int can_renesas_ra_send(const struct device *dev, const struct can_frame *frame,
555 k_timeout_t timeout, can_tx_callback_t callback, void *user_data)
556 {
557 struct can_renesas_ra_data *data = dev->data;
558
559 if (!data->common.started) {
560 return -ENETDOWN;
561 }
562
563 #ifdef CONFIG_CAN_FD_MODE
564 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR | CAN_FRAME_FDF | CAN_FRAME_BRS)) !=
565 0) {
566 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
567 return -ENOTSUP;
568 }
569
570 if ((data->common.mode & CAN_MODE_FD) == 0U &&
571 ((frame->flags & (CAN_FRAME_FDF | CAN_FRAME_BRS)) != 0U)) {
572 LOG_ERR("CAN FD format not supported in non-FD mode");
573 return -ENOTSUP;
574 }
575 #else /* CONFIG_CAN_FD_MODE */
576 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0U) {
577 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
578 return -ENOTSUP;
579 }
580 #endif /* !CONFIG_CAN_FD_MODE */
581
582 if ((frame->flags & CAN_FRAME_FDF) != 0U) {
583 if (frame->dlc > CANFD_MAX_DLC) {
584 LOG_ERR("DLC of %d for CAN FD format frame", frame->dlc);
585 return -EINVAL;
586 }
587 } else {
588 if (frame->dlc > CAN_MAX_DLC) {
589 LOG_ERR("DLC of %d for non-FD format frame", frame->dlc);
590 return -EINVAL;
591 }
592 }
593
594 if (k_sem_take(&data->tx_sem, timeout) != 0) {
595 return -EAGAIN;
596 }
597
598 k_mutex_lock(&data->inst_mutex, K_FOREVER);
599 int ret = 0;
600
601 data->tx_cb = callback;
602 data->tx_usr_data = user_data;
603
604 can_frame_t fsp_frame = {
605 .id = frame->id,
606 .id_mode = ((frame->flags & CAN_FRAME_IDE) != 0) ? CAN_ID_MODE_EXTENDED
607 : CAN_ID_MODE_STANDARD,
608 .type = ((frame->flags & CAN_FRAME_RTR) != 0) ? CAN_FRAME_TYPE_REMOTE
609 : CAN_FRAME_TYPE_DATA,
610 .data_length_code = can_dlc_to_bytes(frame->dlc),
611 .options =
612 ((((frame->flags & CAN_FRAME_FDF) != 0) ? CANFD_FRAME_OPTION_FD : 0UL) |
613 (((frame->flags & CAN_FRAME_BRS) != 0) ? CANFD_FRAME_OPTION_BRS : 0UL) |
614 (((frame->flags & CAN_FRAME_ESI) != 0) ? CANFD_FRAME_OPTION_ERROR : 0UL)),
615 };
616
617 memcpy(fsp_frame.data, frame->data, fsp_frame.data_length_code);
618
619 if (FSP_SUCCESS != can_api->write(data->fsp_can.p_ctrl, CANFD_TX_BUFFER_0, &fsp_frame)) {
620 LOG_DBG("CAN transmit failed");
621 data->tx_cb = NULL;
622 data->tx_usr_data = NULL;
623 k_sem_give(&data->tx_sem);
624 ret = -EIO;
625 goto end;
626 }
627
628 end:
629 k_mutex_unlock(&data->inst_mutex);
630 return ret;
631 }
632
can_renesas_ra_add_rx_filter(const struct device * dev,can_rx_callback_t callback,void * user_data,const struct can_filter * filter)633 static int can_renesas_ra_add_rx_filter(const struct device *dev, can_rx_callback_t callback,
634 void *user_data, const struct can_filter *filter)
635 {
636 struct can_renesas_ra_data *data = dev->data;
637 int filter_id = -ENOSPC;
638
639 k_mutex_lock(&data->inst_mutex, K_FOREVER);
640
641 filter_id = get_free_filter_id(dev);
642 if (filter_id == -ENOSPC) {
643 goto end;
644 }
645
646 set_afl_rule(dev, filter, filter_id);
647
648 memcpy(&data->rx_filter[filter_id].filter, filter, sizeof(struct can_filter));
649 data->rx_filter[filter_id].rx_cb = callback;
650 data->rx_filter[filter_id].rx_usr_data = user_data;
651 data->rx_filter[filter_id].set = true;
652
653 end:
654 k_mutex_unlock(&data->inst_mutex);
655 return filter_id;
656 }
657
can_renesas_ra_remove_rx_filter(const struct device * dev,int filter_id)658 static void can_renesas_ra_remove_rx_filter(const struct device *dev, int filter_id)
659 {
660 struct can_renesas_ra_data *data = dev->data;
661 const struct can_renesas_ra_cfg *cfg = dev->config;
662
663 if ((filter_id < 0) || (filter_id >= cfg->rx_filter_num)) {
664 return;
665 }
666
667 k_mutex_lock(&data->inst_mutex, K_FOREVER);
668
669 remove_afl_rule(dev, filter_id);
670
671 data->rx_filter[filter_id].rx_cb = NULL;
672 data->rx_filter[filter_id].rx_usr_data = NULL;
673 data->rx_filter[filter_id].set = false;
674
675 k_mutex_unlock(&data->inst_mutex);
676 }
677
678 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
can_renesas_ra_recover(const struct device * dev,k_timeout_t timeout)679 static int can_renesas_ra_recover(const struct device *dev, k_timeout_t timeout)
680 {
681 struct can_renesas_ra_data *data = dev->data;
682
683 if (!data->common.started) {
684 return -ENETDOWN;
685 }
686
687 if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0) {
688 return -ENOTSUP;
689 }
690
691 return recover_bus(dev, timeout);
692 }
693 #endif
694
can_renesas_ra_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)695 static int can_renesas_ra_get_state(const struct device *dev, enum can_state *state,
696 struct can_bus_err_cnt *err_cnt)
697 {
698 struct can_renesas_ra_data *data = dev->data;
699 can_info_t fsp_info = {0};
700
701 if (state == NULL && err_cnt == NULL) {
702 return 0;
703 }
704
705 if (FSP_SUCCESS != can_api->infoGet(data->fsp_can.p_ctrl, &fsp_info)) {
706 LOG_DBG("CAN get state info failed");
707 return -EIO;
708 }
709
710 if (state != NULL) {
711 if (!data->common.started) {
712 *state = CAN_STATE_STOPPED;
713 } else {
714 if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_BOEF_Msk) != 0) {
715 *state = CAN_STATE_BUS_OFF;
716 } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_EPF_Msk) != 0) {
717 *state = CAN_STATE_ERROR_PASSIVE;
718 } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_EWF_Msk) != 0) {
719 *state = CAN_STATE_ERROR_WARNING;
720 } else if ((fsp_info.error_code & R_CANFD_CFDC_ERFL_BEF_Msk) != 0) {
721 *state = CAN_STATE_ERROR_ACTIVE;
722 }
723 }
724 }
725
726 if (err_cnt != NULL) {
727 err_cnt->tx_err_cnt = fsp_info.error_count_transmit;
728 err_cnt->rx_err_cnt = fsp_info.error_count_receive;
729 }
730
731 return 0;
732 }
733
can_renesas_ra_set_state_change_callback(const struct device * dev,can_state_change_callback_t callback,void * user_data)734 static void can_renesas_ra_set_state_change_callback(const struct device *dev,
735 can_state_change_callback_t callback,
736 void *user_data)
737 {
738 struct can_renesas_ra_data *data = dev->data;
739 canfd_instance_ctrl_t *p_ctrl = data->fsp_can.p_ctrl;
740 int key = irq_lock();
741
742 k_mutex_lock(&data->inst_mutex, K_FOREVER);
743
744 if (callback != NULL) {
745 /* Enable state change interrupt */
746 p_ctrl->p_reg->CFDC->CTR |= (uint32_t)CANFD_CFG_ERR_IRQ;
747 } else {
748 /* Disable state change interrupt */
749 p_ctrl->p_reg->CFDC->CTR &= (uint32_t)~CANFD_CFG_ERR_IRQ;
750
751 /* Clear state change interrupt flags */
752 p_ctrl->p_reg->CFDC->ERFL &=
753 ~(BIT(R_CANFD_CFDC_ERFL_BOEF_Pos) | BIT(R_CANFD_CFDC_ERFL_EWF_Pos) |
754 BIT(R_CANFD_CFDC_ERFL_EPF_Pos) | BIT(R_CANFD_CFDC_ERFL_BOEF_Pos));
755 }
756
757 data->common.state_change_cb = callback;
758 data->common.state_change_cb_user_data = user_data;
759
760 k_mutex_unlock(&data->inst_mutex);
761
762 irq_unlock(key);
763 }
764
can_renesas_ra_get_core_clock(const struct device * dev,uint32_t * rate)765 static int can_renesas_ra_get_core_clock(const struct device *dev, uint32_t *rate)
766 {
767 const struct can_renesas_ra_cfg *cfg = dev->config;
768 clock_control_subsys_t dll_subsys = (clock_control_subsys_t)&cfg->dll_subsys;
769
770 return clock_control_get_rate(cfg->dll_clk, dll_subsys, rate);
771 }
772
can_renesas_ra_get_max_filters(const struct device * dev,bool ide)773 static int can_renesas_ra_get_max_filters(const struct device *dev, bool ide)
774 {
775 ARG_UNUSED(ide);
776 const struct can_renesas_ra_cfg *cfg = dev->config;
777
778 return cfg->rx_filter_num;
779 }
780
781 #ifdef CONFIG_CAN_FD_MODE
can_renesas_ra_set_timing_data(const struct device * dev,const struct can_timing * timing_data)782 static int can_renesas_ra_set_timing_data(const struct device *dev,
783 const struct can_timing *timing_data)
784 {
785 struct can_renesas_ra_data *data = dev->data;
786
787 if (data->common.started) {
788 return -EBUSY;
789 }
790
791 return set_hw_timing_configuration(dev, &data->data_timing, timing_data);
792 }
793 #endif /* CONFIG_CAN_FD_MODE */
794
can_renesas_ra_fsp_cb(can_callback_args_t * p_args)795 void can_renesas_ra_fsp_cb(can_callback_args_t *p_args)
796 {
797 const struct device *dev = p_args->p_context;
798
799 switch (p_args->event) {
800 case CAN_EVENT_RX_COMPLETE: {
801 can_renesas_ra_call_rx_cb(dev, p_args);
802 break;
803 }
804
805 case CAN_EVENT_TX_COMPLETE: {
806 can_renesas_ra_call_tx_cb(dev, 0);
807 break;
808 }
809
810 case CAN_EVENT_ERR_CHANNEL: {
811 if ((p_args->error & R_CANFD_CFDC_ERFL_BEF_Msk) != 0) {
812 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_ERROR_ACTIVE);
813 }
814 if ((p_args->error & R_CANFD_CFDC_ERFL_EWF_Msk) != 0) {
815 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_ERROR_WARNING);
816 }
817 if ((p_args->error & R_CANFD_CFDC_ERFL_EPF_Msk) != 0) {
818 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_ERROR_PASSIVE);
819 }
820 if ((p_args->error & R_CANFD_CFDC_ERFL_BOEF_Msk) != 0) {
821 can_renesas_ra_call_state_change_cb(dev, CAN_STATE_BUS_OFF);
822 }
823
824 if ((p_args->error & R_CANFD_CFDC_ERFL_ALF_Msk) != 0) { /* Arbitration Lost Error */
825 can_renesas_ra_call_tx_cb(dev, -EBUSY);
826 }
827 if ((p_args->error & (R_CANFD_CFDC_ERFL_AERR_Msk | /* ACK Error */
828 R_CANFD_CFDC_ERFL_ADERR_Msk | /* ACK Delimiter Error */
829 R_CANFD_CFDC_ERFL_B1ERR_Msk | /* Bit 1 Error */
830 R_CANFD_CFDC_ERFL_B0ERR_Msk)) /* Bit 0 Error */
831 != 0) {
832 can_renesas_ra_call_tx_cb(dev, -EIO);
833 }
834 }
835
836 default:
837 break;
838 }
839 }
840
can_renesas_ra_apply_default_config(const struct device * dev)841 static inline int can_renesas_ra_apply_default_config(const struct device *dev)
842 {
843 struct can_renesas_ra_cfg *cfg = (struct can_renesas_ra_cfg *)dev->config;
844 int ret;
845
846 struct can_timing timing = {0};
847
848 /* Calculate bit_timing parameter */
849 ret = can_calc_timing(dev, &timing, cfg->common.bitrate, cfg->common.sample_point);
850 if (ret < 0) {
851 return ret;
852 }
853
854 ret = can_renesas_ra_set_timing(dev, &timing);
855 if (ret != 0) {
856 return ret;
857 }
858
859 #ifdef CONFIG_CAN_FD_MODE
860 can_calc_timing_data(dev, &timing, cfg->common.bitrate_data, cfg->common.sample_point_data);
861 ret = can_renesas_ra_set_timing_data(dev, &timing);
862 if (ret < 0) {
863 return ret;
864 }
865 #endif
866
867 for (uint32_t filter_id = 0; filter_id < cfg->rx_filter_num; filter_id++) {
868 remove_afl_rule(dev, filter_id);
869 }
870
871 return 0;
872 }
873
can_renesas_module_clock_init(const struct device * dev)874 static inline int can_renesas_module_clock_init(const struct device *dev)
875 {
876 const struct can_renesas_ra_cfg *cfg = dev->config;
877 const struct can_renesas_ra_global_cfg *global_cfg = cfg->global_dev->config;
878 int ret;
879
880 ret = clock_control_on(cfg->dll_clk, (clock_control_subsys_t)&cfg->dll_subsys);
881 if (ret < 0) {
882 return -EIO;
883 }
884
885 uint32_t op_rate;
886 uint32_t ram_rate;
887 uint32_t dll_rate;
888
889 ret = clock_control_get_rate(global_cfg->op_clk,
890 (clock_control_subsys_t)&global_cfg->op_subsys, &op_rate);
891 if (ret < 0) {
892 return ret;
893 }
894
895 ret = clock_control_get_rate(global_cfg->ram_clk,
896 (clock_control_subsys_t)&global_cfg->ram_subsys, &ram_rate);
897 if (ret < 0) {
898 return ret;
899 }
900
901 ret = clock_control_get_rate(cfg->dll_clk, (clock_control_subsys_t)&cfg->dll_subsys,
902 &dll_rate);
903 if (ret < 0) {
904 return ret;
905 }
906
907 if (dll_rate < global_cfg->dll_min_freq || dll_rate > global_cfg->dll_max_freq) {
908 LOG_ERR("%s frequency is out of supported range: %d < %s freq < %d",
909 cfg->dll_clk->name, global_cfg->dll_min_freq, cfg->dll_clk->name,
910 global_cfg->dll_max_freq);
911 return -ENOTSUP;
912 }
913
914 /* Clock constraint: refer to '34.1.2 Clock restriction' - RA8M1 MCU group HWM */
915 /*
916 * Operation clock rate must be at least 40Mhz in case CANFD mode.
917 * Otherwise, it must be at least 32MHz.
918 */
919 if (IS_ENABLED(CONFIG_CAN_FD_MODE) ? op_rate < MHZ(40) : op_rate < MHZ(32)) {
920 LOG_ERR("%s frequency should be at least %d", global_cfg->op_clk->name,
921 IS_ENABLED(CONFIG_CAN_FD_MODE) ? MHZ(40) : MHZ(32));
922 return -ENOTSUP;
923 }
924
925 /*
926 * (RAM clock rate / 2) >= DLL rate
927 * (CANFD operation clock rate) >= DLL rate
928 */
929 if ((ram_rate / 2) < dll_rate || op_rate < dll_rate) {
930 LOG_ERR("%s frequency should be less than half of %s and %s frequency should "
931 "be less than %s",
932 global_cfg->ram_clk->name, cfg->dll_clk->name, global_cfg->op_clk->name,
933 cfg->dll_clk->name);
934 return -ENOTSUP;
935 }
936
937 return 0;
938 }
939
can_renesas_ra_init(const struct device * dev)940 static int can_renesas_ra_init(const struct device *dev)
941 {
942 const struct can_renesas_ra_cfg *cfg = dev->config;
943 struct can_renesas_ra_data *data = dev->data;
944 int ret = 0;
945
946 k_mutex_init(&data->inst_mutex);
947 k_sem_init(&data->tx_sem, 1, 1);
948 data->common.started = false;
949
950 ret = can_renesas_module_clock_init(dev);
951 if (ret < 0) {
952 LOG_DBG("clock initialize failed");
953 return ret;
954 }
955
956 /* Configure dt provided device signals when available */
957 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
958 if (ret < 0) {
959 LOG_DBG("pin function initial failed");
960 return ret;
961 }
962
963 /* Apply config and setting for CAN controller HW */
964 ret = can_renesas_ra_apply_default_config(dev);
965 if (ret < 0) {
966 LOG_DBG("invalid default configuration");
967 return ret;
968 }
969
970 ret = can_api->open(data->fsp_can.p_ctrl, data->fsp_can.p_cfg);
971 if (ret != FSP_SUCCESS) {
972 LOG_DBG("CAN bus initialize failed");
973 return -EIO;
974 }
975
976 /* Put CAN controller into stopped state */
977 ret = can_api->modeTransition(data->fsp_can.p_ctrl, CAN_OPERATION_MODE_HALT,
978 CAN_TEST_MODE_DISABLED);
979 if (ret != FSP_SUCCESS) {
980 can_api->close(data->fsp_can.p_ctrl);
981 LOG_DBG("CAN bus initialize failed");
982 return -EIO;
983 }
984
985 return 0;
986 }
987
988 static DEVICE_API(can, can_renesas_ra_driver_api) = {
989 .get_capabilities = can_renesas_ra_get_capabilities,
990 .start = can_renesas_ra_start,
991 .stop = can_renesas_ra_stop,
992 .set_mode = can_renesas_ra_set_mode,
993 .set_timing = can_renesas_ra_set_timing,
994 .send = can_renesas_ra_send,
995 .add_rx_filter = can_renesas_ra_add_rx_filter,
996 .remove_rx_filter = can_renesas_ra_remove_rx_filter,
997 #if defined(CONFIG_CAN_MANUAL_RECOVERY_MODE)
998 .recover = can_renesas_ra_recover,
999 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
1000 .get_state = can_renesas_ra_get_state,
1001 .set_state_change_callback = can_renesas_ra_set_state_change_callback,
1002 .get_core_clock = can_renesas_ra_get_core_clock,
1003 .get_max_filters = can_renesas_ra_get_max_filters,
1004 .timing_min = CAN_RENESAS_RA_TIMING_MIN,
1005 .timing_max = CAN_RENESAS_RA_TIMING_MAX,
1006 #if defined(CONFIG_CAN_FD_MODE)
1007 .set_timing_data = can_renesas_ra_set_timing_data,
1008 .timing_data_min = CAN_RENESAS_RA_TIMING_DATA_MIN,
1009 .timing_data_max = CAN_RENESAS_RA_TIMING_DATA_MAX,
1010 #endif /* CONFIG_CAN_FD_MODE */
1011 };
1012
1013 #define CAN_RENESAS_RA_GLOBAL_IRQ_INIT() \
1014 R_ICU->IELSR_b[VECTOR_NUMBER_CAN_GLERR].IELS = BSP_PRV_IELS_ENUM(EVENT_CAN_GLERR); \
1015 R_ICU->IELSR_b[VECTOR_NUMBER_CAN_RXF].IELS = BSP_PRV_IELS_ENUM(EVENT_CAN_RXF); \
1016 IRQ_CONNECT(VECTOR_NUMBER_CAN_GLERR, \
1017 DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), glerr, priority), \
1018 canfd_error_isr, NULL, 0); \
1019 IRQ_CONNECT(VECTOR_NUMBER_CAN_RXF, \
1020 DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), rxf, priority), \
1021 canfd_rx_fifo_isr, NULL, 0); \
1022 irq_enable(VECTOR_NUMBER_CAN_RXF); \
1023 irq_enable(VECTOR_NUMBER_CAN_GLERR);
1024
1025 static canfd_global_cfg_t g_canfd_global_cfg = {
1026 .global_interrupts = CANFD_CFG_GLERR_IRQ,
1027 .global_config = CANFD_CFG_GLOBAL,
1028 .rx_mb_config = CANFD_CFG_RXMB,
1029 .global_err_ipl = DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), glerr, priority),
1030 .rx_fifo_ipl = DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), rxf, priority),
1031 .rx_fifo_config = CANFD_CFG_RXFIFO,
1032 .common_fifo_config = CANFD_CFG_COMMONFIFO,
1033 };
1034
1035 static const struct can_renesas_ra_global_cfg g_can_renesas_ra_global_cfg = {
1036 .op_clk = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(DT_INST(0, renesas_ra_canfd_global), opclk)),
1037 .ram_clk =
1038 DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(DT_INST(0, renesas_ra_canfd_global), ramclk)),
1039 .op_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global), opclk,
1040 mstp),
1041 .stop_bit = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global), opclk,
1042 stop_bit)},
1043 .ram_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global), ramclk,
1044 mstp),
1045 .stop_bit = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global),
1046 ramclk, stop_bit)},
1047 .dll_min_freq = DT_PROP_OR(DT_INST(0, renesas_ra_canfd_global), dll_min_freq, 0),
1048 .dll_max_freq = DT_PROP_OR(DT_INST(0, renesas_ra_canfd_global), dll_max_freq, UINT_MAX),
1049 };
1050
can_renesas_ra_global_init(const struct device * dev)1051 static int can_renesas_ra_global_init(const struct device *dev)
1052 {
1053 int ret;
1054 const struct can_renesas_ra_global_cfg *cfg = dev->config;
1055
1056 ret = clock_control_on(cfg->op_clk, (clock_control_subsys_t)&cfg->op_subsys);
1057 if (ret < 0) {
1058 LOG_DBG("clock initialize failed");
1059 return ret;
1060 }
1061
1062 ret = clock_control_on(cfg->ram_clk, (clock_control_subsys_t)&cfg->ram_subsys);
1063 if (ret < 0) {
1064 LOG_DBG("clock initialize failed");
1065 return ret;
1066 }
1067
1068 CAN_RENESAS_RA_GLOBAL_IRQ_INIT();
1069
1070 return 0;
1071 }
1072
1073 DEVICE_DT_DEFINE(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), can_renesas_ra_global_init,
1074 NULL, NULL, &g_can_renesas_ra_global_cfg, PRE_KERNEL_2, CONFIG_CAN_INIT_PRIORITY,
1075 NULL)
1076
1077 #define EVENT_CAN_COMFRX(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_CAN, channel, _COMFRX))
1078 #define EVENT_CAN_TX(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_CAN, channel, _TX))
1079 #define EVENT_CAN_CHERR(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_CAN, channel, _CHERR))
1080
1081 #define CAN_RENESAS_RA_CHANNEL_IRQ_INIT(index) \
1082 { \
1083 R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, rx, irq)].IELS = \
1084 EVENT_CAN_COMFRX(DT_INST_PROP(index, channel)); \
1085 R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, tx, irq)].IELS = \
1086 EVENT_CAN_TX(DT_INST_PROP(index, channel)); \
1087 R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, err, irq)].IELS = \
1088 EVENT_CAN_CHERR(DT_INST_PROP(index, channel)); \
1089 \
1090 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, rx, irq), \
1091 DT_INST_IRQ_BY_NAME(index, rx, priority), canfd_common_fifo_rx_isr, \
1092 NULL, 0); \
1093 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, tx, irq), \
1094 DT_INST_IRQ_BY_NAME(index, tx, priority), canfd_channel_tx_isr, NULL, \
1095 0); \
1096 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, err, irq), \
1097 DT_INST_IRQ_BY_NAME(index, err, priority), canfd_error_isr, NULL, 0); \
1098 \
1099 irq_enable(DT_INST_IRQ_BY_NAME(index, rx, irq)); \
1100 irq_enable(DT_INST_IRQ_BY_NAME(index, tx, irq)); \
1101 irq_enable(DT_INST_IRQ_BY_NAME(index, err, irq)); \
1102 }
1103
1104 #define CAN_RENESAS_RA_INIT(index) \
1105 PINCTRL_DT_INST_DEFINE(index); \
1106 static canfd_afl_entry_t canfd_afl##index[DT_INST_PROP(index, rx_max_filters)]; \
1107 struct can_renesas_ra_filter \
1108 can_renesas_ra_rx_filter##index[DT_INST_PROP(index, rx_max_filters)]; \
1109 static can_bit_timing_cfg_t g_canfd_bit_timing##index; \
1110 static const struct can_renesas_ra_cfg can_renesas_ra_cfg##index = { \
1111 .common = CAN_DT_DRIVER_CONFIG_INST_GET(index, 0, 5000000), \
1112 .global_dev = DEVICE_DT_GET(DT_INST_PARENT(index)), \
1113 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
1114 .dll_clk = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(index, dllclk)), \
1115 .dll_subsys = \
1116 { \
1117 .mstp = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, mstp), \
1118 .stop_bit = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, stop_bit), \
1119 }, \
1120 .rx_filter_num = DT_INST_PROP(index, rx_max_filters), \
1121 }; \
1122 static canfd_instance_ctrl_t fsp_canfd_ctrl##index; \
1123 static canfd_extended_cfg_t fsp_canfd_extend####index = { \
1124 .p_afl = canfd_afl##index, \
1125 .txmb_txi_enable = CANFD_CFG_TXMB_TXI_ENABLE, \
1126 .error_interrupts = 0U, \
1127 .p_global_cfg = &g_canfd_global_cfg, \
1128 }; \
1129 static can_cfg_t fsp_canfd_cfg####index = { \
1130 .channel = DT_INST_PROP(index, channel), \
1131 .ipl = DT_INST_IRQ_BY_NAME(index, err, priority), \
1132 .error_irq = DT_INST_IRQ_BY_NAME(index, err, irq), \
1133 .rx_irq = DT_INST_IRQ_BY_NAME(index, rx, irq), \
1134 .tx_irq = DT_INST_IRQ_BY_NAME(index, tx, irq), \
1135 .p_extend = &fsp_canfd_extend##index, \
1136 .p_bit_timing = &g_canfd_bit_timing##index, \
1137 .p_context = DEVICE_DT_INST_GET(index), \
1138 .p_callback = can_renesas_ra_fsp_cb, \
1139 }; \
1140 static struct can_renesas_ra_data can_renesas_ra_data##index = { \
1141 .fsp_can = \
1142 { \
1143 .p_ctrl = &fsp_canfd_ctrl##index, \
1144 .p_cfg = &fsp_canfd_cfg##index, \
1145 .p_api = &g_canfd_on_canfd, \
1146 }, \
1147 .rx_filter = can_renesas_ra_rx_filter##index, \
1148 .dev = DEVICE_DT_INST_GET(index), \
1149 }; \
1150 static int can_renesas_ra_init##index(const struct device *dev) \
1151 { \
1152 const struct device *global_canfd = DEVICE_DT_GET(DT_INST_PARENT(index)); \
1153 if (!device_is_ready(global_canfd)) { \
1154 return -EIO; \
1155 } \
1156 CAN_RENESAS_RA_CHANNEL_IRQ_INIT(index) \
1157 return can_renesas_ra_init(dev); \
1158 } \
1159 CAN_DEVICE_DT_INST_DEFINE(index, can_renesas_ra_init##index, NULL, \
1160 &can_renesas_ra_data##index, &can_renesas_ra_cfg##index, \
1161 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
1162 &can_renesas_ra_driver_api);
1163
1164 DT_INST_FOREACH_STATUS_OKAY(CAN_RENESAS_RA_INIT)
1165
