1/*
2 * NOTE: Autogenerated file by gen_board_pinctrl.py
3 * for MKE18F512VLL16/signal_configuration.xml
4 *
5 * Copyright (c) 2022, NXP
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9
10#include <nxp/kinetis/MKE18F512VLL16-pinctrl.h>
11
12&pinctrl {
13	adc0_default: adc0_default {
14		group0 {
15			pinmux = <ADC0_SE0_PTA0>,
16				<ADC0_SE1_PTA1>,
17				<ADC0_SE12_PTC14>;
18			drive-strength = "low";
19			slew-rate = "slow";
20		};
21	};
22
23	dac0_default: dac0_default {
24		group0 {
25			pinmux = <DAC0_OUT_PTE9>;
26			drive-strength = "low";
27			slew-rate = "slow";
28		};
29	};
30
31	flexcan0_default: flexcan0_default {
32		group0 {
33			pinmux = <CAN0_RX_PTE4>,
34				<CAN0_TX_PTE5>;
35			drive-strength = "low";
36			slew-rate = "slow";
37		};
38	};
39
40	/* Route FLEXIO CLOCKOUT pin */
41	flexio_clockout: flexio_clockout {
42		group0 {
43			pinmux = <CLKOUT_PTE10>;
44			drive-strength = "low";
45			slew-rate = "slow";
46		};
47	};
48
49	ftm0_default: ftm0_default {
50		group0 {
51			pinmux = <FTM0_CH0_PTD15>,
52				<FTM0_CH1_PTD16>,
53				<FTM0_CH5_PTB5>;
54			drive-strength = "low";
55			slew-rate = "slow";
56		};
57	};
58
59	ftm3_default: ftm3_default {
60		group0 {
61			pinmux = <FTM3_CH4_PTC10>,
62				<FTM3_CH5_PTC11>,
63				<FTM3_CH6_PTC12>,
64				<FTM3_CH7_PTC13>;
65			drive-strength = "low";
66			slew-rate = "slow";
67		};
68	};
69
70	lpi2c0_default: lpi2c0_default {
71		group0 {
72			pinmux = <LPI2C0_SCL_PTA3>,
73				<LPI2C0_SDA_PTA2>;
74			drive-strength = "low";
75			slew-rate = "slow";
76		};
77	};
78
79	lpi2c1_default: lpi2c1_default {
80		group0 {
81			pinmux = <LPI2C1_SCL_PTD9>,
82				<LPI2C1_SDA_PTD8>;
83			drive-strength = "low";
84			slew-rate = "slow";
85		};
86	};
87
88	lpspi0_default: lpspi0_default {
89		group0 {
90			pinmux = <LPSPI0_SCK_PTE0>,
91				<LPSPI0_SIN_PTE1>,
92				<LPSPI0_SOUT_PTE2>;
93			drive-strength = "low";
94			slew-rate = "slow";
95		};
96	};
97
98	/* Enable PCS2 for SPI0 */
99	lpspi0_pcs2: lpspi0_pcs2 {
100		group0 {
101			pinmux = <LPSPI0_SCK_PTE0>,
102				<LPSPI0_SIN_PTE1>,
103				<LPSPI0_SOUT_PTE2>,
104				<LPSPI0_PCS2_PTE6>;
105			drive-strength = "low";
106			slew-rate = "slow";
107		};
108	};
109
110	lpspi1_default: lpspi1_default {
111		group0 {
112			pinmux = <LPSPI1_SCK_PTD0>,
113				<LPSPI1_SIN_PTD1>,
114				<LPSPI1_SOUT_PTD2>;
115			drive-strength = "low";
116			slew-rate = "slow";
117		};
118	};
119
120	/* select PCS0 for lpspi1 */
121	lpspi1_pcs0: lpspi1_pcs0 {
122		group0 {
123			pinmux = <LPSPI1_SCK_PTD0>,
124				<LPSPI1_SIN_PTD1>,
125				<LPSPI1_SOUT_PTD2>,
126				<LPSPI1_PCS0_PTD3>;
127			drive-strength = "low";
128			slew-rate = "slow";
129		};
130	};
131
132	/* select PCS0 and PCS2 for lpspi1 */
133	lpspi1_pcs0_pcs2: lpspi1_pcs0_pcs2 {
134		group0 {
135			pinmux = <LPSPI1_SCK_PTD0>,
136				<LPSPI1_SIN_PTD1>,
137				<LPSPI1_SOUT_PTD2>,
138				<LPSPI1_PCS2_PTA16>,
139				<LPSPI1_PCS0_PTD3>;
140			drive-strength = "low";
141			slew-rate = "slow";
142		};
143	};
144
145	/* select PCS2 for lpspi1 */
146	lpspi1_pcs2: lpspi1_pcs2 {
147		group0 {
148			pinmux = <LPSPI1_SCK_PTD0>,
149				<LPSPI1_SIN_PTD1>,
150				<LPSPI1_SOUT_PTD2>,
151				<LPSPI1_PCS2_PTA16>;
152			drive-strength = "low";
153			slew-rate = "slow";
154		};
155	};
156
157	lpuart0_default: lpuart0_default {
158		group0 {
159			pinmux = <LPUART0_RX_PTB0>,
160				<LPUART0_TX_PTB1>;
161			drive-strength = "low";
162			slew-rate = "slow";
163		};
164	};
165
166};
167