1/*
2 * Copyright (c) 2021 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "skeleton.dtsi"
8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "intel,lakemont";
18			d-cache-line-size = <64>;
19			reg = <0>;
20		};
21
22	};
23
24	intc: ioapic@fec00000  {
25		compatible = "intel,ioapic";
26		reg = <0xfec00000 0x1000>;
27		interrupt-controller;
28		#interrupt-cells = <3>;
29	};
30
31	intc_loapic: loapic@fee00000  {
32		compatible = "intel,loapic";
33		reg = <0xfee00000 0x1000>;
34		interrupt-controller;
35		#interrupt-cells = <3>;
36	};
37
38	/*
39	 * Platforms with Lakemont SoC can have different hardware
40	 * configurations. So RAM and peripherals need to be
41	 * defined in the board configuration's DTS.
42	 */
43	soc {
44		#address-cells = <1>;
45		#size-cells = <1>;
46		compatible = "simple-bus";
47		ranges;
48	};
49};
50