1/*
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/dt-bindings/i2c/i2c.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	compatible = "litex,vexriscv", "litex-dev";
13	model = "litex,vexriscv";
14
15
16	chosen {
17		zephyr,entropy = &prbs0;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23		cpu0: cpu@0 {
24			clock-frequency = <100000000>;
25			compatible = "litex,vexriscv-standard", "riscv";
26			device_type = "cpu";
27			reg = <0>;
28			riscv,isa = "rv32im_zicsr_zifencei";
29			status = "okay";
30		};
31	};
32	soc {
33		#address-cells = <1>;
34		#size-cells = <1>;
35		compatible = "litex,vexriscv";
36		ranges;
37		ctrl0: soc_controller@e0000000 {
38			compatible = "litex,soc-controller";
39			reg = <0xe0000000 0x4
40				0xe0000004 0x4
41				0xe0000008 0x4>;
42			reg-names = "reset",
43				"scratch",
44				"bus_errors";
45		};
46		intc0: interrupt-controller@bc0 {
47			compatible = "litex,vexriscv-intc0";
48			#address-cells = <0>;
49			#interrupt-cells = <2>;
50			interrupt-controller;
51			reg = <0xbc0 0x4 0xfc0 0x4>;
52			reg-names = "irq_mask", "irq_pending";
53			riscv,max-priority = <7>;
54		};
55		uart0: serial@e0001800 {
56			compatible = "litex,uart";
57			interrupt-parent = <&intc0>;
58			interrupts = <2 10>;
59			reg = <0xe0001800 0x4
60				0xe0001804 0x4
61				0xe0001808 0x4
62				0xe000180c 0x4
63				0xe0001810 0x4
64				0xe0001814 0x4
65				0xe0001818 0x4
66				0xe000181c 0x4>;
67			reg-names =
68				"rxtx",
69				"txfull",
70				"rxempty",
71				"ev_status",
72				"ev_pending",
73				"ev_enable",
74				"txempty",
75				"rxfull";
76			status = "disabled";
77		};
78		spi0: spi@e0002000 {
79			compatible = "litex,spi";
80			reg = <0xe0002000 0x4
81				0xe0002004 0x4
82				0xe0002008 0x4
83				0xe000200c 0x4
84				0xe0002010 0x4
85				0xe0002014 0x4>;
86			reg-names = "control",
87				"status",
88				"mosi",
89				"miso",
90				"cs",
91				"loopback";
92			status = "disabled";
93			#address-cells = <1>;
94			#size-cells = <0>;
95		};
96		spi1: spi@e000c000 {
97			compatible = "litex,spi-litespi";
98			reg = <0xe000c000 0x4>,
99				<0xe000c004 0x4>,
100				<0xe000c008 0x4>,
101				<0xe000c00c 0x4>,
102				<0xe000c010 0x4>,
103				<0xe000c800 0x4>,
104				<0x60000000 0x1000000>;
105			reg-names = "core_mmap_dummy_bits",
106				"core_master_cs",
107				"core_master_phyconfig",
108				"core_master_rxtx",
109				"core_master_status",
110				"phy_clk_divisor",
111				"flash_mmap";
112			#address-cells = <1>;
113			#size-cells = <0>;
114			spiflash0: flash@0 {
115				compatible = "jedec,spi-nor";
116				reg = <0>;
117				spi-max-frequency = <10000000>;
118			};
119		};
120		timer0: timer@e0002800 {
121			compatible = "litex,timer0";
122			interrupt-parent = <&intc0>;
123			interrupts = <1 0>;
124			reg = <0xe0002800 0x4
125				0xe0002804 0x4
126				0xe0002808 0x4
127				0xe000280c 0x4
128				0xe0002810 0x4
129				0xe0002814 0x4
130				0xe0002818 0x4
131				0xe000281c 0x4
132				0xe0002820 0x4
133				0xe0002824 0x8>;
134			reg-names =
135				"load",
136				"reload",
137				"en",
138				"update_value",
139				"value",
140				"ev_status",
141				"ev_pending",
142				"ev_enable",
143				"uptime_latch",
144				"uptime_cycles";
145			status = "disabled";
146		};
147		eth0: ethernet@e0009800 {
148			compatible = "litex,liteeth";
149			interrupt-parent = <&intc0>;
150			interrupts = <3 0>;
151			reg = <0xe0009800 0x4
152				0xe0009804 0x4
153				0xe0009808 0x4
154				0xe000980c 0x4
155				0xe0009810 0x4
156				0xe0009814 0x4
157				0xe0009818 0x4
158				0xe000981c 0x4
159				0xe0009820 0x4
160				0xe0009824 0x4
161				0xe0009828 0x4
162				0xe000982c 0x4
163				0xe0009830 0x4
164				0xe0009834 0x4
165				0xb0000000 0x2000>;
166			local-mac-address = [10 e2 d5 00 00 02];
167			reg-names = "rx_slot",
168				"rx_length",
169				"rx_errors",
170				"rx_ev_status",
171				"rx_ev_pending",
172				"rx_ev_enable",
173				"tx_start",
174				"tx_ready",
175				"tx_level",
176				"tx_slot",
177				"tx_length",
178				"tx_ev_status",
179				"tx_ev_pending",
180				"tx_ev_enable",
181				"buffers";
182			status = "disabled";
183		};
184		dna0: dna@e0003800 {
185			compatible = "litex,dna0";
186			/* DNA data is 57-bits long,
187			so it requires 8 bytes.
188			In LiteX each 32-bit register holds
189			only a single byte of meaningful data,
190			hence 8 registers. */
191			reg = <0xe0003800 0x20>;
192			reg-names = "mem";
193			status = "disabled";
194		};
195		i2c0: i2c@e0005000 {
196			compatible = "litex,i2c";
197			reg = <0xe0005000 0x4 0xe0005004 0x4>;
198			reg-names = "write", "read";
199			clock-frequency = <I2C_BITRATE_STANDARD>;
200			#address-cells = <1>;
201			#size-cells = <0>;
202			status = "disabled";
203		};
204		gpio_out: gpio@e0005800 {
205			compatible = "litex,gpio";
206			reg = <0xe0005800 0x4>;
207			reg-names = "control";
208			ngpios = <4>;
209			port-is-output;
210			status = "disabled";
211			gpio-controller;
212			#gpio-cells = <2>;
213		};
214		gpio_in: gpio@e0006000 {
215			compatible = "litex,gpio";
216			reg = <0xe0006000 0x4
217				0xe0006004 0x4
218				0xe0006008 0x4
219				0xe0006010 0x4
220				0xe0006014 0x4>;
221			interrupt-parent = <&intc0>;
222			interrupts = <4 2>;
223			reg-names = "base",
224				"irq_mode",
225				"irq_edge",
226				"irq_pend",
227				"irq_en";
228			ngpios = <4>;
229			status = "disabled";
230			gpio-controller;
231			#gpio-cells = <2>;
232		};
233		prbs0: prbs@e0006800 {
234			compatible = "litex,prbs";
235			reg = <0xe0006800 0x4>;
236			reg-names = "status";
237			status = "disabled";
238		};
239		pwm0: pwm@e0007000 {
240			compatible = "litex,pwm";
241			reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
242			reg-names = "enable", "width", "period";
243			status = "disabled";
244			#pwm-cells = <2>;
245		};
246		i2s_rx: i2s_rx@e000a800 {
247			compatible = "litex,i2s";
248			reg = <0xe000a800 0x4
249				0xe000a804 0x4
250				0xe000a808 0x4
251				0xe000a80c 0x4
252				0xe000a810 0x4
253				0xe000a814 0x4
254				0xb1000000 0x40000>;
255			interrupt-parent = <&intc0>;
256			interrupts = <6 2>;
257			#address-cells = <1>;
258			#size-cells = <0>;
259			reg-names = "ev_status",
260				"ev_pending",
261				"ev_enable",
262				"rx_ctl",
263				"rx_stat",
264				"rx_conf",
265				"fifo";
266			fifo_depth = <256>;
267			status = "disabled";
268		};
269		i2s_tx: i2s_tx@e000b000 {
270			compatible = "litex,i2s";
271			reg = <0xe000b000 0x4
272				0xe000b004 0x4
273				0xe000b008 0x4
274				0xe000b00c 0x4
275				0xe000b010 0x4
276				0xe000b014 0x4
277				0xb2000000 0x40000>;
278			interrupt-parent = <&intc0>;
279			interrupts = <7 2>;
280			#address-cells = <1>;
281			#size-cells = <0>;
282			reg-names = "ev_status",
283				"ev_pending",
284				"ev_enable",
285				"tx_ctl",
286				"tx_stat",
287				"tx_conf",
288				"fifo";
289			fifo_depth = <256>;
290			status = "disabled";
291		};
292		clock-outputs {
293			#address-cells = <1>;
294			#size-cells = <0>;
295			clk0: clock-controller@0 {
296				#clock-cells = <1>;
297				reg = <0>;
298				compatible = "litex,clkout";
299				clock-output-names = "CLK_0";
300				litex,clock-frequency = <11289600>;
301				litex,clock-phase = <0>;
302				litex,clock-duty-num = <1>;
303				litex,clock-duty-den = <2>;
304				litex,clock-margin = <1>;
305				litex,clock-margin-exp = <2>;
306				status = "disabled";
307			};
308			clk1: clock-controller@1 {
309				#clock-cells = <1>;
310				reg = <1>;
311				compatible = "litex,clkout";
312				clock-output-names = "CLK_1";
313				litex,clock-frequency = <22579200>;
314				litex,clock-phase = <0>;
315				litex,clock-duty-num = <1>;
316				litex,clock-duty-den = <2>;
317				litex,clock-margin = <1>;
318				litex,clock-margin-exp = <2>;
319				status = "disabled";
320			};
321		};
322		clock0: clock@e0004800 {
323			compatible = "litex,clk";
324			reg = <0xe0004800 0x4
325				0xe0004804 0x4
326				0xe0004808 0x4
327				0xe000480c 0x4
328				0xe0004810 0x4
329				0xe0004814 0x4
330				0xe0004818 0x4
331				0xe000481c 0x4>;
332			reg-names = "drp_reset",
333				"drp_locked",
334				"drp_read",
335				"drp_write",
336				"drp_drdy",
337				"drp_adr",
338				"drp_dat_w",
339				"drp_dat_r";
340			#clock-cells = <1>;
341			clocks = <&clk0 0>, <&clk1 1>;
342			clock-output-names = "CLK_0", "CLK_1";
343			litex,lock-timeout = <10>;
344			litex,drdy-timeout = <10>;
345			litex,divclk-divide-min = <1>;
346			litex,divclk-divide-max = <107>;
347			litex,clkfbout-mult-min = <2>;
348			litex,clkfbout-mult-max = <65>;
349			litex,vco-freq-min = <600000000>;
350			litex,vco-freq-max = <1200000000>;
351			litex,clkout-divide-min = <1>;
352			litex,clkout-divide-max = <126>;
353			litex,vco-margin = <0>;
354			status = "disabled";
355		};
356	};
357};
358