1/*
2 * Copyright (c) 2021 Argentum Systems Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv6-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13
14/ {
15	aliases {
16		watchdog0 = &wdog;
17	};
18
19	chosen {
20		zephyr,flash-controller = &nvmctrl;
21		zephyr,entropy = &trng;
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-m0+";
31			reg = <0>;
32		};
33	};
34
35	sram0: memory@20000000 {
36		compatible = "mmio-sram";
37		reg = <0x20000000 0x8000>;
38	};
39
40	id: device_id@80a00c {
41		compatible = "atmel,sam0-id";
42		reg =	<0x0080A00C 0x4>,
43			<0x0080A040 0x4>,
44			<0x0080A044 0x4>,
45			<0x0080A048 0x4>;
46	};
47
48	soc {
49		nvmctrl: nvmctrl@41004000  {
50			compatible = "atmel,sam0-nvmctrl";
51			reg = <0x41004000 0x22>;
52			interrupts = <4 0>;
53			lock-regions = <16>;
54
55			#address-cells = <1>;
56			#size-cells = <1>;
57
58			flash0: flash@0 {
59				compatible = "soc-nv-flash";
60				reg = <0 0x40000>;
61				write-block-size = <4>;
62			};
63		};
64
65		pm: pm@40000400 {
66			compatible = "atmel,saml2x-pm";
67			reg = <0x40000400 0x400>;
68			interrupts = <0 0>;
69			#clock-cells = <2>;
70		};
71
72		mclk: mclk@40000400 {
73			compatible = "atmel,saml2x-mclk";
74			reg = <0x40000400 0x400>;
75			#clock-cells = <2>;
76		};
77
78		gclk: gclk@40001800 {
79			compatible = "atmel,saml2x-gclk";
80			reg = <0x40001800 0x400>;
81			#clock-cells = <1>;
82		};
83
84		dmac: dmac@44000400 {
85			compatible = "atmel,sam0-dmac";
86			reg = <0x44000400 0x400>;
87			interrupts = <5 0>;
88			#dma-cells = <2>;
89		};
90
91		eic: eic@40002400 {
92			compatible = "atmel,sam0-eic";
93			reg = <0x40002400 0x24>;
94			interrupts = <3 0>;
95		};
96
97		wdog: watchdog@40001c00 {
98			compatible = "atmel,sam0-watchdog";
99			reg = <0x40001c00 0x0c>;
100			interrupts = <1 0>;
101		};
102
103		sercom0: sercom@42000000 {
104			compatible = "atmel,sam0-sercom";
105			reg = <0x42000000 0x40>;
106			status = "disabled";
107		};
108
109		sercom1: sercom@42000400 {
110			compatible = "atmel,sam0-sercom";
111			reg = <0x42000400 0x40>;
112			status = "disabled";
113		};
114
115		sercom2: sercom@42000800 {
116			compatible = "atmel,sam0-sercom";
117			reg = <0x42000800 0x40>;
118			status = "disabled";
119		};
120
121		sercom3: sercom@42000c00 {
122			compatible = "atmel,sam0-sercom";
123			reg = <0x42000C00 0x40>;
124			status = "disabled";
125		};
126
127		sercom4: sercom@42001000 {
128			compatible = "atmel,sam0-sercom";
129			reg = <0x42001000 0x40>;
130			status = "disabled";
131		};
132
133		sercom5: sercom@43000400 {
134			compatible = "atmel,sam0-sercom";
135			reg = <0x43000400 0x40>;
136			status = "disabled";
137		};
138
139		tc4: tc@43000800 {
140			compatible = "atmel,sam0-tc32";
141			reg = <0x43000800 0x34>;
142		};
143
144		pinctrl: pinctrl@40002800 {
145			compatible = "atmel,sam0-pinctrl";
146			#address-cells = <1>;
147			#size-cells = <1>;
148			ranges = <0x40002800 0x40002800 0x100>;
149
150			porta: gpio@40002800 {
151				compatible = "atmel,sam0-gpio";
152				reg = <0x40002800 0x80>;
153				gpio-controller;
154				#gpio-cells = <2>;
155				#atmel,pin-cells = <2>;
156
157			};
158
159			portb: gpio@40002880 {
160				compatible = "atmel,sam0-gpio";
161				reg = <0x40002880 0x80>;
162				gpio-controller;
163				#gpio-cells = <2>;
164				#atmel,pin-cells = <2>;
165			};
166		};
167
168		rtc: rtc@40002000 {
169			compatible = "atmel,sam0-rtc";
170			reg = <0x40002000 0x1c>;
171			interrupts = <2 0>;
172			clock-generator = <0>;
173			status = "disabled";
174		};
175
176		adc: adc@43000c00 {
177			compatible = "atmel,sam0-adc";
178			reg = <0x43000c00 0x30>;
179
180			/*
181			 * 16 MHz max, so clock it with the
182			 * 48 MHz DFLL / 2 / 2 = 12 MHz
183			 */
184			gclk = <3>;
185			prescaler = <2>;
186			#io-channel-cells = <1>;
187		};
188
189		dac: dac@42003000 {
190			compatible = "atmel,sam0-dac";
191			status = "disabled";
192			reg = <0x42003000 0x1a>;
193			#io-channel-cells = <0>;
194		};
195
196		trng: random@42003800 {
197			compatible = "atmel,sam-trng";
198			reg = <0x42003800 0x24>;
199			interrupts = <27 0>;
200		};
201	};
202};
203
204&nvic {
205	arm,num-irq-priority-bits = <2>;
206};
207