1 /* 2 * Copyright (c) 2023 bytes at work AG 3 * Copyright (c) 2020 Teslabs Engineering S.L. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_ 9 #define ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_ 10 11 /** 12 * @name General parameters. 13 * @{ 14 */ 15 16 /** ID1 */ 17 #define OTM8009A_ID1 0x40U 18 /** Read ID1 command */ 19 #define OTM8009A_CMD_ID1 0xDA 20 21 /** Reset pulse time (ms), ref. Table 6.3.4.1 */ 22 #define OTM8009A_RESET_TIME 10U 23 /** Wake up time after reset pulse, ref. Table 6.3.4.1 */ 24 #define OTM8009A_WAKE_TIME 20U 25 /** Time to wait after exiting sleep mode (ms), ref. 5.2.11. */ 26 #define OTM8009A_EXIT_SLEEP_MODE_WAIT_TIME 5U 27 28 /** @} */ 29 30 /** 31 * @name Display timings (ref. table 6.4.2.1) 32 * @{ 33 */ 34 35 /** Horizontal low pulse width */ 36 #define OTM8009A_HSYNC 2U 37 /** Horizontal front porch. */ 38 #define OTM8009A_HFP 34U 39 /** Horizontal back porch. */ 40 #define OTM8009A_HBP 34U 41 /** Vertical low pulse width. */ 42 #define OTM8009A_VSYNC 1U 43 /** Vertical front porch. */ 44 #define OTM8009A_VFP 16U 45 /** Vertical back porch. */ 46 #define OTM8009A_VBP 15U 47 48 /** @} */ 49 50 /** 51 * @name Register fields. 52 * @{ 53 */ 54 55 /** 56 * @name MIPI DCS Write Control Display fields. 57 * @{ 58 */ 59 60 /** Write Control Display: brightness control. */ 61 #define OTM8009A_WRCTRLD_BCTRL BIT(5) 62 /** Write Control Display: display dimming. */ 63 #define OTM8009A_WRCTRLD_DD BIT(3) 64 /** Write Control Display: backlight. */ 65 #define OTM8009A_WRCTRLD_BL BIT(2) 66 67 /** Adaptibe Brightness Control: off. */ 68 #define OTM8009A_WRCABC_OFF 0x00U 69 /** Adaptibe Brightness Control: user interface. */ 70 #define OTM8009A_WRCABC_UI 0x01U 71 /** Adaptibe Brightness Control: still picture. */ 72 #define OTM8009A_WRCABC_ST 0x02U 73 /** Adaptibe Brightness Control: moving image. */ 74 #define OTM8009A_WRCABC_MV 0x03U 75 76 /** @} */ 77 78 /** 79 * @name MIPI MCS (Manufacturer Command Set). 80 * @{ 81 */ 82 83 /** Address Shift Function */ 84 #define OTM8009A_MCS_ADRSFT 0x0000U 85 /** Panel Type Setting */ 86 #define OTM8009A_MCS_PANSET 0xB3A6U 87 /* Source Driver Timing Setting */ 88 #define OTM8009A_MCS_SD_CTRL 0xC0A2U 89 /** Panel Driving Mode */ 90 #define OTM8009A_MCS_P_DRV_M 0xC0B4U 91 /** Oscillator Adjustment for Idle/Normal mode */ 92 #define OTM8009A_MCS_OSC_ADJ 0xC181U 93 /** RGB Video Mode Setting */ 94 #define OTM8009A_MCS_RGB_VID_SET 0xC1A1U 95 /** Source Driver Precharge Control */ 96 #define OTM8009A_MCS_SD_PCH_CTRL 0xC480U 97 /** Command not documented */ 98 #define OTM8009A_MCS_NO_DOC1 0xC48AU 99 /** Power Control Setting 1 */ 100 #define OTM8009A_MCS_PWR_CTRL1 0xC580U 101 /** Power Control Setting 2 for Normal Mode */ 102 #define OTM8009A_MCS_PWR_CTRL2 0xC590U 103 /** Power Control Setting 4 for DC Voltage */ 104 #define OTM8009A_MCS_PWR_CTRL4 0xC5B0U 105 /** PWM Parameter 1 */ 106 #define OTM8009A_MCS_PWM_PARA1 0xC680U 107 /** PWM Parameter 2 */ 108 #define OTM8009A_MCS_PWM_PARA2 0xC6B0U 109 /** PWM Parameter 3 */ 110 #define OTM8009A_MCS_PWM_PARA3 0xC6B1U 111 /** PWM Parameter 4 */ 112 #define OTM8009A_MCS_PWM_PARA4 0xC6B3U 113 /** PWM Parameter 5 */ 114 #define OTM8009A_MCS_PWM_PARA5 0xC6B4U 115 /** PWM Parameter 6 */ 116 #define OTM8009A_MCS_PWM_PARA6 0xC6B5U 117 /** Panel Control Setting 1 */ 118 #define OTM8009A_MCS_PANCTRLSET1 0xCB80U 119 /** Panel Control Setting 2 */ 120 #define OTM8009A_MCS_PANCTRLSET2 0xCB90U 121 /** Panel Control Setting 3 */ 122 #define OTM8009A_MCS_PANCTRLSET3 0xCBA0U 123 /** Panel Control Setting 4 */ 124 #define OTM8009A_MCS_PANCTRLSET4 0xCBB0U 125 /** Panel Control Setting 5 */ 126 #define OTM8009A_MCS_PANCTRLSET5 0xCBC0U 127 /** Panel Control Setting 6 */ 128 #define OTM8009A_MCS_PANCTRLSET6 0xCBD0U 129 /** Panel Control Setting 7 */ 130 #define OTM8009A_MCS_PANCTRLSET7 0xCBE0U 131 /** Panel Control Setting 8 */ 132 #define OTM8009A_MCS_PANCTRLSET8 0xCBF0U 133 /** Panel U2D Setting 1 */ 134 #define OTM8009A_MCS_PANU2D1 0xCC80U 135 /** Panel U2D Setting 2 */ 136 #define OTM8009A_MCS_PANU2D2 0xCC90U 137 /** Panel U2D Setting 3 */ 138 #define OTM8009A_MCS_PANU2D3 0xCCA0U 139 /** Panel D2U Setting 1 */ 140 #define OTM8009A_MCS_PAND2U1 0xCCB0U 141 /** Panel D2U Setting 2 */ 142 #define OTM8009A_MCS_PAND2U2 0xCCC0U 143 /** Panel D2U Setting 3 */ 144 #define OTM8009A_MCS_PAND2U3 0xCCD0U 145 /** GOA VST Setting */ 146 #define OTM8009A_MCS_GOAVST 0xCE80U 147 /** GOA CLKA1 Setting */ 148 #define OTM8009A_MCS_GOACLKA1 0xCEA0U 149 /** GOA CLKA2 Setting */ 150 #define OTM8009A_MCS_GOACLKA2 0xCEA7U 151 /** GOA CLKA3 Setting */ 152 #define OTM8009A_MCS_GOACLKA3 0xCEB0U 153 /** GOA CLKA4 Setting */ 154 #define OTM8009A_MCS_GOACLKA4 0xCEB7U 155 /** GOA ECLK Setting */ 156 #define OTM8009A_MCS_GOAECLK 0xCFC0U 157 /** GOA Other Options 1 */ 158 #define OTM8009A_MCS_GOAPT1 0xCFC6U 159 /** GOA Signal Toggle Option Setting */ 160 #define OTM8009A_MCS_GOATGOPT 0xCFC7U 161 /** Command not documented */ 162 #define OTM8009A_MCS_NO_DOC2 0xCFD0U 163 /** GVDD/NGVDD */ 164 #define OTM8009A_MCS_GVDDSET 0xD800U 165 /** VCOM Voltage Setting */ 166 #define OTM8009A_MCS_VCOMDC 0xD900U 167 /** Gamma Correction 2.2+ Setting */ 168 #define OTM8009A_MCS_GMCT2_2P 0xE100U 169 /** Gamma Correction 2.2- Setting */ 170 #define OTM8009A_MCS_GMCT2_2N 0xE200U 171 /** Command not documented */ 172 #define OTM8009A_MCS_NO_DOC3 0xF5B6U 173 /** Enable Access Command2 "CMD2" */ 174 #define OTM8009A_MCS_CMD2_ENA1 0xFF00U 175 /** Enable Access Orise Command2 */ 176 #define OTM8009A_MCS_CMD2_ENA2 0xFF80U 177 178 /** @} */ 179 180 #endif /* ZEPHYR_DRIVERS_DISPLAY_DISPLAY_OTM8009A_H_ */ 181
