1/*
2 * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH
3 * Copyright (c) 2017 Linaro Limited
4 * Copyright (c) 2023 Nordic Semiconductor ASA
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9#include "reel_board_nrf52840_2-pinctrl.dtsi"
10
11/ {
12	model = "reel board v2";
13	compatible = "phytec,reel_board_v2";
14
15	chosen {
16		zephyr,console = &uart0;
17		zephyr,shell-uart = &uart0;
18		zephyr,uart-mcumgr = &uart0;
19		zephyr,bt-mon-uart = &uart0;
20		zephyr,bt-c2h-uart = &uart0;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23		zephyr,code-partition = &slot0_partition;
24		zephyr,display = &ssd16xx;
25	};
26
27	aliases {
28		watchdog0 = &wdt0;
29	};
30
31	mipi_dbi {
32		compatible = "zephyr,mipi-dbi-spi";
33		spi-dev = <&spi1>;
34		reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
35		dc-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
36		#address-cells = <1>;
37		#size-cells = <0>;
38
39		ssd16xx: ssd16xxfb@0 {
40			compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a";
41			mipi-max-frequency = <4000000>;
42			reg = <0>;
43			width = <250>;
44			height = <122>;
45			busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
46
47			full {
48				gdv = [15];
49				sdv = [41 a8 32];
50				vcom = <0x26>;
51				border-waveform = <0x03>;
52				dummy-line = <0x30>;
53				gate-line-width = <0x0a>;
54				lut = [
55					/*
56					 * Waveform Composition
57					 *
58					 * There are 7 Voltage Source (VS) Level groups
59					 * n = {0,1,2...6}, each group contains
60					 * 4 phases x = {A,B,C,D}.
61					 * 2 bits represent the voltage in a phase:
62					 * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2
63					 *
64					 * For example 0x80 represents sequence VSL-VSS-VSS-VSS,
65					 */
66					80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */
67					10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */
68					80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */
69					10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */
70					00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */
71					/*
72					 * TPnx determines the length of each phase,
73					 * and RPn repeat count of a sequence.
74					 * TPnA, TPnB, TPnC, TPnD, RPn
75					 *
76					 * For example TP0A=3, TP0B=3, and RP0=2:
77					 * VS sequence                    : VSL-VSS-VSS-VSS
78					 * number of Gate Pulses (length) :  3   3   0   0
79					 * repeat count                   :        2
80					 */
81					03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */
82					09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */
83					03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */
84					00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */
85					00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */
86					00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */
87					00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */
88				];
89			};
90
91			partial {
92				gdv = [15];
93				sdv = [41 a8 32];
94				vcom = <0x26>;
95				border-waveform = <0x01>;
96				dummy-line = <0x30>;
97				gate-line-width = <0x0a>;
98				lut = [
99					00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */
100					80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */
101					40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */
102					80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */
103					00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */
104					0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */
105					00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */
106					00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */
107					00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */
108					00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */
109					00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */
110					00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */
111				];
112			};
113		};
114	};
115};
116
117&spi1 {
118	compatible = "nordic,nrf-spi";
119	status = "okay";
120	cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
121
122	pinctrl-0 = <&spi1_default>;
123	pinctrl-1 = <&spi1_sleep>;
124	pinctrl-names = "default", "sleep";
125};
126