1/*
2 * Copyright 2021-2022,2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_rt11xx_cm7.dtsi>
10#include "mimxrt1170_evk.dtsi"
11
12/ {
13	model = "NXP MIMXRT1170-EVK board";
14	compatible = "nxp,mimxrt1176";
15
16	aliases {
17		mipi-dsi = &mipi_dsi;
18		watchdog0 = &wdog1;
19	};
20
21	chosen {
22		zephyr,sram = &sdram0;
23		zephyr,dtcm = &dtcm;
24		zephyr,itcm = &itcm;
25		zephyr,console = &lpuart1;
26		zephyr,shell-uart = &lpuart1;
27		zephyr,canbus = &flexcan3;
28		zephyr,flash-controller = &is25wp128;
29		zephyr,flash = &is25wp128;
30		zephyr,code-partition = &slot0_partition;
31		zephyr,cpu1-region = &ocram;
32		zephyr,ipc = &mailbox_a;
33	};
34
35	sdram0: memory@80000000 {
36		/* Winbond W9825G6KH-5I */
37		device_type = "memory";
38		reg = <0x80000000 DT_SIZE_M(64)>;
39	};
40
41	/*
42	 * This node describes the GPIO pins of the MIPI FPC interface,
43	 * J48 on the EVK. This interface is standard to several
44	 * NXP EVKs, and is used with several MIPI displays
45	 * (available as zephyr shields)
46	 */
47	nxp_mipi_connector: mipi-connector {
48		compatible = "gpio-nexus";
49		#gpio-cells = <2>;
50		gpio-map-mask = <0xffffffff 0xffffffc0>;
51		gpio-map-pass-thru = <0 0x3f>;
52		gpio-map =	<0  0 &gpio9 29 0>,	/* Pin 1, LEDK */
53				<21 0 &gpio9 1  0>,	/* Pin 21, RESET */
54				<22 0 &gpio9 4  0>,	/* Pin 22, LPTE */
55				<26 0 &gpio6 4  0>,	/* Pin 26, CTP_I2C SDA */
56				<27 0 &gpio6 5  0>,	/* Pin 27, CTP_I2C SCL */
57				<28 0 &gpio9 0  0>,	/* Pin 28, CTP_RST */
58				<29 0 &gpio2 31 0>,	/* Pin 29, CTP_INT */
59				<32 0 &gpio11 16 0>,	/* Pin 32, PWR_EN */
60				<34 0 &gpio9 29 0>;	/* Pin 34, BL_PWM */
61	};
62
63	/*
64	 * This node describes the GPIO pins mapping of the 44-pin camera
65	 * connector, J2 on the EVK. This camera interface is supported
66	 * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and
67	 * is used with an ov5640 camera module available as a Zephyr shield
68	 */
69	nxp_cam_connector: cam-connector {
70		compatible = "nxp,cam-44pins-connector";
71		#gpio-cells = <2>;
72		gpio-map-mask = <0xffffffff 0xffffffc0>;
73		gpio-map-pass-thru = <0 0x3f>;
74		gpio-map =	<9 0 &gpio11 15 0>,	/* Pin 9, RESETB */
75				<17 0 &gpio9 25  0>;	/* Pin 17, PWDN */
76	};
77};
78
79zephyr_lcdif: &lcdif {};
80
81zephyr_mipi_dsi: &mipi_dsi {
82	dphy-ref-frequency = <24000000>;
83};
84
85&lpuart1 {
86	status = "okay";
87	current-speed = <115200>;
88};
89
90&flexcan3 {
91	status = "okay";
92	can-transceiver {
93		max-bitrate = <5000000>;
94	};
95};
96
97&lpspi1 {
98	dmas = <&edma0 0 36>, <&edma0 1 37>;
99	dma-names = "rx", "tx";
100	status = "okay";
101};
102
103nxp_mipi_i2c: &lpi2c5 {
104	pinctrl-0 = <&pinmux_lpi2c5>;
105	pinctrl-names = "default";
106	#address-cells = <1>;
107	#size-cells = <0>;
108};
109
110&lpadc0 {
111	status = "okay";
112};
113
114&usdhc1 {
115	status = "okay";
116	detect-dat3;
117	pwr-gpios = <&gpio10 2 GPIO_ACTIVE_LOW>;
118	sdmmc {
119		compatible = "zephyr,sdmmc-disk";
120		status = "okay";
121	};
122};
123
124&edma0 {
125	status = "okay";
126};
127
128/* GPT and Systick are enabled. If power management is enabled, the GPT
129 * timer will be used instead of systick, as allows the core clock to
130 * be gated.
131 */
132&gpt_hw_timer {
133	status = "okay";
134};
135
136&systick {
137	status = "okay";
138};
139
140&wdog1 {
141	status = "okay";
142};
143
144
145&sai1 {
146	status = "okay";
147};
148
149zephyr_udc0: &usb1 {
150	status = "okay";
151	phy_handle = <&usbphy1>;
152};
153
154&usbphy1 {
155	status = "okay";
156	tx-d-cal = <7>;
157	tx-cal-45-dp-ohms = <6>;
158	tx-cal-45-dm-ohms = <6>;
159};
160
161&mailbox_a {
162	status = "okay";
163};
164
165&pit1 {
166	status = "okay";
167};
168
169&pit2 {
170	status = "okay";
171};
172
173nxp_cam_i2c: &lpi2c6 {};
174
175nxp_mipi_csi: &mipi_csi2rx {};
176
177nxp_csi: &csi {};
178