1/*
2 * Copyright 2021,2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_rt11xx_cm7.dtsi>
10#include "mimxrt1160_evk.dtsi"
11
12/ {
13	model = "NXP MIMXRT1160-EVK board";
14	compatible = "nxp,mimxrt1166";
15
16	chosen {
17		zephyr,sram = &sdram0;
18		zephyr,dtcm = &dtcm;
19		zephyr,itcm = &itcm;
20		zephyr,console = &lpuart1;
21		zephyr,shell-uart = &lpuart1;
22		zephyr,canbus = &flexcan3;
23		zephyr,flash-controller = &is25wp128;
24		zephyr,flash = &is25wp128;
25		zephyr,code-partition = &slot0_partition;
26		zephyr,cpu1-region = &ocram;
27		zephyr,ipc = &mailbox_a;
28	};
29
30	sdram0: memory@80000000 {
31		/* Winbond W9825G6KH-5I */
32		device_type = "memory";
33		reg = <0x80000000 DT_SIZE_M(64)>;
34	};
35
36	aliases {
37		watchdog0 = &wdog1;
38	};
39
40	/*
41	 * This node describes the GPIO pins mapping of the 44-pin camera
42	 * connector, J2 on the EVK. This camera interface is supported
43	 * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and
44	 * is used with an ov5640 camera module available as a Zephyr shield
45	 */
46	nxp_cam_connector: cam-connector {
47		compatible = "nxp,cam-44pins-connector";
48		#gpio-cells = <2>;
49		gpio-map-mask = <0xffffffff 0xffffffc0>;
50		gpio-map-pass-thru = <0 0x3f>;
51		gpio-map =	<9 0 &gpio11 15 0>,	/* Pin 9, RESETB */
52				<17 0 &gpio9 25  0>;	/* Pin 17, PWDN */
53	};
54
55	/*
56	 * This node describes the GPIO pins of the MIPI FPC interface,
57	 * J48 on the EVK. This interface is standard to several
58	 * NXP EVKs, and is used with several MIPI displays
59	 * (available as zephyr shields)
60	 */
61	 nxp_mipi_connector: mipi-connector {
62		compatible = "gpio-nexus";
63		#gpio-cells = <2>;
64		gpio-map-mask = <0xffffffff 0xffffffc0>;
65		gpio-map-pass-thru = <0 0x3f>;
66		gpio-map =	<0  0 &gpio9 29 0>,	/* Pin 1, LEDK */
67				<21 0 &gpio9 1  0>,	/* Pin 21, RESET */
68				<22 0 &gpio9 4  0>,	/* Pin 22, LPTE */
69				<26 0 &gpio6 4  0>,	/* Pin 26, CTP_I2C SDA */
70				<27 0 &gpio6 5  0>,	/* Pin 27, CTP_I2C SCL */
71				<28 0 &gpio9 0  0>,	/* Pin 28, CTP_RST */
72				<29 0 &gpio2 31 0>,	/* Pin 29, CTP_INT */
73				<32 0 &gpio11 16 0>,	/* Pin 32, PWR_EN */
74				<34 0 &gpio9 29 0>;	/* Pin 34, BL_PWM */
75	};
76};
77
78&lpuart1 {
79	status = "okay";
80	current-speed = <115200>;
81};
82
83&flexcan3 {
84	status = "okay";
85	can-transceiver {
86		max-bitrate = <5000000>;
87	};
88};
89
90&lpi2c1 {
91	status = "okay";
92};
93
94&lpspi1 {
95	status = "okay";
96};
97
98/* GPT and Systick are enabled. If power management is enabled, the GPT
99 * timer will be used instead of systick, as allows the core clock to
100 * be gated.
101 */
102&gpt_hw_timer {
103	status = "okay";
104};
105
106&systick {
107	status = "okay";
108};
109
110&lpadc0 {
111	status = "okay";
112};
113
114&wdog1 {
115	status = "okay";
116};
117
118&edma0 {
119	status = "okay";
120};
121
122zephyr_udc0: &usb1 {
123	status = "okay";
124};
125
126&mailbox_a {
127	status = "okay";
128};
129
130&pit1 {
131	status = "okay";
132};
133
134&pit2 {
135	status = "okay";
136};
137
138nxp_cam_i2c: &lpi2c6 {};
139
140nxp_mipi_csi: &mipi_csi2rx {};
141
142nxp_csi: &csi {};
143
144zephyr_lcdif: &lcdif {};
145
146zephyr_mipi_dsi: &mipi_dsi {
147	dphy-ref-frequency = <24000000>;
148};
149
150nxp_mipi_i2c: &lpi2c5 {
151	pinctrl-0 = <&pinmux_lpi2c5>;
152	pinctrl-names = "default";
153	#address-cells = <1>;
154	#size-cells = <0>;
155};
156