1/*
2 * Copyright (c) 2019, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_lpc55S6x_ns.dtsi>
10#include "lpcxpresso55s69.dtsi"
11
12/ {
13	model = "NXP LPCXpresso55S69 board";
14	compatible = "nxp,lpc55xxx", "nxp,lpc";
15
16	cpus {
17		/delete-node/ cpu@0;
18	};
19
20	chosen {
21		zephyr,sram = &sram3;
22		zephyr,flash = &flash0;
23		zephyr,code-partition = &slot0_ns_partition;
24		zephyr,entropy = &rng;
25	};
26};
27
28/*
29 * Default for this board is to allocate SRAM3-4 to cpu1 but the
30 * application can have an application specific device tree to
31 * allocate the SRAM0-4 differently.
32 *
33 * For example, SRAM0-3 could be allocated to cpu0 with only SRAM4
34 * for cpu1. This would require the zephyr,sram chosen value for cpu1
35 * to be changed to sram4 and the value of sram0 to have a DT_SIZE_K
36 * of 256.
37 *
38 */
39&sram3 {
40	compatible = "mmio-sram";
41	reg = <0x20030000 DT_SIZE_K(80)>;
42};
43
44
45&gpio0 {
46	status = "okay";
47};
48
49&gpio1 {
50	status = "okay";
51};
52
53&blue_led {
54	status = "okay";
55};
56
57&mailbox0 {
58	status = "okay";
59};
60
61&mma8652fc {
62	status = "disabled";
63};
64