1/* 2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <mem.h> 7#include <zephyr/dt-bindings/adc/adc.h> 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h> 11#include <zephyr/dt-bindings/clock/esp32c3_clock.h> 12#include <dt-bindings/pinctrl/esp32-pinctrl.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 aliases { 19 die-temp0 = &coretemp; 20 }; 21 22 chosen { 23 zephyr,canbus = &twai; 24 zephyr,entropy = &trng0; 25 zephyr,flash-controller = &flash; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "espressif,riscv", "riscv"; 35 riscv,isa = "rv32imc_zicsr"; 36 reg = <0>; 37 cpu-power-states = <&light_sleep &deep_sleep>; 38 }; 39 40 power-states { 41 light_sleep: light_sleep { 42 compatible = "zephyr,power-state"; 43 power-state-name = "standby"; 44 min-residency-us = <200>; 45 exit-latency-us = <60>; 46 }; 47 48 deep_sleep: deep_sleep { 49 compatible = "zephyr,power-state"; 50 power-state-name = "soft-off"; 51 min-residency-us = <660>; 52 exit-latency-us = <105>; 53 }; 54 }; 55 }; 56 57 pinctrl: pin-controller { 58 compatible = "espressif,esp32-pinctrl"; 59 status = "okay"; 60 }; 61 62 wifi: wifi { 63 compatible = "espressif,esp32-wifi"; 64 status = "disabled"; 65 }; 66 67 soc { 68 #address-cells = <1>; 69 #size-cells = <1>; 70 compatible = "simple-bus"; 71 ranges; 72 73 sram0: memory@3fc7c000 { 74 compatible = "mmio-sram"; 75 reg = <0x3fc7c000 0x50000>; 76 }; 77 78 intc: interrupt-controller@600c2000 { 79 compatible = "espressif,esp32-intc"; 80 #address-cells = <0>; 81 #interrupt-cells = <1>; 82 interrupt-controller; 83 reg = <0x600c2000 0x198>; 84 status = "okay"; 85 }; 86 87 systimer0: systimer@60023000 { 88 compatible = "espressif,esp32-systimer"; 89 reg = <0x60023000 0x80>; 90 interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE>; 91 interrupt-parent = <&intc>; 92 status = "okay"; 93 }; 94 95 rtc: rtc@60008000 { 96 compatible = "espressif,esp32-rtc"; 97 reg = <0x60008000 0x1000>; 98 xtal-freq = <ESP32_CLK_XTAL_40M>; 99 #clock-cells = <1>; 100 status = "okay"; 101 102 rtc_timer: rtc_timer { 103 compatible = "espressif,esp32-rtc-timer"; 104 slow-clk-freq = <ESP32_RTC_SLOW_CLK_FREQ_90K>; 105 interrupts = <RTC_CORE_INTR_SOURCE>; 106 interrupt-parent = <&intc>; 107 status = "okay"; 108 }; 109 }; 110 111 flash: flash-controller@60002000 { 112 compatible = "espressif,esp32-flash-controller"; 113 reg = <0x60002000 0x1000>; 114 115 #address-cells = <1>; 116 #size-cells = <1>; 117 118 flash0: flash@0 { 119 compatible = "soc-nv-flash"; 120 reg = <0 0x400000>; 121 erase-block-size = <4096>; 122 write-block-size = <4>; 123 }; 124 }; 125 126 gpio0: gpio@60004000 { 127 compatible = "espressif,esp32-gpio"; 128 gpio-controller; 129 #gpio-cells = <2>; 130 reg = <0x60004000 0x800>; 131 interrupts = <GPIO_INTR_SOURCE>; 132 interrupt-parent = <&intc>; 133 /* Maximum available pins (per port) 134 * Actual occupied pins are specified 135 * on part number dtsi level, using 136 * the `gpio-reserved-ranges` property. 137 */ 138 ngpios = <26>; /* 0..25 */ 139 }; 140 141 i2c0: i2c@60013000 { 142 compatible = "espressif,esp32-i2c"; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 reg = <0x60013000 0x1000>; 146 interrupts = <I2C_EXT0_INTR_SOURCE>; 147 interrupt-parent = <&intc>; 148 clocks = <&rtc ESP32_I2C0_MODULE>; 149 status = "disabled"; 150 }; 151 152 uart0: uart@60000000 { 153 compatible = "espressif,esp32-uart"; 154 reg = <0x60000000 0x400>; 155 status = "disabled"; 156 interrupts = <UART0_INTR_SOURCE>; 157 interrupt-parent = <&intc>; 158 clocks = <&rtc ESP32_UART0_MODULE>; 159 }; 160 161 uart1: uart@60010000 { 162 compatible = "espressif,esp32-uart"; 163 reg = <0x60010000 0x400>; 164 status = "disabled"; 165 interrupts = <UART1_INTR_SOURCE>; 166 interrupt-parent = <&intc>; 167 clocks = <&rtc ESP32_UART1_MODULE>; 168 current-speed = <115200>; 169 }; 170 171 ledc0: ledc@60019000 { 172 compatible = "espressif,esp32-ledc"; 173 pwm-controller; 174 #pwm-cells = <3>; 175 reg = <0x60019000 0x1000>; 176 clocks = <&rtc ESP32_LEDC_MODULE>; 177 status = "disabled"; 178 }; 179 180 usb_serial: uart@60043000 { 181 compatible = "espressif,esp32-usb-serial"; 182 reg = <0x60043000 0x400>; 183 status = "disabled"; 184 interrupts = <USB_INTR_SOURCE>; 185 interrupt-parent = <&intc>; 186 clocks = <&rtc ESP32_USB_MODULE>; 187 }; 188 189 timer0: counter@6001f000 { 190 compatible = "espressif,esp32-timer"; 191 reg = <0x6001F000 DT_SIZE_K(4)>; 192 group = <0>; 193 index = <0>; 194 interrupts = <TG0_T0_LEVEL_INTR_SOURCE>; 195 interrupt-parent = <&intc>; 196 status = "disabled"; 197 }; 198 199 timer1: counter@60020000 { 200 compatible = "espressif,esp32-timer"; 201 reg = <0x60020000 DT_SIZE_K(4)>; 202 group = <1>; 203 index = <0>; 204 interrupts = <TG1_T0_LEVEL_INTR_SOURCE>; 205 interrupt-parent = <&intc>; 206 status = "disabled"; 207 }; 208 209 trng0: trng@3ff700b0 { 210 compatible = "espressif,esp32-trng"; 211 reg = <0x3FF700B0 0x4>; 212 status = "disabled"; 213 }; 214 215 twai: can@6002b000 { 216 compatible = "espressif,esp32-twai"; 217 reg = <0x6002b000 DT_SIZE_K(4)>; 218 interrupts = <TWAI_INTR_SOURCE>; 219 interrupt-parent = <&intc>; 220 clocks = <&rtc ESP32_TWAI_MODULE>; 221 sample-point = <875>; 222 status = "disabled"; 223 }; 224 225 spi2: spi@60024000 { 226 compatible = "espressif,esp32-spi"; 227 reg = <0x60024000 DT_SIZE_K(4)>; 228 interrupts = <SPI2_INTR_SOURCE>; 229 interrupt-parent = <&intc>; 230 clocks = <&rtc ESP32_SPI2_MODULE>; 231 dma-clk = <ESP32_GDMA_MODULE>; 232 dma-host = <0>; 233 status = "disabled"; 234 }; 235 236 wdt0: watchdog@6001f048 { 237 compatible = "espressif,esp32-watchdog"; 238 reg = <0x6001f048 0x20>; 239 interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>; 240 interrupt-parent = <&intc>; 241 clocks = <&rtc ESP32_TIMG0_MODULE>; 242 status = "disabled"; 243 }; 244 245 wdt1: watchdog@60020048 { 246 compatible = "espressif,esp32-watchdog"; 247 reg = <0x60020048 0x20>; 248 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>; 249 interrupt-parent = <&intc>; 250 clocks = <&rtc ESP32_TIMG1_MODULE>; 251 status = "disabled"; 252 }; 253 254 coretemp: coretemp@60040058 { 255 compatible = "espressif,esp32-temp"; 256 friendly-name = "coretemp"; 257 reg = <0x60040058 0x4>; 258 status = "disabled"; 259 }; 260 261 adc0: adc@60040000 { 262 compatible = "espressif,esp32-adc"; 263 reg = <0x60040000 4>; 264 unit = <1>; 265 channel-count = <5>; 266 #io-channel-cells = <1>; 267 status = "disabled"; 268 }; 269 270 adc1: adc@60040004 { 271 compatible = "espressif,esp32-adc"; 272 reg = <0x60040004 4>; 273 unit = <2>; 274 channel-count = <2>; 275 #io-channel-cells = <1>; 276 status = "disabled"; 277 }; 278 279 dma: dma@6003f000 { 280 compatible = "espressif,esp32-gdma"; 281 reg = <0x6003f000 DT_SIZE_K(4)>; 282 #dma-cells = <1>; 283 interrupts = <DMA_CH0_INTR_SOURCE DMA_CH1_INTR_SOURCE DMA_CH2_INTR_SOURCE>; 284 interrupt-parent = <&intc>; 285 clocks = <&rtc ESP32_GDMA_MODULE>; 286 dma-channels = <6>; 287 dma-buf-addr-alignment = <4>; 288 status = "disabled"; 289 }; 290 291 }; 292 293}; 294
