1 /* 2 * Copyright (c) 2021 IP-Logix Inc. 3 * Arvin Farahmand <arvinf@ip-logix.com> 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __DSA_KSZ8863_H__ 8 #define __DSA_KSZ8863_H__ 9 10 /* SPI commands */ 11 #define KSZ8863_SPI_CMD_WR (BIT(6)) 12 #define KSZ8863_SPI_CMD_RD (BIT(6) | BIT(5)) 13 14 /* PHY registers */ 15 #define KSZ8863_BMCR 0x00 16 #define KSZ8863_BMSR 0x01 17 #define KSZ8863_PHYID1 0x02 18 #define KSZ8863_PHYID2 0x03 19 #define KSZ8863_ANAR 0x04 20 #define KSZ8863_ANLPAR 0x05 21 #define KSZ8863_LINKMD 0x1D 22 #define KSZ8863_PHYSCS 0x1F 23 24 /* SWITCH registers */ 25 #define KSZ8863_CHIP_ID0 0x00 26 #define KSZ8863_CHIP_ID1 0x01 27 #define KSZ8863_GLOBAL_CTRL0 0x02 28 #define KSZ8863_GLOBAL_CTRL1 0x03 29 #define KSZ8863_GLOBAL_CTRL2 0x04 30 #define KSZ8863_GLOBAL_CTRL3 0x05 31 #define KSZ8863_GLOBAL_CTRL4 0x06 32 #define KSZ8863_GLOBAL_CTRL5 0x07 33 #define KSZ8863_GLOBAL_CTRL9 0x0B 34 #define KSZ8863_GLOBAL_CTRL10 0x0C 35 #define KSZ8863_GLOBAL_CTRL11 0x0D 36 #define KSZ8863_GLOBAL_CTRL12 0x0E 37 #define KSZ8863_GLOBAL_CTRL13 0x0F 38 #define KSZ8863_PORT1_CTRL0 0x10 39 #define KSZ8863_PORT1_CTRL1 0x11 40 #define KSZ8863_PORT1_CTRL2 0x12 41 #define KSZ8863_PORT1_CTRL3 0x13 42 #define KSZ8863_PORT1_CTRL4 0x14 43 #define KSZ8863_PORT1_CTRL5 0x15 44 #define KSZ8863_PORT1_Q0_IG_LIMIT 0x16 45 #define KSZ8863_PORT1_Q1_IG_LIMIT 0x17 46 #define KSZ8863_PORT1_Q2_IG_LIMIT 0x18 47 #define KSZ8863_PORT1_Q3_IG_LIMIT 0x19 48 #define KSZ8863_PORT1_PHY_CTRL 0x1A 49 #define KSZ8863_PORT1_LINKMD 0x1B 50 #define KSZ8863_PORT1_CTRL12 0x1C 51 #define KSZ8863_PORT1_CTRL13 0x1D 52 #define KSZ8863_PORT1_STAT0 0x1E 53 #define KSZ8863_PORT1_STAT1 0x1F 54 55 #define KSZ8863_PORT2_CTRL0 0x20 56 #define KSZ8863_PORT2_CTRL1 0x21 57 #define KSZ8863_PORT2_CTRL2 0x22 58 #define KSZ8863_PORT2_CTRL3 0x23 59 #define KSZ8863_PORT2_CTRL4 0x24 60 #define KSZ8863_PORT2_CTRL5 0x25 61 #define KSZ8863_PORT2_Q0_IG_LIMIT 0x26 62 #define KSZ8863_PORT2_Q1_IG_LIMIT 0x27 63 #define KSZ8863_PORT2_Q2_IG_LIMIT 0x28 64 #define KSZ8863_PORT2_Q3_IG_LIMIT 0x29 65 #define KSZ8863_PORT2_PHY_CTRL 0x2A 66 #define KSZ8863_PORT2_LINKMD 0x2B 67 #define KSZ8863_PORT2_CTRL12 0x2C 68 #define KSZ8863_PORT2_CTRL13 0x2D 69 #define KSZ8863_PORT2_STAT0 0x2E 70 #define KSZ8863_PORT2_STAT1 0x2F 71 72 #define KSZ8863_PORT3_CTRL0 0x30 73 #define KSZ8863_PORT3_CTRL1 0x31 74 #define KSZ8863_PORT3_CTRL2 0x32 75 #define KSZ8863_PORT3_CTRL3 0x33 76 #define KSZ8863_PORT3_CTRL4 0x34 77 #define KSZ8863_PORT3_CTRL5 0x35 78 #define KSZ8863_PORT3_Q0_IG_LIMIT 0x36 79 #define KSZ8863_PORT3_Q1_IG_LIMIT 0x37 80 #define KSZ8863_PORT3_Q2_IG_LIMIT 0x38 81 #define KSZ8863_PORT3_Q3_IG_LIMIT 0x39 82 #define KSZ8863_PORT3_STAT1 0x3F 83 84 #define KSZ8863_MAC_ADDR0 0x70 85 #define KSZ8863_MAC_ADDR1 0x71 86 #define KSZ8863_MAC_ADDR2 0x72 87 #define KSZ8863_MAC_ADDR3 0x73 88 #define KSZ8863_MAC_ADDR4 0x74 89 #define KSZ8863_MAC_ADDR5 0x75 90 #define KSZ8863_USER0 0x76 91 #define KSZ8863_USER1 0x77 92 #define KSZ8863_USER2 0x78 93 94 #define KSZ8863_GLOBAL_CTRL1_TAIL_TAG_EN BIT(6) 95 #define KSZ8863_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_ENA BIT(1) 96 97 #define KSZ8863_CTRL2_PORTn(n) (0x12 + ((n) * 0x10)) 98 #define KSZ8863_CTRL2_TRANSMIT_EN BIT(2) 99 #define KSZ8863_CTRL2_RECEIVE_EN BIT(1) 100 #define KSZ8863_CTRL2_LEARNING_DIS BIT(0) 101 102 #define KSZ8863_STAT2_PORTn(n) (0x1E + ((n) * 0x10)) 103 #define KSZ8863_STAT2_LINK_GOOD BIT(5) 104 105 #define KSZ8863_CHIP_ID0_ID_DEFAULT 0x88 106 #define KSZ8863_CHIP_ID1_ID_DEFAULT 0x31 107 #define KSZ8863_REGISTER_67 0x43 108 #define KSZ8863_SOFTWARE_RESET_SET BIT(4) 109 #define KSZ8863_SOFTWARE_RESET_CLEAR 0 110 111 enum { 112 /* LAN ports for the ksz8863 switch */ 113 KSZ8863_PORT1 = 0, 114 KSZ8863_PORT2, 115 /* SWITCH <-> CPU port */ 116 KSZ8863_PORT3, 117 }; 118 119 #define KSZ8863_REG_IND_CTRL_0 0x79 120 #define KSZ8863_REG_IND_CTRL_1 0x7A 121 #define KSZ8863_REG_IND_DATA_8 0x7B 122 #define KSZ8863_REG_IND_DATA_7 0x7C 123 #define KSZ8863_REG_IND_DATA_6 0x7D 124 #define KSZ8863_REG_IND_DATA_5 0x7E 125 #define KSZ8863_REG_IND_DATA_4 0x7F 126 #define KSZ8863_REG_IND_DATA_3 0x80 127 #define KSZ8863_REG_IND_DATA_2 0x81 128 #define KSZ8863_REG_IND_DATA_1 0x82 129 #define KSZ8863_REG_IND_DATA_0 0x83 130 131 #define KSZ8863_STATIC_MAC_TABLE_VALID BIT(3) 132 #define KSZ8863_STATIC_MAC_TABLE_OVRD BIT(4) 133 #define KSZ8863_STATIC_MAC_TABLE_USE_FID BIT(5) 134 135 #define KSZ8XXX_CHIP_ID0 KSZ8863_CHIP_ID0 136 #define KSZ8XXX_CHIP_ID1 KSZ8863_CHIP_ID1 137 #define KSZ8XXX_CHIP_ID0_ID_DEFAULT KSZ8863_CHIP_ID0_ID_DEFAULT 138 #define KSZ8XXX_CHIP_ID1_ID_DEFAULT KSZ8863_CHIP_ID1_ID_DEFAULT 139 #define KSZ8XXX_FIRST_PORT KSZ8863_PORT1 140 #define KSZ8XXX_LAST_PORT KSZ8863_PORT3 141 #define KSZ8XXX_CPU_PORT KSZ8863_PORT3 142 #define KSZ8XXX_REG_IND_CTRL_0 KSZ8863_REG_IND_CTRL_0 143 #define KSZ8XXX_REG_IND_CTRL_1 KSZ8863_REG_IND_CTRL_1 144 #define KSZ8XXX_REG_IND_DATA_8 KSZ8863_REG_IND_DATA_8 145 #define KSZ8XXX_REG_IND_DATA_7 KSZ8863_REG_IND_DATA_7 146 #define KSZ8XXX_REG_IND_DATA_6 KSZ8863_REG_IND_DATA_6 147 #define KSZ8XXX_REG_IND_DATA_5 KSZ8863_REG_IND_DATA_5 148 #define KSZ8XXX_REG_IND_DATA_4 KSZ8863_REG_IND_DATA_4 149 #define KSZ8XXX_REG_IND_DATA_3 KSZ8863_REG_IND_DATA_3 150 #define KSZ8XXX_REG_IND_DATA_2 KSZ8863_REG_IND_DATA_2 151 #define KSZ8XXX_REG_IND_DATA_1 KSZ8863_REG_IND_DATA_1 152 #define KSZ8XXX_REG_IND_DATA_0 KSZ8863_REG_IND_DATA_0 153 #define KSZ8XXX_STATIC_MAC_TABLE_VALID KSZ8863_STATIC_MAC_TABLE_VALID 154 #define KSZ8XXX_STATIC_MAC_TABLE_OVRD KSZ8863_STATIC_MAC_TABLE_OVRD 155 #define KSZ8XXX_STAT2_LINK_GOOD KSZ8863_STAT2_LINK_GOOD 156 #define KSZ8XXX_RESET_REG KSZ8863_REGISTER_67 157 #define KSZ8XXX_RESET_SET KSZ8863_SOFTWARE_RESET_SET 158 #define KSZ8XXX_RESET_CLEAR KSZ8863_SOFTWARE_RESET_CLEAR 159 #define KSZ8XXX_STAT2_PORTn KSZ8863_STAT2_PORTn 160 #define KSZ8XXX_SPI_CMD_RD KSZ8863_SPI_CMD_RD 161 #define KSZ8XXX_SPI_CMD_WR KSZ8863_SPI_CMD_WR 162 #define KSZ8XXX_SOFT_RESET_DURATION 1000 163 #define KSZ8XXX_HARD_RESET_WAIT 10000 164 165 #endif /* __DSA_KSZ8863_H__ */ 166
