1# Copyright (c) 2022 Intel Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_SERIES_INTEL_ACE
5
6config SOC_SERIES
7	string
8	default "ace"
9
10config SOC_TOOLCHAIN_NAME
11	string
12	default "intel_ace15_mtpm"
13
14config SMP
15	default y
16
17# MTL leaves the upper mapping in the same spot as cAVS, but moves the
18# lower one inexplicably.
19config XTENSA_UNCACHED_REGION
20	default 2
21
22# Parameters for gen_isr_tables.py:
23
24config 2ND_LVL_INTR_00_OFFSET
25	default 4
26
27config MULTI_LEVEL_INTERRUPTS
28	default y
29
30config MAX_IRQ_PER_AGGREGATOR
31	default 29
32
33config NUM_2ND_LEVEL_AGGREGATORS
34	default 1
35
36config 2ND_LVL_ISR_TBL_OFFSET
37	default 9
38
39config 2ND_LEVEL_INTERRUPTS
40	default y
41
42config XTENSA_TIMER
43	default n
44
45config XTENSA_TIMER_ID
46	default 0
47
48config SYS_CLOCK_HW_CYCLES_PER_SEC
49	default 393216000 if XTENSA_TIMER
50	default 38400000 if INTEL_ADSP_TIMER
51
52config SYS_CLOCK_TICKS_PER_SEC
53	default 12000
54
55config XTENSA_CCOUNT_HZ
56	default 393216000
57
58config DYNAMIC_INTERRUPTS
59	default y
60
61if LOG
62
63config LOG_BACKEND_ADSP
64	default y
65
66endif # LOG
67
68source "soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*"
69
70endif # SOC_SERIES_INTEL_ACE
71