1# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_FAMILY_ESP32
5
6# Xtensa default options for ESP32 family
7config XTENSA_RESET_VECTOR
8	default n
9
10config XTENSA_USE_CORE_CRT1
11	default n
12
13config GEN_ISR_TABLES
14	default y
15
16config GEN_IRQ_VECTOR_TABLE
17	default n
18
19config CLOCK_CONTROL
20	default y
21
22config SYS_CLOCK_HW_CYCLES_PER_SEC
23	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
24
25config XTENSA_CCOUNT_HZ
26	default SYS_CLOCK_HW_CYCLES_PER_SEC
27
28config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
29	default n
30
31if BOOTLOADER_MCUBOOT
32
33	config HAS_FLASH_LOAD_OFFSET
34		default y
35	config MCUBOOT_GENERATE_UNSIGNED_IMAGE
36		default y
37	config MCUBOOT_GENERATE_CONFIRMED_IMAGE
38		default y
39	config ROM_START_OFFSET
40		default 0x20
41
42endif # BOOTLOADER_MCUBOOT
43
44endif # SOC_FAMILY_ESP32
45