1# RV32M1 SoC RISC-V core default configuration values
2
3# Copyright (c) 2018 Foundries.io Ltd
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_OPENISA_RV32M1_RISCV32
7
8config SOC
9	default "openisa_rv32m1"
10
11# 32 from event unit + 32 * (1 + max enabled INTMUX channel)
12config NUM_IRQS
13	default 288 if RV32M1_INTMUX_CHANNEL_7
14	default 256 if RV32M1_INTMUX_CHANNEL_6
15	default 224 if RV32M1_INTMUX_CHANNEL_5
16	default 192 if RV32M1_INTMUX_CHANNEL_4
17	default 160 if RV32M1_INTMUX_CHANNEL_3
18	default 128 if RV32M1_INTMUX_CHANNEL_2
19	default 96 if RV32M1_INTMUX_CHANNEL_1
20	default 64 if RV32M1_INTMUX_CHANNEL_0
21	default 32
22
23config RISCV_GENERIC_TOOLCHAIN
24	default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr"
25	default n
26
27config RISCV_SOC_CONTEXT_SAVE
28	default y if SOC_OPENISA_RV32M1_RI5CY
29
30config RISCV_SOC_OFFSETS
31	default y
32
33config RISCV_SOC_INTERRUPT_INIT
34	default y
35
36# We need to disable the watchdog out of reset, as it's enabled by
37# default. Use the WDOG_INIT hook for doing that.
38config WDOG_INIT
39	def_bool y
40
41config SYS_CLOCK_HW_CYCLES_PER_SEC
42	default 8000000
43
44if MULTI_LEVEL_INTERRUPTS
45
46config MAX_IRQ_PER_AGGREGATOR
47	default 32
48
49config 2ND_LEVEL_INTERRUPTS
50	default y
51
52config 2ND_LVL_ISR_TBL_OFFSET
53	default 32
54
55config NUM_2ND_LEVEL_AGGREGATORS
56	default 8 if RV32M1_INTMUX_CHANNEL_7
57	default 7 if RV32M1_INTMUX_CHANNEL_6
58	default 6 if RV32M1_INTMUX_CHANNEL_5
59	default 5 if RV32M1_INTMUX_CHANNEL_4
60	default 4 if RV32M1_INTMUX_CHANNEL_3
61	default 3 if RV32M1_INTMUX_CHANNEL_2
62	default 2 if RV32M1_INTMUX_CHANNEL_1
63	default 1		# just channel 0
64
65config 2ND_LVL_INTR_00_OFFSET
66	default 24
67
68config 2ND_LVL_INTR_01_OFFSET
69	int
70	default 25
71
72config 2ND_LVL_INTR_02_OFFSET
73	int
74	default 26
75
76config 2ND_LVL_INTR_03_OFFSET
77	int
78	default 27
79
80config 2ND_LVL_INTR_04_OFFSET
81	int
82	default 28
83
84config 2ND_LVL_INTR_05_OFFSET
85	int
86	default 29
87
88config 2ND_LVL_INTR_06_OFFSET
89	int
90	default 30
91
92config 2ND_LVL_INTR_07_OFFSET
93	int
94	default 31
95
96config RV32M1_INTMUX_CHANNEL_0
97	default y
98
99config RV32M1_INTMUX_CHANNEL_1
100	default y
101
102config RV32M1_INTMUX_CHANNEL_2
103	default y
104
105config RV32M1_INTMUX_CHANNEL_3
106	default y
107
108config RV32M1_INTMUX_CHANNEL_4
109	default y
110
111config RV32M1_INTMUX_CHANNEL_5
112	default y
113
114config RV32M1_INTMUX_CHANNEL_6
115	default y
116
117config RV32M1_INTMUX_CHANNEL_7
118	default y
119
120endif # MULTI_LEVEL_INTERRUPTS
121
122endif # SOC_OPENISA_RV32M1_RISCV32
123