1 /* 2 * Copyright (c) 2021 Andrés Manelli <am@toroid.io> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** @file 8 * @brief System module to support early STM32 MCU configuration 9 */ 10 11 #include <zephyr/device.h> 12 #include <zephyr/init.h> 13 #include <soc.h> 14 #include <zephyr/arch/cpu.h> 15 #include <stm32_ll_system.h> 16 #include <stm32_ll_bus.h> 17 18 /** 19 * @brief Perform SoC configuration at boot. 20 * 21 * This should be run early during the boot process but after basic hardware 22 * initialization is done. 23 * 24 * @return 0 25 */ st_stm32_common_config(void)26static int st_stm32_common_config(void) 27 { 28 #ifdef CONFIG_LOG_BACKEND_SWO 29 /* Enable SWO trace asynchronous mode */ 30 #if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32H5X) 31 LL_DBGMCU_EnableTraceClock(); 32 #endif 33 #if !defined(CONFIG_SOC_SERIES_STM32WBX) 34 LL_DBGMCU_SetTracePinAssignment(LL_DBGMCU_TRACE_ASYNCH); 35 #endif 36 #endif /* CONFIG_LOG_BACKEND_SWO */ 37 38 #if defined(CONFIG_USE_SEGGER_RTT) 39 /* On some STM32 boards, for unclear reason, 40 * RTT feature is working with realtime update only when 41 * - one of the DMA is clocked. 42 * See https://github.com/zephyrproject-rtos/zephyr/issues/34324 43 */ 44 #if defined(__HAL_RCC_DMA1_CLK_ENABLE) 45 __HAL_RCC_DMA1_CLK_ENABLE(); 46 #elif defined(__HAL_RCC_GPDMA1_CLK_ENABLE) 47 __HAL_RCC_GPDMA1_CLK_ENABLE(); 48 #endif /* __HAL_RCC_DMA1_CLK_ENABLE */ 49 50 /* On some STM32 boards, for unclear reason, 51 * RTT feature is working with realtime update only when 52 * - one of the DBGMCU bit STOP/STANDBY/SLEEP is set 53 * See https://github.com/zephyrproject-rtos/zephyr/issues/34324 54 */ 55 #if defined(LL_APB1_GRP1_PERIPH_DBGMCU) 56 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); 57 #elif defined(LL_APB1_GRP2_PERIPH_DBGMCU) 58 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); 59 #elif defined(LL_APB2_GRP1_PERIPH_DBGMCU) 60 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); 61 #endif /* LL_APB1_GRP1_PERIPH_DBGMCU */ 62 63 #endif /* CONFIG_USE_SEGGER_RTT */ 64 65 66 #if defined(CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP) 67 68 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X) 69 HAL_EnableDBGStopMode(); 70 #else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ 71 #if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X) 72 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); 73 LL_DBGMCU_EnableDBGStopMode(); 74 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU); 75 #elif defined(SOC_SERIES_STM32F0X) 76 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); 77 LL_DBGMCU_EnableDBGStopMode(); 78 LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU); 79 #elif defined(SOC_SERIES_STM32L0X) 80 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); 81 LL_DBGMCU_EnableDBGStopMode(); 82 LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU); 83 #else /* all other parts */ 84 LL_DBGMCU_EnableDBGStopMode(); 85 #endif 86 #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ 87 88 #else 89 90 /* keeping in mind that debugging draws a lot of power we explcitly disable when not needed */ 91 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X) 92 HAL_DisableDBGStopMode(); 93 #else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ 94 #if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X) 95 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); 96 LL_DBGMCU_DisableDBGStopMode(); 97 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU); 98 #elif defined(SOC_SERIES_STM32F0X) 99 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); 100 LL_DBGMCU_DisableDBGStopMode(); 101 LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU); 102 #elif defined(SOC_SERIES_STM32L0X) 103 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); 104 LL_DBGMCU_DisableDBGStopMode(); 105 LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU); 106 #else /* all other parts */ 107 LL_DBGMCU_DisableDBGStopMode(); 108 #endif 109 #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */ 110 111 #endif /* CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP */ 112 113 return 0; 114 } 115 116 SYS_INIT(st_stm32_common_config, PRE_KERNEL_1, 1); 117
