1 /* 2 * Copyright (c) 2017 Google LLC. 3 * Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef _ATMEL_SAMD_SOC_H_ 9 #define _ATMEL_SAMD_SOC_H_ 10 11 #ifndef _ASMLANGUAGE 12 13 #define DONT_USE_CMSIS_INIT 14 15 #include <zephyr/types.h> 16 17 #if defined(CONFIG_SOC_PART_NUMBER_SAMD21E15A) 18 #include <samd21e15a.h> 19 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E16A) 20 #include <samd21e16a.h> 21 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E17A) 22 #include <samd21e17a.h> 23 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E18A) 24 #include <samd21e18a.h> 25 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G15A) 26 #include <samd21g15a.h> 27 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G16A) 28 #include <samd21g16a.h> 29 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G17A) 30 #include <samd21g17a.h> 31 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G17AU) 32 #include <samd21g17au.h> 33 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G18A) 34 #include <samd21g18a.h> 35 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G18AU) 36 #include <samd21g18au.h> 37 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J15A) 38 #include <samd21j15a.h> 39 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J16A) 40 #include <samd21j16a.h> 41 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J17A) 42 #include <samd21j17a.h> 43 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J18A) 44 #include <samd21j18a.h> 45 #else 46 #error Library does not support the specified device. 47 #endif 48 49 #endif /* _ASMLANGUAGE */ 50 51 #include "adc_fixup_sam0.h" 52 #include "../common/soc_port.h" 53 #include "../common/atmel_sam0_dt.h" 54 55 /** Processor Clock (HCLK) Frequency */ 56 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 57 58 /** Master Clock (MCK) Frequency */ 59 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 60 61 /** Known values */ 62 #define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 63 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 64 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 65 #define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 66 #define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 67 #define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 68 69 /** GCLK1 source frequency selector */ 70 #if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) 71 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 72 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) 73 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 74 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) 75 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 76 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) 77 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 78 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) 79 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ 80 #else 81 #error Unsupported GCLK1 clock source. 82 #endif 83 84 /** Dividers and frequency for GCLK0 */ 85 #define SOC_ATMEL_SAM0_GCLK0_DIV \ 86 (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) 87 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 88 89 /** DFLL48M output frequency */ 90 #define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ 91 (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) 92 93 /** Dividers and frequency for GCLK1 */ 94 #define SOC_ATMEL_SAM0_GCLK1_DIV \ 95 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) 96 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ 97 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) 98 99 /** DFLL48M output multiplier */ 100 #define SOC_ATMEL_SAM0_DFLL48M_MUL \ 101 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) 102 103 /** Frequency for GCLK2 */ 104 #define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 105 106 /** Dividers and frequency for GCLK3 */ 107 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 108 #define SOC_ATMEL_SAM0_GCLK3_DIV \ 109 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) 110 111 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 112 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 113 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 114 115 #endif /* _ATMEL_SAMD_SOC_H_ */ 116
