1 /* 2 * Copyright (c) 2018 Sean Nyekjaer 3 * Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef _ATMEL_SAMD_SOC_H_ 9 #define _ATMEL_SAMD_SOC_H_ 10 11 #ifndef _ASMLANGUAGE 12 13 #define DONT_USE_CMSIS_INIT 14 15 #include <zephyr/types.h> 16 17 #if defined(CONFIG_SOC_PART_NUMBER_SAMD20E14) 18 #include <samd20e14.h> 19 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E15) 20 #include <samd20e15.h> 21 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E16) 22 #include <samd20e16.h> 23 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E17) 24 #include <samd20e17.h> 25 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E18) 26 #include <samd20e18.h> 27 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G14) 28 #include <samd20g14.h> 29 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G15) 30 #include <samd20g15.h> 31 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G16) 32 #include <samd20g16.h> 33 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17) 34 #include <samd20g17.h> 35 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17U) 36 #include <samd20g17u.h> 37 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18) 38 #include <samd20g18.h> 39 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18U) 40 #include <samd20g18u.h> 41 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J14) 42 #include <samd20j14.h> 43 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J15) 44 #include <samd20j15.h> 45 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J16) 46 #include <samd20j16.h> 47 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J17) 48 #include <samd20j17.h> 49 #elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J18) 50 #include <samd20j18.h> 51 #else 52 #error Library does not support the specified device. 53 #endif 54 55 #endif /* _ASMLANGUAGE */ 56 57 #include "adc_fixup_sam0.h" 58 #include "../common/soc_port.h" 59 #include "../common/atmel_sam0_dt.h" 60 61 /** Processor Clock (HCLK) Frequency */ 62 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 63 64 /** Master Clock (MCK) Frequency */ 65 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 66 67 /** Known values */ 68 #define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 69 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 70 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 71 #define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 72 #define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 73 #define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 74 75 /** GCLK1 source frequency selector */ 76 #if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) 77 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 78 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) 79 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 80 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) 81 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 82 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) 83 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 84 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) 85 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ 86 #else 87 #error Unsupported GCLK1 clock source. 88 #endif 89 90 /** Dividers and frequency for GCLK0 */ 91 #define SOC_ATMEL_SAM0_GCLK0_DIV \ 92 (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) 93 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 94 95 /** DFLL48M output frequency */ 96 #define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ 97 (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) 98 99 /** Dividers and frequency for GCLK1 */ 100 #define SOC_ATMEL_SAM0_GCLK1_DIV \ 101 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) 102 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ 103 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) 104 105 /** DFLL48M output multiplier */ 106 #define SOC_ATMEL_SAM0_DFLL48M_MUL \ 107 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) 108 109 /** Frequency for GCLK2 */ 110 #define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 111 112 /** Dividers and frequency for GCLK3 */ 113 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 114 #define SOC_ATMEL_SAM0_GCLK3_DIV \ 115 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) 116 117 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 118 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 119 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 120 121 #endif /* _ATMEL_SAMD_SOC_H_ */ 122
