1/*
2 * Copyright 2018 Foundries.io Ltd
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <riscv/openisa/rv32m1.dtsi>
7
8/ {
9	aliases {
10		intmux = &intmux1;
11		system-lptmr = &lptmr2;
12	};
13
14	cpus {
15		/delete-node/ cpu@0;
16	};
17};
18
19&m0_flash {
20	partitions {
21		compatible = "fixed-partitions";
22		#address-cells = <1>;
23		#size-cells = <1>;
24
25		/* This configuration assumes the Arm cores are disabled, as
26		 * these base addresses contain the Arm core vector tables if
27		 * they are used.
28		 */
29
30		zero_riscy_code_partition: partition@1000000 {
31			reg = <0x01000000 0x0003ff00>;
32		};
33
34		zero_riscy_vector_partition: partition@3ff00 {
35			reg = <0x0003ff00 0x100>;
36		};
37	};
38};
39
40/*
41 * INTMUX channels below are somewhat arbitrary.
42 *
43 * The peripherals are all placed in channel 0. This can be overridden with
44 * overlays, e.g. to manage IRQ priorities, and it will Just Work, but using
45 * fewer channels here allows disabling unused ones in Kconfig, making the
46 * binary smaller.
47 *
48 * Each enabled channel requires 256 bytes in _sw_isr_table, so the savings for
49 * disabling channels can add up.
50 */
51
52/delete-node/ &intmux0;
53
54&intmux1 {
55	status = "okay";
56};
57
58&intmux1_ch0 {
59	interrupt-parent = <&event1>;
60	status = "okay";
61};
62
63&intmux1_ch1 {
64	interrupt-parent = <&event1>;
65};
66
67&intmux1_ch2 {
68	interrupt-parent = <&event1>;
69};
70
71&intmux1_ch3 {
72	interrupt-parent = <&event1>;
73};
74
75&intmux1_ch4 {
76	interrupt-parent = <&event1>;
77};
78
79&intmux1_ch5 {
80	interrupt-parent = <&event1>;
81};
82
83&intmux1_ch6 {
84	interrupt-parent = <&event1>;
85};
86
87&intmux1_ch7 {
88	interrupt-parent = <&event1>;
89};
90
91&lptmr0 {
92	interrupt-parent = <&intmux1_ch0>;
93	interrupts = <6>;
94};
95
96&lptmr1 {
97	interrupt-parent = <&intmux1_ch0>;
98	interrupts = <7>;
99};
100
101&lptmr2 {
102	interrupt-parent = <&event1>;
103	interrupts = <14>;
104};
105
106&gpioa {
107	interrupt-parent = <&intmux1_ch0>;
108	interrupts = <25>;
109};
110
111&gpiob {
112	interrupt-parent = <&intmux1_ch0>;
113	interrupts = <26>;
114};
115
116&gpioc {
117	interrupt-parent = <&intmux1_ch0>;
118	interrupts = <27>;
119};
120
121&gpiod {
122	interrupt-parent = <&intmux1_ch0>;
123	interrupts = <28>;
124};
125
126&gpioe {
127	interrupt-parent = <&event1>;
128	interrupts = <21>;
129};
130
131&lpuart0 {
132	interrupt-parent = <&intmux1_ch0>;
133	interrupts = <21>;
134};
135
136&lpuart1 {
137	interrupt-parent = <&intmux1_ch0>;
138	interrupts = <22>;
139};
140
141&lpuart2 {
142	interrupt-parent = <&intmux1_ch0>;
143	interrupts = <23>;
144};
145
146&lpuart3 {
147	interrupt-parent = <&event1>;
148	interrupts = <20>;
149};
150
151&lpi2c0 {
152	interrupt-parent = <&intmux1_ch0>;
153	interrupts = <13>;
154};
155
156&lpi2c1 {
157	interrupt-parent = <&intmux1_ch0>;
158	interrupts = <14>;
159};
160
161&lpi2c2 {
162	interrupt-parent = <&intmux1_ch0>;
163	interrupts = <15>;
164};
165
166&lpi2c3 {
167	interrupt-parent = <&event1>;
168	interrupts = <16>;
169};
170
171&lpspi0 {
172	interrupt-parent = <&intmux1_ch0>;
173	interrupts = <18>;
174};
175
176&lpspi1 {
177	interrupt-parent = <&intmux1_ch0>;
178	interrupts = <19>;
179};
180
181&lpspi2 {
182	interrupt-parent = <&intmux1_ch0>;
183	interrupts = <20>;
184};
185
186&lpspi3 {
187	interrupt-parent = <&event1>;
188	interrupts = <19>;
189};
190
191&generic_fsk {
192	interrupt-parent = <&intmux1_ch0>;
193	interrupts = <17>;
194};
195
196&tpm0 {
197	interrupt-parent = <&intmux1_ch0>;
198	interrupts = <8>;
199};
200
201&tpm1 {
202	interrupt-parent = <&intmux1_ch0>;
203	interrupts = <9>;
204};
205
206&tpm2 {
207	interrupt-parent = <&intmux1_ch0>;
208	interrupts = <10>;
209};
210
211&tpm3 {
212	interrupt-parent = <&event1>;
213	interrupts = <15>;
214};
215
216&trng {
217	interrupt-parent = <&event1>;
218	interrupts = <12>;
219};
220