1# Copyright 2022-2023 NXP
2#
3# SPDX-License-Identifier: Apache-2.0
4
5description: NXP S32 SIUL2 External Interrupts Request controller
6
7compatible: "nxp,s32-siul2-eirq"
8
9include: [interrupt-controller.yaml, pinctrl-device.yaml, base.yaml]
10
11properties:
12  reg:
13    required: true
14
15  reg-names:
16    required: true
17
18  pinctrl-0:
19    required: true
20
21  pinctrl-names:
22    required: true
23
24  filter-prescaler:
25    type: int
26    description: |
27      Setting the prescaler which selects the clock for all digital filters.
28      Valid range: 0 - 15.
29
30  interrupt-names:
31    description: |
32      For platforms that external interrupt lines belong to different interrupt
33      IDs (i.e. there is no single interrupt handler for all the lines), this
34      property is used by the shim driver to determine the ISR name as defined
35      by the HAL.
36
37      The naming must follow: <from-line-number>_<to-line-number>, for example:
38      interrupt-names = "0_7", "8_15", "16_23", "24_31";
39
40child-binding:
41  description: |
42    NXP S32 SIUL2 External Interrupt line configuration. For each
43    interrupt line that has specific requirements about digital
44    glitch filter, a node using this binding must be added, the
45    name must be "line_<line_number>". For example:
46
47      line_0: line_0 {
48          filter-enable;
49          filter-counter = <5>;
50      };
51
52    If the controller has no child node, the digital filter will be
53    disabled for all external interrupt lines.
54
55  properties:
56    filter-enable:
57      type: boolean
58      required: true
59      description: |
60        Enable digital glitch filter to filter out glitches on the input pad.
61
62    filter-counter:
63      type: int
64      required: true
65      description: |
66        Configuring the filter counter associated with digital glitch filter.
67        Valid range: 0 - 15.
68
69interrupt-cells:
70  - gpio-pin
71  - eirq-line
72